8/10/2019 srcode http://slidepdf.com/reader/full/srcode 1/87 Abstract:This document covers the details of firmware implemented in FPGA on WG-DPEC-1. !oard. WG-DPEC-1. !oard acts as data ac"uisition and si#nal processin# unit to achieve closed loop functionalit$ of F%G. The phase-error data is received throu#h the P&'FET output of C(F%G s$stem) it is demodulated and used to #enerate phase-error-compensation si#nal to achieve closed loop functionalit$ of the s$stem. FPGA is used in interfacin# with various components) performin# di#ital si#nal processin# functions and communicatin# with user interface. 1
Transcript
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Abstract:
This document covers the details of firmware implemented in FPGA on WG-DPEC-1. !oard.WG-DPEC-1. !oard acts as data ac"uisition and si#nal processin# unit to achieve closed loopfunctionalit$ of F%G. The phase-error data is received throu#h the P&'FET output of C(F%G s$stem) it isdemodulated and used to #enerate phase-error-compensation si#nal to achieve closed loop functionalit$ of the s$stem. FPGA is used in interfacin# with various components) performin# di#ital si#nal processin#functions and communicatin# with user interface.
1.1 PURPOSE.................................................................................................................................................. 91.2 SCOPE...................................................................................................................................................... 91.3 LIST OF ABBREVIATIONS............................................................................................................................ 9
Lst 56r7sFi#ure 1> loc dia#ram of s$stem............................................................................................................... 11Fi#ure +> Dia#ram showin# all the interfaces of FPGA on WG-DPEC-1. !oard.........................................18Fi#ure /> FPGA !ased si#nal processin#....................................................................................................+1Fi#ure 8> Component identification..............................................................................................................+/Fi#ure *> loc dia#ram of Cloc #eneration module..................................................................................+6Fi#ure 9> 83<B) +3<B Cloc #eneration flow............................................................................................./
Fi#ure 6> +7<B) 17<B cloc #eneration flow......................................................................................./+Fi#ure > loc dia#ram of ate update module........................................................................................./8Fi#ure 4> cl*<B #eneration flow............................................................................................................ /9Fi#ure 1> loc dia#ram of eference si#nal %3.................................................................................../Fi#ure 11> loc dia#ram of ADC data sampler...........................................................................................81Fi#ure 1+> ADC 0ample replacement lo#ic flow..........................................................................................8/Fi#ure 1/> loc dia#ram of Demodulation multiplier..................................................................................8*Fi#ure 18> loc dia#ram of movin# avera#e filter......................................................................................86Fi#ure 1*> 0$nchronous F&F% !ased F& filter desi#n flow.........................................................................84Fi#ure 19> loc dia#ram of Gain multiplier.................................................................................................*+Fi#ure 16> loc dia#ram of 0tep-siBe inte#rator.........................................................................................**Fi#ure 1> loc dia#ram of :+pi control chain...........................................................................................*Fi#ure 14> Al#orithm for :+pi error correction..............................................................................................9
Fi#ure +> loc dia#ram of amp-si#nal #eneration module.....................................................................98Fi#ure +1> Al#orithm for amp si#nal #eneration........................................................................................99Fi#ure ++> Pipelined implementation of ramp si#nal #eneration..................................................................96Fi#ure +/> (%C7 D&AGA3 of P&C%(A;E implementation %F ,AT...................................................68Fi#ure +8> 19 deep -!it F&F%..................................................................................................................... 6Fi#ure +*> Water Tan 3odel of ucet ri#ade F&F%................................................................................Fi#ure +9> 84 F&F% usin# three 19 F&F% modules...............................................................................1Fi#ure +6> ,AT transmitter macro............................................................................................................. /Fi#ure +> Architecture of ,AT transmitter macro...................................................................................../Fi#ure +4> Timin# characteristics of ,AT T when !uffer is not full...........................................................*Fi#ure /> Timin# characteristics of ,AT T when !uffer is full.................................................................*Fi#ure /1> ,AT receiver macro.................................................................................................................9Fi#ure /+> Architecture of ,AT receiver macro.........................................................................................9
Fi#ure //> Timin# characteristics of ,AT with data present.................................................................Fi#ure /8> Timin# characteristics of ,AT when !uffer is full................................................................Fi#ure /*> 3aster slave communication scheme........................................................................................4Fi#ure /9> Accessin# Pico!laBe &nput and %utput.......................................................................................4+Fi#ure /6> Timin# characteristics of ,AT T when !uffer is not full...........................................................4+Fi#ure /> Timin# characteristics of ,AT T when !uffer is full.................................................................4/Fi#ure /4> Timin# characteristics of ,AT with data present.................................................................4/Fi#ure 8> Timin# characteristics of ,AT when !uffer is full................................................................4/Fi#ure 81> ADC data read timin#................................................................................................................. 48Fi#ure 8+> DAC timin#................................................................................................................................. 48Fi#ure 8/> Data flow dia#ram...................................................................................................................... 4*
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Lst tab87sTa!le 1> FPGA &nput?%utput si#nal connections..........................................................................................1*Ta!le +> Ta!le of offset !inar$ for 8 !its.......................................................................................................14Ta!le /> Twos complement usin# a 8-!it inte#er.........................................................................................+Ta!le 8> &nput and %utput si#nals of Cloc #eneration module.................................................................... +Ta!le *> &nput and %utput si#nals of ate-update module........................................................................... /*Ta!le 9> &nput and output si#nals of eference si#nal %3......................................................................../4
Ta!le 6> &nput and output si#nals of ADC data sampler............................................................................... 8+Ta!le > &nput and output si#nals of Demodulation multiplier.......................................................................8*Ta!le 4> &nput and output si#nals of 3ovin# avera#e filter...........................................................................8Ta!le 1> &nput and output si#nals of Gain multiplier................................................................................... */Ta!le 11> &nput and output si#nals of 0tep-siBe inte#rator...........................................................................*9Ta!le 1+> &nput and output si#nals of :+pi control chain.............................................................................. *4Ta!le 1/> &nput and %utput si#nals of amp-#eneration module.................................................................9*Ta!le 18> FPGA 3emor$ utiliBation.............................................................................................................41Ta!le 1*> e"uirement mappin#.................................................................................................................. 49Ta!le 19> FPGA resource utiliBation..........................................................................................................16Ta!le 16> FPGA Pin details........................................................................................................................ 14
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1.1 Itr6ct
1.1.1 P6r;s7
This document covers the details of firmware desi#n implemented in :irte-&& FPGA of WG-DPEC-1.!oard which is used in Di#ital Closed (oop Fi!er %ptic G$ro s$stem.
1.1.2 Sc;7The scope of this document covers the desi#n and development efforts involved in Firmware for Closed(oop DF%G. &t covers the followin# points associated with the intended s$stem) Product perspective)functional description) end users5 perspective) product functions and specifications. &t then details desi#nconstraints and assumptions and dependencies.
1.1.3 Lst abbr7<ats
ACC Accelerometer ADC Analo# to Di#ital Converter A3 Bloc Random Access !emor$C( Confi#ura!le Lo#ic BlocC(F%G Closed Loop Fi!er Optic #$ro
DAC Di#ital to Analo# Converter DC3 Di#ital Cloc !ana#er DF%G Di#ital approach Fi!er Optic #$roDPEC Di#ital Phase Estimator CardD0P Di#ital Si#nal Processor D:GA Di#itall$ controlled Varia!le #ain Amplifier FDD Firmware Desi#n DocumentFF Flip FlopF&F% First In First OutF%G Fi!er Optic #$roFPGA Field Pro#ramma!le #ate Arra$&&C &+C Inter Inte#rated-circuit Communication&' Input
TAG )oint Test Action #roup(,T Loo Up Ta!le(:D0 Low Volta#e Differential Si#nal'A Not Applica!le%,T OutputPC Personal Computer P&'FETA3 Random Access !emor$%3 Read Onl$ !emor$C& Research Centre Imarat0(D Super Luminescent Diode0P& Serial Peripheral Interface00 Specification Re"uirement Sheet
TD To Be Discussed,AT Universal As$nchronous Receiver Transmitter :<D( Ver$ <i#h 0peed &nte#rated Circuit $ardware Descriptive Lan#ua#eWG "avelet #roup
1.1.4 R77r7c7s
• WG-DPEC-1. 00 Document
• Technical specification manuals of :&TE=-&& FPGA from =ilin
• Data sheets of on-!oard components lie ADC AD08++) DAC (TC199
• 0chematic of WG-DPEC-1.
• Technical reference papers from C&
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1.1. Dc6=7t O<7r<7>
WG-DPEC-1. FPGA Firmware Desi#n Document covers the followin#
• Assumptions and dependencies
• Firmware desi#n constraints
• Technical specifications
• Desi#n description
• &mplementation details
• Eternal) internal and user interfaces
• 3emor$ 3appin#
1.2 #77ra8 D7scr;t
1.2.1 Pr6ct ;7rs;7ct<7
WG-DPEC-1. !oard acts as data ac"uisition and si#nal processin# unit to achieve closed loop
functionalit$ of F%G. This will !e used for rotation rate computation usin# F%G as a sensor.F%G wors on the principle of 0a#nac phase shift. The output of the F%G is characteriBed !$ the e"uation> -t ? 1@ cs Rt @ Bt
Where 2t is output in terms of 0a#nac phase shift in radians)t is rate of rotation in rad?sect is !iasin# si#nal
C(F%G is !iased with s"uare wave si#nal of period e"ual to transit time of the fi!er-coil.The P&'FET converts optical power) which is output of F%G to electrical si#nal. This output is s"uare wavemodulated co-sinusoidal si#nal.The modulated 0a#nac Phase shift data is received throu#h P&'FET output of C(F%G.%n-!oard 19-!it ADC will receive the data from P&'FET and will !e processed to #enerate the feed!acsi#nal for the phase modulator is #iven throu#h 19-!it DAC. This feed !ac si#nal represents phase-error-compensation si#nal to achieve closed loop functionalit$ of the s$stem.
FPGA is used in interfacin# with various components) performin# di#ital si#nal processin# functions andcommunicatin# with user interface.
The FPGA firmware mainl$ consists of followin# three sections>1 Control and cloc si#nal #eneration+ Al#orithm implementation/ Communication with eternal world Presentl$ ,AT
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Fi#ure 1> loc dia#ram of s$stem
1.3 D7s5 cstrats
1.3.1 St>ar7 cstrats
• The pin assi#nment should !e accordin# to the schematic and proper &% standard should !e set.
• Wherever possi!le the lo#ic will mae use of in !uilt features of FPGA such as !loc A3) DC3)
macros constructed with FPGA primitives etc
1.3.2 $ar>ar7 cstrats
• Cloc should not contain #litches.
• :olta#e levels at &?% should match with the interface.
• Power suppl$ should !e ripple free.
1.4 $ar>ar7 t7rac7 7ta8s
1.4.1 It7rac7 a5ra=
Fi#ure +> Dia#ram showin# all the interfaces of FPGA on WG-DPEC-1. !oard
S8.N Prt a=7 Dr7ct T;7 , >t D7scr;t
1 C(7 &' 0TDH(%G&C * 3<B cloc from thecr$stal oscillator
+ ,ATHC(7 &' 0TDH(%G&C 1.8/+ 3<B cloc from thecr$stal oscillator
/ E0ETHT%PH' &' 0TDH(%G&C <ardware eset to FPGA
8 ADCHDATA &' 0TDH(%G&CH:ECT%1*D%W'T%
19-!it data input from ADC
* ADCHE0ET %,T 0TDH(%G&C eset control to ADC
4
WG-DPEC-1.0
Fiber
Optic
Gyroscope
HOST
ADCAD08++
FP#A/C2V20*4CS144
Cr$stal%scillator
* 3<B
Cr$stal%scillator
1.8/+ 3<B
=CF80Confi#urationFlash?TAG
&nterface
esetcircuit
DAC1(TC199
DAC+(TC199
0+/+?8++interface
3A=/19+
Temp-erature0ensors
(:D0
Power0uppl$
&nterface to ACC !oard
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9 ADCHC0 %,T 0TDH(%G&C Chip-select control to ADC
6 ADCH,02 &' 0TDH(%G&C us$-status input from ADC
ADCHPD+ %,T 0TDH(%G&C Power-Down control to ADC
4 ADCHD %,T 0TDH(%G&C 0$nchroniBation pulse to ADC for parallel output
1 ADCHC%':0T %,T 0TDH(%G&C Convert-start control to ADC
11 TDHT%P %,T 0TDH(%G&C Transmit to 0+/+ ,AT &C
1+ DHT%P &' 0TDH(%G&C eceive from 0+/+ ,AT&C
1/ TE0T1 %,T 0TDH(%G&C %n-!oard test point
18 TE0T+ %,T 0TDH(%G&C %n-!oard test point
1* DAC1HC(7 %,T 0TDH(%G&C Cloc si#nal to DAC1
19 DATAHT%HDAC1 %,T 0TDH(%G&CH:ECT%1*D%W'T%
19-!it data to DAC1
16 DAC+HC(7 %,T 0TDH(%G&C Cloc si#nal to DAC+
1 DATAHT%HDAC+ %,T 0TDH(%G&CH:ECT%1*D%W'T%
19-!it data to DAC+
Ta!le 1> FPGA &nput?%utput si#nal connections
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The followin# :<D( code of FPGA specifies the eternal input @ output connections
ADC interface>19-!it parallel data received from ADC. This data represents the #$ro phase error. Cloc and reset to ADCis driven !$ FPGA. Data read s$nchroniBation control is driven !$ FPGA.
DAC1 interface>19-!it parallel data output from FPGA to DAC. This data represents the phase error compensatin# si#nal.Cloc si#nal to DAC is driven !$ FPGA.
DAC+ interface>19-!it parallel data output from FPGA to DAC. This data represents the !ias s"uare wave si#nal.Cloc si#nal to DAC is driven !$ FPGA
0+/+?08++ interface>Communication with PC application software is implemented on ,AT. FPGA actin# as 3aster of communication transfers the desired data to PC. Confi#uration parameters from PC are received on theserial line.
Cr$stal %scillator>*3<B and 1.8/+3<B oscillators suppl$ cloc inputs to FPGA. These master clocs are used further toderive internal clocs used in si#nal processin# !$ FPGA features.
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Confi#uration flash interface>%n-!oard =ilin platform serial flash is used to confi#ure the FPGA after ever$ power-on.
Temperature sensor interface>&+C !ased readin# of temperature data !oth %n-!oard sensor and other connectors.
ACC !oard interface>
0P& !ased data transfer !etween WG-DPEC-1. !oard and WG-F%GACC-+..
1.4.2 C==6cat ;rtc8s
1.4.2.1 UART
The ,AT transmitter?receiver macro is provided !$ =ilin. This is havin# the followin#characteristics>
1. 1 start !it+. data !its/. 1 parit$ !it8. 1 stop !it.This macro also contains a 19 !$te F&F%. The F&F% siBe can also etenda!le !$ cascadin# more
!ucet !ri#ade F&F%s.
An as$nchronous transmitter @ receiver means transmitter @ receiver are not s$nchroniBed.<owever the$ do !oth utiliBe a timin# reference which is of a suita!le tolerance to allow the serial transfer of each !$te of data.
The data transmitted seriall$ (0 first at a #iven !it rate A,D rate which is nown !$ thetransmitter and receiver. 0ince the transmitter can start sendin# data at an$ time) the receiver needs amethod of identif$in# when the first (0 is !ein# sent. This is achieved !$ the transmitter sendin# anactive low start si#nal for the duration of one !it.
The receiver uses the fallin# ed#e of the start !it to !e#in an internal timin# circuit. This timin# isthen used to sample the value of the serial input at a point which is approimatel$ at the mid-point of eachdata !it. This is where the data should !e most sta!le. After the PA&T2 !it has !een sampled) the receiver checs to see if the transmitted stop nit hi#h is the value epected which helps confirm correct operation.
0ince the receiver re-s$nchroniBes starts the internal timin# circuit to the fallin# ed#e of eachstart !it) the timin# of the transmitter and receiver onl$ need to !e the same to a tolerance of L a !it periodin ever$ 1 !it periods. This *M accurac$ is reall$ no issue to achieve in an$ di#ital s$stem.
&n common with man$ ,AT solutions) these macros epect that a timin# reference !e provided inthe form of an ena!le si#nal NenH19HH!aud5) which is applied at 19 times the !it rate.
The normal status of ,AT serial line is active <&G<. &n this wa$ a new start !it is identified !$ itsfallin# ed#e.
1.4.3 Data r=ats
1.4.3.1 Os7t bar r=at
%ffset !inar$ is a di#ital codin# scheme where all-Bero corresponds to the minimal ne#ative value and all-
one to the maimal positive value. There is no standard for offset !inar$) !ut most often the JBeroJ value isrepresented !$ a 1 in the most si#nificant !it and Bero in all other !its.
%ffset !inar$ is often used in di#ital si#nal processin# D0P. 3ost A?D Analo# to Di#ital and D?A Di#italto Analo# chips are unipolar) which means that the$ cannot handle !ipolar si#nals si#nals with !othpositive and ne#ative values. A simple solution to this is to !ias the analo# si#nals with a DC offset e"ualto half of the A?D and D?A converters ran#e. The resultin# di#ital data then ends up !ein# in offset !inar$format.
Bar c7 D7c=a8 c7
1111 6
111 9
111 *
11 8
111 /
11 +
11 1
1
111 O1
11 O+
11 O/
1 O8
11 O*
1 O9
1 O6
O
Ta!le +> Ta!le of offset !inar$ for 8 !its
%ffset !inar$ ma$ !e converted into twos complement !$ invertin# the most si#nificant !it. For eample)with !it values) the offset !inar$ value ma$ !e =%ed with in order to convert to twos complement.
1.4.3.2 T>s c=;87=7t r=at
The twos complement of a !inar$ num!er is defined as the value o!tained !$ su!tractin# the num!er froma lar#e power of two specificall$) from +N for an N -!it twos complement. The twos complement of thenum!er then !ehaves lie the ne#ative of the ori#inal num!er in most arithmetic) and it can coeist withpositive num!ers in a natural wa$. A twos-complement s$stem or twos-complement arithmetic is a s$stem in which ne#ative num!ers arerepresented !$ the twos complement of the a!solute valueK this s$stem is the most common method of
representin# si#ned inte#ers on computers. &n such a s$stem) a num!er is ne#ated converted frompositive to ne#ative or vice versa !$ computin# its twos complement. An '-!it twos-complement numerals$stem can represent ever$ inte#er in the ran#e O+'O1 to +'O1O1.The twos-complement s$stem has the advanta#e of not re"uirin# that the addition and su!traction circuitr$eamine the si#ns of the operands to determine whether to add or su!tract. This propert$ maes thes$stem !oth simpler to implement and capa!le of easil$ handlin# hi#her precision arithmetic. Also) Berohas onl$ a sin#le representation) o!viatin# the su!tleties associated with ne#ative Bero) which eists inones-complement s$stems.
The a!ove dia#ram is the proposed approach to #enerate the feed !ac si#nal for compensatin# thephase error of C(F%G s$stem.
18
D<7 b +Q1* >t bt s787ct89>1* t r76c7
t7 5a
#a!68t;87r
S5 7t77 t 32 btD<7 b 1' >t bt s787ct 29:4 t r76c7
t7 5a
8
S5 7t77
#a r=UART
/+
C8G2!C8G2!
19
F&F% of depthN'5 samples'I19
/
S5 7t77
S5 7t77
/
C8G2!
RE#
/
S5 7t77
/
19
C8G2!
ADC Data2s c=;87=7t r=at
C8G2!
=19
RE#
201'
RO!
Fied %ffsetfrom ,AT/+
Dead!and Compenstaion Amplitude from ,AT
Epected to !e with in /+ !itran#e
/+
SH6ar7 >a<7: 0 6t cc87 a;r5ra==ab87 ;7r a a=;8t67
r DEADBAND c=;7sat
U;;7r Tr7s8
/+
/+
/+
Ra=;#77ratr
/+
/+
L>7r Tr7s8
Fied 0tep-siBefrom ,AT
/+
30
RE#
TDAC
19
C8200% C8200% /+
S5 7t77
S5 7t77
C8200%
//
RE#
!U/
//
//
//
//
//
0tep-siBe selectionfrom ,AT
19
U;;7r 1'bts
D<7b 2J1'
t7tract1' bt
31:1'
RE#
86
32:0
C8200%
86
+ms pulseAs$nc-C(EA
32 bt Data tPC <7r Uart
D<7 b 2J9as acc6=68at7400 t=7s 40:9
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The rate data comin# from ADC 19 !its is demodulated and passed throu#h F& filter. The result ismultiplied with #ain factor received throu#h ,AT. The multiplier output is inte#rated with the transit timereference to #enerate final step siBe) which will !e used for #eneration of ramp. This ramp si#nal and the!iasin# si#nal s"uare wave of 1 7<B and pea to pea amplitude of pi?+ volts are used as controlsi#nals for C(F%G.
19. ,AT Transmitter controller @16. &nte#rated top module.
19
Cloc #eneration module
Data samplin# cloc ,art clocTransit cloc
Cloc #eneration module
Data samplin# cloc ,art clocTransit cloc
Demodulator
multiplier
ampsi#nal#enera
tor
iassi#nal#enera
tor
ADCData
eference
0"uare
Wave
3ovin# AccumulationFilter
Gain3ultipli
er
Dead-!and
compensator
ateinte#ra
tor
(oopGain
Dead-!andCompensation
Amplitude
Datato
DAC-+
Datato
DAC-1
ateupdatemodule
@
,AT
P&C%-(A;E
Pea-pea
amplitude
DatatoPC
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1.'.2 F6cts !ar C=;7ts
1.'.2.1 C8c 577rat =687
This desi#n module supplies the necessar$ cloc si#nals to all other desi#n modules. &nput to this moduleis the cloc si#nal from the Cr$stal %scillator. ,sin# FPGA resource lie DC3 and some mod-counter lo#icnecessar$ cloc si#nals are derived.
1.'.2.2 Rat7 6;at7 =687This desi#n module #enerates timin# control si#nals used to upload data to PC. ased on the timin#control si#nals #enerated) step-siBe data is avera#ed. &n the current desi#n) +ms avera#ed data is sent toPC usin# these control si#nals. %ne of these control si#nals is used to #enerate the compensation s"uarewave si#nal used in Dead-!and compensation.
1.'.2.3 R77r7c7 s5a8 RO!
This desi#n module #enerates reference si#nal used for demodulatin# data from ADC. This module is amemor$ initialiBed with /+ !it data representin# 1 and -1 samples. The memor$ is + deep and read atdata samplin# cloc to s$nchroniBe with ADC data samplin#. Address to the %3 is #enerated !ased on3od-+ ,p-counter from the inte#rated top module. <alf of the memor$ is initialiBed with 1 samples andthe other half with -1 samples representin# a s"uare wave reference si#nal.
1.'.2.4 ADC ata sa=;87r
This module samples 19-!it data from ADC with data-samplin# cloc +3<B. 0amplin# data is ena!ledwith counter !ased control si#nal. &t is o!served some spie occurrence in the P&'FET output data) inorder to avoid these unwanted spie samples) the ADC output samples around the spie occurrences arei#nored and are replaced with the latest received valid data sample. This selection of sample replacementis user confi#ura!le. ,ser can enter the sample num!er) !$ which the entered sample num!er and thefollowed immediate + samples are replaced with the latest received valid data sample.
1.'.2. D7=68at =68t;87r
The multiplier used here is FPGA resource primitive. &t is confi#ured to have si#ned 19-!its inputs andsi#ned /+-!it output. 3odulated data from P&'FET is received !$ FPGA throu#h ADC) then demodulatedusin# this multiplier with the reference s"uare wave samples. With this multiplier) ADC samples aredemodulated over ever$ su!se"uent two transit-time which results as the difference !etween ADCsamples of those two transit-times. %ver a period of two transit-time) ever$ first 1 ADC data samples aremultiplied with 1 reference si#nal N15 samples) net 1 ADC data samples are multiplied with 1reference si#nal N-15 samples.
1.'.2.' !<5 a<7ra57 8t7r
The filter is used to smooth the closed loop control s$stem response) which improves the threshold andresolution characteristics of the s$stem. Thou#h it is named is movin# avera#in# filter) actualimplementation results as 3ovin# accumulation filter followed with !inar$ division in +s powers.$ this filterin# the deviation in error can !e minimiBed.
1.'.2.( #a =68t;87r
The multiplier used here is FPGA resource. &t is used to control the #ain of the filtered output error si#nalamplitude. Gain is controlled !$ fractional multiplication of si#nal. &t is a si#ned multiplier. ,ser can selectthe fractional value over ,AT with which si#nal to !e multiplied. &t also controls the fastness of the loopclosure of the s$stem.
1.'.2.& D7a*ba c=;7satr
The closed loop operation suffers from a locup near rotation rates around Bero. The locup is alsoreferred to as dead-!and) dead-Bone) or a re#ion of insta!ilit$. &t is a ran#e of rates where the sensitivit$ of the #$ro reduces to Bero such that #$ro no lon#er senses rotation rate.This dead-!and error can !e eliminated !$ the addition of a periodic compensation si#nal) at the input tothe step-siBe inte#rator.
1.'.2.9 St7;*sK7 t75ratr This is an &nte#ral controller. This module inte#rates the #ain controlled error output for ever$ transit time.The inte#rated output will !e used for the phase error compensation si#nal #eneration. &n a closed loop
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s$stem) when the error input is of hi#h?low amplitude) the compensation si#nal of proportional amplitudewill !e #enerated. <ence this inte#ration at ever$ transit time never overflows. The inte#rated output is alsoupload to PC over a selected period.
1.'.2.10 V2; ctr8 ca
The value :+pi corresponds to the pea-pea amplitude of the feed !ac compensation si#nal ampsi#nal. The purpose of this controller is to correct the error in this amplitude at ever$ ramp-reset instance.
1.'.2.11 Ra=; s5a8 577rat
This module is the feed!ac phase error compensation si#nal #enerator. The step-siBe data is inte#ratedwith reference to the upper and lower thresholds and results ramp si#nal whose fre"uenc$ is proportionalto the step-siBe.
1.'.2.12 Bas s5a8 577rat
0"uare wave ias si#nal of 17<B fre"uenc$ is #enerated. The !ias si#nal amplitude is proportional tothe ramp si#nal amplitude. The !ias si#nal time period is proportional to the transit time period.
1.'.2.13 St7; sK7 a<7ra57 =687
This module accumulates the final step-siBe data over a selective period !$ the user) then avera#es and
this output will !e fed to ,art controller for transmission.
1.( D7s5 7ta8s
1.(.1 C8c 577rat =687
This desi#n module supplies the necessar$ cloc si#nals to all other desi#n modules. &nput to this moduleis the cloc si#nal from the Cr$stal %scillator. ,sin# FPGA resource lie DC3 and some mod-counter lo#icnecessar$ cloc si#nals are derived.
Ta!le 8> &nput and %utput si#nals of Cloc #eneration module
1.(.1.2 C7 7scr;t
&n this module) instantiation of the DC3 to #enerate the desired cloc si#nals is shown here.The #lo!al reset input to the FPGA from the !oard is active-low. The DC3 reset input polarit$ should !eactive-hi#h) hence the #lo!al reset input is inverted and fed as reset to DC3.The cloc input to the DC3 is *3<B cloc from the on-!oard cr$stal oscillator. %utputs of the DC3 are83<B and !uffered *3<B clocs.The (%C7EDH0 si#nal output from the DC3 validates the output cloc sta!ilit$ of the DC3. This outputsi#nal state is initiall$ low after power-on) !ecomes hi#h when DC3 #ives sta!le cloc output. This si#nalalon# with #lo!al reset si#nal is used to #enerate internal reset 0TH(C7H'Hint si#nal for all other modules of the desi#n to ensure !etter performance.
&nstHclH#en> clH#enP%T 3AP C(7&'H&' I C(7) -- * 3<B %sc cl0TH&' I E0ETHT%PHP)C(7F=H%,T I clH83Hint) -- 8 3<BC(7&'H&,FGH%,T I clH*3Hint) -- * 3<B(%C7EDH%,T I (%C7EDH0K
-------------------------------------------------------------------clH83 SI clH83HintKclH*3 SI clH*3HintK-------------------------------------------------------------------0TH(C7H'Hint SI E0ETHT%PH' and (%C7EDH0KE0ETH(%C7EDH' SI 0TH(C7H'HintK-------------------------------------------------------------------
These DC3 output cloc si#nals are used to #enerate the other desired fre"uencies !ased on 3od-counters.From *3<B cloc si#nal) +*3<B is derived usin# To##le-flip-flop functionalit$.
elsif clH+7H,Fevent and clH+7H,F I1 thenclH17Hint SI not clH17HintK
end ifKend processK
clH17 SI clH17HintK-------------------------------------------------------------------
1.(.2 Rat7 6;at7 =687
This desi#n module #enerates timin# control si#nals used to upload data to PC. ased on the timin#control si#nals #enerated) step-siBe data is avera#ed. &n the current desi#n) +ms avera#ed data is sent toPC usin# these control si#nals. %ne of these control si#nals is used to #enerate the compensation s"uarewave si#nal used in Dead-!and compensation.
* clH*<B %,T 0TDH(%G&C &nte#ral multiples of *<Bfre"uenc$ output used for Dead-!and compensation
9 pulseH+Hms %,T 0TDH(%G&C Pulse output once ever$inte#ral multiples of +ms
used to reset the process of accumulatin# 0tep-siBe data
while upload to PC
Ta!le *> &nput and %utput si#nals of ate-update module
1.(.2.2 C7 7scr;t
ased on the input ateH,pdateH:A( a counter is incremented at +7<B cloc. Counter increments untilits value reaches ateH,pdateH:A( and then resets.This is done to derive low fre"uenc$ si#nal inte#ral multiples of 17<B cloc. As the ateH,pdateH:A( is pro#ramma!le !$ user) the mod of the counter decides the desired lowfre"uenc$ si#nal #eneration rateHupdateHclHtmp.
,sin# this inte#ral multiples of 17<B fre"uenc$) inte#ral multiples of *7<B fre"uenc$ are #enerated sothat step-siBe data to !e uploaded to PC at +ms) 8msU..inte#ral multiples of +ms.
elsif rateHupdateHclHtmpevent and rateHupdateHclHtmp I thenclH*<BHint SI not clH*<BHintK
end ifKend processK
clH*<B SI clH*<BHintKpulseH+Hms SI clH*<BHintK---------------------------------------------------------------------
+9
3od
ateH,pdateH:A(
1counter
D flip flop
clH+7
0TH'
rateHupdateHclHtmp
clH+7
D flip flop
rateHupdateHclHtmp
0TH'
clH*<B Hint
19
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1.(.3 R77r7c7 s5a8 RO!
This desi#n module #enerates reference si#nal used for demodulatin# data from ADC. This module is amemor$ initialiBed with /+ !it data representin# 1 and -1 samples. The memor$ is + deep and read atdata samplin# cloc to s$nchroniBe with ADC data samplin#. Address to the %3 is #enerated !ased on3od-+ ,p-counter from the inte#rated top module. <alf of the memor$ is initialiBed with 1 samples andthe other half with -1 samples representin# a s"uare wave reference si#nal.
1 Cl &' 0TDH(%G&C Data samplin# cloc input to%3 to s$nchroniBe
readin# %3 with ADC data
+ Addr &' 0TDH(%G&CH:ECT%8D%W'T%
Address input to + deep%3
/ Dataout %,T 0TDH(%G&CH:ECT%/1D%W'T% Data output from the %3used to demodulate ADCsamples
+6
R77r7c7 s5a8 RO!
addr
Dataout
Cl
*
/+
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Ta!le 9> &nput and output si#nals of eference si#nal %3
1.(.3.2 C7 7scr;t
The followin# code shows initialiBation of memor$ of depth +. As shown here) 1 samples of memor$indicate 1 and the remainin# 1 samples indicate -1 samples. <ence this %3 is used to #enerate thereference s"uare wave samples which will !e used to demodulate the ADC data samples.loc memor$ resource of FPGA is used to #enerate this %3.
attri!ute A3H0T2(E > strin#Kattri!ute A3H0T2(E of %3H3E3> si#nal is J(%C7JK
----------------------------------------------------------------------- %3 contents---------------------------------------------------------------------%3H3E3 SI
The address input from the inte#rated top module is re#istered and fed to the %3.---------------------------------------------------------------------process cl!e#in
ifclevent and cl I 1 thenrHaddr SI addrKend ifK
end processK
As this is a %3 ead onl$ memor$) providin# address input to the %3 #ives out the data sample. As the address is #enerated !ased on the mod-counter) data is read continuousl$ from %3 throu#h outthe operation.---------------------------------------------------------------------Dataout SI %3H3E3convHinte#errHaddrK---------------------------------------------------------------------
+
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1.(.4 DC ata sa=;87r
This module samples 19-!it data from ADC with data-samplin# cloc +3<B. 0amplin# data is ena!ledwith counter !ased control si#nal. &t is o!served some spie occurrence in the P&'FET output data) inorder to avoid these unwanted spie samples) the ADC output samples around the spie occurence arei#nored and are replaced with the latest received valid data sample. This selection of sample replacementis user confi#ura!le. ,ser can enter the sample num!er) !$ which the entered sample num!er and thefollowed immediate + samples are replaced with the latest received valid data sample.
Ta!le 6> &nput and output si#nals of ADC data sampler
1.(.4.2 C7 7scr;t
ADC data are sampled with data-samplin# cloc +3<B. As per the present specifications of the s$stem)transit cloc fre"uenc$ is +7<B. <ence for each transit cloc) 1 samples of ADC data can !e receivedwhen sampled with +3<B.
3od-1 counter ena!leHcounter is used for this sample replacement function. ,ser selects particular sample num!er startHsampleHnum which needs to !e replaced with valid data.ena!leHadcHsample is the control #enerated !ased on which valid data will replace these unwantedsamples.When ena!leHadcHsample is low) the valid sample data replaces the current input ADC samples.
When ena!leHadcHsample is hi#h) ADC output samples are simpl$ re#istered 0ampledHADCHData.
elsif clH+3event and clH+3 I thenif ena!leHcounter I J11J then
ena!leHcounter SI others I Kelse
ena!leHcounter SI ena!leHcounter 1Kend ifK
end ifKend processK---------------------------------------------------------------------
/
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Fi#ure 1+> ADC 0ample replacement lo#ic flow
ena!leHre# SI when ena!leHcounter I startHsampleHnum else 1K
processclH+3) 0TH'!e#in
if 0TH' I thenena!leHre#Hdel SI others I 1K
elsif clH+3event and clH+3 I thenena!leHre#Hdel SI ena!leHre#Hdel @ ena!leHre#K
end ifKend processK
ena!leHadcHsample SI ena!leHre# A'D ena!leHre#Hdel A'D ena!leHre#Hdel1K---------------------------------------------------------------------processclH+3) 0TH'!e#in
if 0TH' I then0ampledHADCHData SI others I K
elsif clH+3event and clH+3 I thenif ena!leHadcHsample I 1 then
0ampledHADCHData SI ADCHDATAKend ifK
end ifKend processK---------------------------------------------------------------------
/1
D flip flop
clH+3
0TH'
0ampledHADCHData
3od -1counter
clH+38
8I
startHsampleHnum
ena!leHcounter
Dflipflop
Dflipflop
clH+3 clH+3
19
ADCHData19
19
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1.(. D7=68at =68t;87r
The multiplier used here is FPGA resource primitive. &t is confi#ured to have si#ned 19-!its inputs andsi#ned /+-!it output.
Fi#ure 1/> loc dia#ram of Demodulation multiplier
/+
D7=68at=68t;87r
0ampledHADCHData demodHmulHout
clH+3
DE3%DHEFHsi#
19
19
/+
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3odulated data from P&'FET is received !$ FPGA throu#h ADC) then demodulated usin# this multiplier with the reference s"uare wave samples DE3%DHEFHsi#.
With this multiplier) ADC samples are demodulated over ever$ su!se"uent two transit-time which results asthe difference !etween ADC samples of those two transit-time.
%ver a period of two transit-time) ever$ first 1 ADC data samples are multiplied with 1 reference si#nal
N15 samples) net 1 ADC data samples are multiplied with 1 reference si#nal N-15 samples.
1.(..1 I;6t a 6t;6t s5a8 7scr;t
S8.N Prt a=7 Dr7ct T;7 , >t D7scr;t
1 Cl &' 0TDH(%G&C +3<B Data-samplin# clocinput
+ A &' 0TDH(%G&CH:ECT%1*D%W'T%
19-!it si#ned data input.0ampledHADCHData isconnected to this port
/ &' 0TDH(%G&CH:ECT%1*
D%W'T%
19-!it si#ned data input.
DE3%DHEFHsi# isconnected to this port
8 P %,T 0TDH(%G&CH:ECT%/1D%W'T%
19-!it si#ned data output)demodHmulHout is
connected to this port
Ta!le > &nput and output si#nals of Demodulation multiplier
1.(..2 C7 7scr;t
<ere shown the instantiation of this FPGA resource in the top-level module)
&nstHdemodHmultiplier > demodHmultiplierP%T 3AP
cl I clH+3)a I 0ampledHADCHData)! I DE3%DHEFHsi#1* downto )p I demodHmulHout
K
As 19-!it ADC data are multiplied with ?-1 value) least 19 !its of the output product is the sufficientinformation.
demodHmulHoutHint SI demodHmulHout1* downto K
//
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1.(.' !<5 a<7ra57 8t7r
The filter is used to smooth the closed loop control s$stem response) which improves the threshold andresolution characteristics of the s$stem. Thou#h it is named is movin# avera#in# filter) actualimplementation results as 3ovin# accumulation filter followed with !inar$ division in +s powers.$ this filterin# the deviation in error can !e minimiBed.
18-!it data input from top-module indicatin# the !uffer
siBe used for filterin#
8 demodHmulHdata &' 0TDH(%G&CH:ECT%1*
D%W'T%
19-!it Demodulated ADC
data* F&HFilterHout %,T 0TDH(%G&CH:ECT%/1
D%W'T% /+-!it Filter output data
Ta!le 4> &nput and output si#nals of 3ovin# avera#e filter
1.(.'.2 C7 7scr;t
19-!it output demodHmulHdata from the demodulation multiplier is fed as input to F& t$pe 3ovin#avera#e filter module.This filter is an accumulation circuit) which will sum the predefined num!er of samples ' defined in thecode !$ the parameter filterHdepth Fifo depth must !e #reater than filterHdepth. At an$ point in the time the output of the filter is sum of ' most recent samples. <ere filter is worin# at+3<B Data-samplin# cloc) so in order to #et summation of inte#er num!er of wave forms of 17<B +Transit time) ' is alwa$s inte#er multiple of +) and the maimum value of ' is restricted !$ the F&F%depth. The flow dia#ram of filter is shown !elow.
Y(n) = Y(n-1) + x(n) –x(n-N)
--------------------------------------------------------------------- F& 3ovin# Avera#e filter -------------------------------------------------------------------0THP SI not 0TH'K
&nstHfifoHforHfilter > fifoHforHfilterport map
cl I cl)srst I 0THP)din I demodHmulHdata)wrHen I wrHenHfifo)rdHen I rdHenHstart)dout I demodHfifoHout)full I %PE')empt$ I %PE'
Generation of write ena!le to fifo is !ased on this counter. ,ntil counter value is /) write ena!le to fifo islow) this is the initial dela$ fied to !alance the input data path dela$.%nce write ena!le is set to hi#h) it remains continuousl$ hi#h.
#enerateHwrHen>processcl) 0TH'!e#in
if 0TH' I thencounterHforHwr SI others I K
elsif clevent and cl I 1 thenif wrHenHfifo I then
counterHforHwr SI counterHforHwr 1K
/9
Scr6sFIFO
0THP srst
demodHmulHdata din
empt$ empt$
dout demodHfifoHout
ClH+3 cl
wrHenHfifo wrHen
19
/
full full
rdHen rdHenHstart
EG
/
/
0i#neteneded to /
!it
0i#n eteneded to/ !it
ClH+3
-
AccumHDemodHout
0i#neteneded to /+
!it
/
EG
ClH+3
+ Ien
1
V11
counterHforHwr
wrHenHfifo
EG
ClH+3
18 Ien
1
FilterHdepth
counterHforHrd
rdHenHfifo
+
18
F&HFilterHout
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end ifKend ifK
end processK-------------------------------------------------------------------wrHenHfifo SI 1 when counterHforHwr I J11J else
Generation of read ena!le to fifo is !ased on this counter. ead ena!le to fifo is initiall$ low) once writeena!le to fifo !ecomes hi#h and completes writin# of data locations of specified depth ') readin# from fifois ena!led.This is done to ensure that !efore avera#in#) the entire ' corresponds to depth samples are written tofifo.
#enerateHrdHenHstart>processcl) 0TH'!e#in
if 0TH' I thencounterHforHrd SI others I K
elsif clevent and cl I 1 thenif rdHenHstart I and wrHenHfifo I 1 then
counterHforHrd SI counterHforHrd 1K
end ifKend ifK
end processK-------------------------------------------------------------------rdHenHstart SI 1 when counterHforHrd I filterHdepth else
AccumHDemodHout SI others I Kelsif clevent and cl I 1 then
AccumHDemodHout SI AccumHDemodHoutHtmpKend ifK
end processK------------------------------------------------------------------- As mentioned in the a!ove dia#ram) at ever$ instance the summation of ever$ consecutive ' samples iscalculated in this wa$. At '1 th cloc ed#e the output of F& filter is) 0um of '1 samples X first sample.
The multiplier used here is FPGA resource. &t is used to control the #ain of the filtered output error si#nal
amplitude. Gain is controlled !$ fractional multiplication of si#nal. &t is a si#ned multiplier. ,ser can selectthe fractional value over ,AT with which si#nal to !e multiplied.&t also controls the fastness of the loop closure of the s$stem.
The fractional scalin# factor is confi#ured !$ the user. <ere shown the 7p value assi#ned with ,art data.
p SI uHdata8 @ uHdata*K
/
#a =68t;87r
F&HFilterHoutHre# a" propHout
clH+3 cl
7p !
/+
19
8
0THP aclr
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&nstHmulHpid > mulHpidport map
cl I clH+3)a I F&HFilterHoutHre#) -- /+ !it! I p) -- 19 !it Proportional #ain For unit #ain of rate) set for 98d" I propHout) -- 8 !it Proportional outputaclr I 0THP
1 cl &' 0TDH(%G&C +3<B Data samplin# cloccloc input
+ a &' 0TDH(%G&CH:ECT%/1D%W'T%
/+-!it si#ned Filtered data isconnected which needs to
!e scaled
/ ! &' 0TDH(%G&CH:ECT%1*D%W'T%
19-!it unsi#ned proportional#ain controlled !$ user used
to scale the filtered si#nal
8 " %,T 0TDH(%G&CH:ECT%86D%W'T%
8-!it si#ned product output
* aclr &' 0TDH(%G&C Active hi#h reset input is
connected
Ta!le 1> &nput and output si#nals of Gain multiplier
1.(.(.2 C7 7scr;t
The 19-!it unsi#ned value p selected !$ the user is one of the inputs to the #ain multiplier. As this is 19-!itwidth the ran#e of this scale factor is Y to +Q19-1Z.
For the current implementation) the avera#in# filter depth is fied to 19 &nte#er multiple of +samples.<ence accumulation of 19 samples results I 19 times [ error si#nal.Filter output is divided !$ 19 to reduce the #ain I 19 times [ error si#nal?19.
&n this multiplier) the fractional multiplication is performed to #et error si#nal of less amplitude which will !eused for net sta#e inte#ration.
propHout is the 8-!it si#ned output of the multiplier. &n the net sa#e propHout 89downto 1* is used forinte#ration. <ence the ouput of multiplier is further divided !$ +Q1*.
<ence)Gain multiplier effective output is I 19 times [ error si#nal?19?+Q1*
I 19 [ error si#nal ?+Q14.
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1.(.& D7a*ba c=;7satr
The closed loop operation suffers from a locup near rotation rates around Bero. The locup is alsoreferred to as dead-!and) dead-Bone) or a re#ion of insta!ilit$. &t is a ran#e of rates where the sensitivit$ of the #$ro reduces to Bero such that #$ro no lon#er senses rotation rate.
This dead-!and error can !e eliminated !$ the addition of a periodic compensation si#nal) at the input tothe step-siBe inte#rator.
1.(.&.1 C7 7scr;t
,ser can select the amplitude of the compensation over ,AT. This is shown in the followin# part of code.Compensation amplitude is /+-!it value./+-!it Fied offset value can !e selected over ,art) if re"uired can !e added to this compensationamplitude.
The duration of compensation is selected !ased on consideration of data upload rate to PC. At present for ever$ +ms duration) step-siBe data needs to !e upload to PC. <ence the period of dead-!and compensation should also !e in proportion to that upload rate. <ere the period of compensation is+ms.
<ence a periodic +ms period - clH*<B s"uare wave DHCompHout of selected amplitude,artHDHcompHamp is #enerated.
--------------------------------------------------------------------- Dead !and error compensation usin# Fied offset addition @-- su!traction with %n-%ff periods of clH*<B si#nal.-------------------------------------------------------------------
,artHDHcompHamp SI uHdata @ uHdata4 @ uHdata1 @ uHdata11K-- fiedHoffset SI uHdataHsevenK
fiedHoffset SI others I KDHCompHout SI fiedHoffset ,artHDHcompHamp when clH*<B I 1 else
The #enerated s"uare wave dead-!and compensator si#nal is added to the #ain multiplier output which
is fed as input to the net sta#e 0tep-siBe inte#rator.
dmodHerror SI propHoutHint DHCompHoutK
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1.(.9 St7;*sK7 t75ratr
This is an &nte#ral controller. This module inte#rates the #ain controlled error output for ever$ transit time.The inte#rated output will !e used for the phase error compensation si#nal #eneration. &n a closed loops$stem) when the error input is of hi#h?low amplitude) the compensation si#nal of proportional amplitudewill !e #enerated. <ence this inte#ration at ever$ transit time never overflows. The inte#rated output is alsoupload to PC over a selected period.
,ser selection control for Fied?actual step-siBe input
consideration for theinte#ration
8 dmodHerror &' 0TDH(%G&CH:ECT%/1 Compensated Gain
81
St7;*sK7 t75ratr
0TH'
dmodHerror
stepHsiBe
clHtransit
F&=HHACT,A(H00H0E(
Fied0tep0iBe
/+
/+
// +
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D%W'T% multiplier output
* Fied0tep0iBe &' 0TDH(%G&CH:ECT%/1D%W'T%
/+-!it Fied step-siBe dataselected !$ user over ,AT
9 stepHsiBe %,T 0TDH(%G&CH:ECT%/+ D%W'T%
Effective 0tep-siBe output)will !e used for ramp-
#eneration and avera#er.
Ta!le 11> &nput and output si#nals of 0tep-siBe inte#rator
1.(.9.2 C7 7scr;t
Gain controlled error output is /+-!it dmodHerror.ased on the user selection parameter F&=HHACT,A(H00H0E( Fied step-siBe and actual step-siBe ismultipleed) which will !e inte#rated at ever$ transit-time. The inte#rated output is stepHsiBe.
When F&=HHACT,A(H00H0E( is V) actual input error is inte#rated to form the step-siBe.When F&=HHACT,A(H00H0E( is V1) user selected fied-step-siBe /+-!it value is inte#rated to form the
step-siBe. This will !e used for some testin# in open loop condition.
---------------------------------------------------------------------------------------------------------stepHsiBeHtemp SI dmodHerrorK---------------------------------------------------------------------------------------------------------with F&=HHACT,A(H00H0E( select stepHsiBeHtemp1 SI
--------------------------------------------------------------------- 0tep-siBe inte#ration after ever$ transit-time of G$ro.-------------------------------------------------------------------process0TH') clHtransit!e#in
if 0TH' I thenstepHsiBeHint SI othersI K
elsif clHtransitevent and clHtransit I then
stepHsiBeHint SI stepHsiBeHtemp1Kend ifK
end processK---------------------------------------------------------------------------------------------------------
stepHsiBe SI stepHsiBeHintK---------------------------------------------------------------------------------------------------------
8+
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1.(.10 V2; ctr8 ca
The value :+pi corresponds to the pea-pea amplitude of the feed !ac compensation si#nal amp
si#nal. The purpose of this controller is to correct the error in this amplitude at ever$ ramp-reset instance.
-- F&3ovin# Avera#e filter to store the samples Rust !efore and after the ramp reset instance-------------------------------------------------------------------&nstH3ovin#HAv#HFilterH:+piHctrl> 3ovin#HAv#HFilterH:+piHctrlP%T 3AP
cl I clH+3)0TH' I 0TH')filterHdepth I :+piHCtrlHFifoHdepth)demodHmulHdata I demodHmulHoutHint)
F&HFilterHout I F&HFilterHoutK
process0TH') clH+3!e#in
if 0TH' I then F&HFilterHoutHre# SI othersI K
elsif clH+3event and clH+3 I then F&HFilterHoutHre# SI F&HFilterHoutK
end ifKend processK-------------------------------------------------------------------
--------------------------------------------------------------------- P%P%T&%'A( GA&' 3,(T&P(&E-------------------------------------------------------------------0THP SI '%T 0TH'K
&nstHmulH#ainHctrl > mulHpidport map
cl I clH+3)a I F&HFilterHoutHre#) -- /+ !it! I GainHval) -- 19 !it Proportional #ain" I 3ulHout) -- 8 !it Proportional outputaclr I 0THP
--------------------------------------------------------------------- 0tep-siBe inte#ration after ever$ transit-time+7<B of G$ro.-------------------------------------------------------------------
&nt#H:+piHErrorHtemp SI 3ulHout/9 downto *K
-- &nt#H:+piHErrorHtemp1 SI &nt#H:+piHErrorHtemp &nt#H:+piHErrorK&nt#H:+piHErrorHtemp1 SI &nt#H:+piHErrorHtempK
process0TH') clH+3
!e#inif 0TH' I then
ampHesetHctrlHd1 SI KampHesetHctrlHd+ SI KampHesetHctrlHd/ SI K
elsif clH+3event and clH+3 I thenampHesetHctrlHd1 SI ampHesetHctrlKampHesetHctrlHd+ SI ampHesetHctrlHd1KampHesetHctrlHd/ SI ampHesetHctrlHd+K
-- 0(19H1> 19-!it shift re#ister (,T operatin# on ne#ed#e of cloc0(19H1Hinst1 > 0(19H1
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#eneric map &'&T I =JJport map
] I P%GHC'THE'HDE(A21) -- 0( data output A I DE(A2H0E(HCT() -- 0electYZ input A1 I DE(A2H0E(HCT(1) -- 0electY1Z input A+ I DE(A2H0E(HCT(+) -- 0electY+Z input A/ I DE(A2H0E(HCT(/) -- 0electY/Z inputC(7 I clH+3) -- Cloc input
D I P%GHC'THE' -- 0( data inputK
0(19H1Hinst+ > 0(19H1#eneric map &'&T I =JJport map
] I P%GHC'THE'HDE(A2+) -- 0( data output A I DE(A2H0E(HCT() -- 0electYZ input A1 I DE(A2H0E(HCT(1) -- 0electY1Z input A+ I DE(A2H0E(HCT(+) -- 0electY+Z input A/ I DE(A2H0E(HCT(/) -- 0electY/Z inputC(7 I clH+3) -- Cloc inputD I P%GHC'THE'HDE(A21 -- 0( data input
K
processDE(A2H0E(HCT(8) P%GHC'THE'HDE(!e#in
ifDE(A2H0E(HCT(8 I then&nt#HE' SI P%GHC'THE'HDE(A21K
else&nt#HE' SI P%GHC'THE'HDE(A2+K
end ifKend processK
process0TH') clH+3
!e#inif 0TH' I then
&nt#H:+piHError SI othersI Kelsif clH+3event and clH+3 I then
if&nt#HE' I 1 then&nt#H:+piHError SI &nt#H:+piHErrorHtemp1K
end ifKend ifK
end processK
:+piHErrorHcompHval SI &nt#H:+piHErrorK
'%TE > 0till further stud$ of :+pi variation with rotation rate at the ramp-reset is need.
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1.(.11 Ra=; s5a8 577rat
This module is the feed!ac phase error compensation si#nal #enerator. The step-siBe data is inte#ratedwith reference to the upper and lower thresholds and results ramp si#nal whose fre"uenc$ is proportionalto the step-siBe.
Fi#ure +> loc dia#ram of amp-si#nal #eneration module
Ta!le 1/> &nput and %utput si#nals of amp-#eneration module
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Fi#ure +1> Al#orithm for amp si#nal #eneration
*
0,H%,T1 I3od0tep siBe-:H+piH/+
3od0tep siBe:H+piH/+
$es
no
0,H%,T1 I3od0tep siBe
0,H%,T1 I3od0tep siBe+-:H+piH/+
3od0tepsiBe+ :H+piH/+
$es
no
0,H%,T1 I3od0tep siBe+
0tepsiBe
Positive 'e#ative
0tepsiBe
Positive 'e#ative
ampHintHs IampHintHs 0,H%,T1- :H+piH/+
ampHintHs IampHintHs 0,H%,T1
:H,pThr-rampHintH s SI0,H%,T1
$es
no
ampHintHs IampHintHs - 0,H%,T1 :H+piH/+
ampHintHs IampHintHs - 0,H%,T1
rampHint Hs -:H(owThr SI0,H%,T1
$es
no
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Fi#ure ++> Pipelined implementation of ramp si#nal #eneration
1.(.11.2 C7 7scr;t
The followin# part of :<D( code #ives the details of the implementation of ramp-si#nal #eneration.amp-si#nal pea-pea amplitude is confi#ured !$ the user usin# PC application. This is also referred toas :+\ ampH:pp. ,pper and lower thresholds of the ramp-si#nal are derived from :+\.
As ampH:pp is /+-!it value) midH/+!it represents half of the ma#nitude of a /+-!it value. ,sin# thesetwo parameters) upper and lower threshold values are calculated as shown.
*1
FF1 FF+ FF/ FF8
0tep siBe
0tep siBe+
: +pi /+
;ero 0,H1
0,HA1
0tep siBe del1 /+ 0tep siBe del/ 30
0,H%,T1
//
/+
/+
+
/+
/+
/+
0tep siBe /+
/+
/+
+
0,H%,T1
0tep siBe del/ 30
:H,pHThr
:H(owHThr
: +pi /+
;ero
amp intHs
/+
/+
/+
//
/+
/+ /+
/+
/+
/+
/+
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midH/+!it SI J1111111111111111111111111111111JK:H,pThr SI midH/+!it @ ampH:pp/1 downto 1K -- ,pper threshold:H(oThr SI not :H,pThrK
0tep-siBe is rotation-rate dependent parameter. 0tep-siBe value is in Two5s complement format) itsma#nitude is used for ramp-si#nal inte#ration.
0ince the DAC used for ramp-si#nal output accepts data in %ffset !inar$ format) ramp-si#nal should !e inoffset !inar$ representation. The ma#nitude of step-siBe is etracted !ased on its si#n !it.&f step-siBe is positive) the ma#nitude of step-siBe is the step-siBe itself.&f step-siBe is ne#ative) the ma#nitude of step-siBe is its Twos complemented value.Two5s complemented value of actual step-siBe data is stepHsiBeH+sHcmp. amp si#nal is #enerated !$ theinte#ration of the step-siBe ma#nitude.
stepHsiBeH+sHcmp SI not stepHsiBe 1K
AHC3PT SI stepHsiBe/1 downto when stepHsiBe/+ I else stepHsiBeH+sHcmp/1 downto K
The ma#nitude of step-siBe AHC3PT is compared with the ramp-si#nal pea-pea amplitude /+-!it:+\. ased on the comparator result respective controls 0,HselHctrl1 are set as follows
&f step-siBe is positive and #reater than :+\) 0,HselHctrl1 value is V.&f step-siBe is positive and less than or e"uals :+\) 0,HselHctrl1 value is V1.&f step-siBe is ne#ative and #reater than :+\) 0,HselHctrl1 value is V1.&f step-siBe is ne#ative and less than or e"uals :+\) 0,HselHctrl1 value is V11.
The least si#nificant !it of 0,HselHctrl1 is #enerated !ased on comparator.The most si#nificant !it of 0,HselHctrl1 is #enerated usin# the si#n of step-siBe. This is done to reduceone multipleer usa#e.
process0TH') rampH#enHcl!e#in
if 0TH' I then0,HselHctrl1 SI others I KstepHsiBeHdel1 SI others I KstepHsiBeH+Hdel1 SI others I K
elsif rampH#enHclevent and rampH#enHcl I 1 thenif AHC3PT ampH:pp/1 downto then
0,HselHctrl1 SI Kelse
0,HselHctrl1 SI 1Kend ifK0,HselHctrl11 SI stepHsiBe/+K
stepHsiBeHdel1 SI stepHsiBeKstepHsiBeH+Hdel1 SI stepHsiBeH+sHcmpK
end ifKend processK
&f step-siBe is positive and #reater than :+\) 0,HselHctrl1 value is V then the difference !etween step-siBe ma#nitude and :+\ is calculated) which will !e used to #enerate ramp-si#nal.
&f step-siBe is positive and less than or e"uals :+\) 0,HselHctrl1 value is V1 then the same step-siBema#nitude will !e used to #enerate ramp-si#nal.
&f step-siBe is ne#ative and #reater than :+\) 0,HselHctrl1 value is V1 then the difference !etweenstep-siBe ma#nitude and :+\ is calculated) which will !e used to #enerate ramp-si#nal.
&f step-siBe is positive and less than :+\) 0,HselHctrl1 value is V11 then the same step-siBe ma#nitudewill !e used to #enerate ramp-si#nal.
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if AHC3PT+ SI 0,H%,T1 thenrampHintHs SI rampHintHs 0,H%,T1 - ampH:pp/1 downto KampHesetHctrl SI 1K
elserampHintHs SI rampHintHs 0,H%,T1KampHesetHctrl SI K
end ifKelse
if AHC3PT+ SI 0,H%,T1 thenrampHintHs SI rampHintHs - 0,H%,T1 ampH:pp/1 downto KampHesetHctrl SI 1K
elserampHintHs SI rampHintHs - 0,H%,T1KampHesetHctrl SI K
end ifKend ifK
end ifKend processK
1.(.12 Bas s5a8 577rat
0"uare wave ias si#nal of 17<B fre"uenc$ is #enerated. The !ias si#nal amplitude is proportional tothe ramp si#nal amplitude. The !ias si#nal time period is proportional to the transit time period.
1.(.12.1 C7 7scr;t
The amplitude of the !ias si#nal can !e confi#ured !$ user over ,art. As shown in the code) over a cloc 17<B) the s"uare wave is #enerated.
This module accumulates the final step-siBe data over a selective period !$ the user) then avera#es andthis output will !e fed to ,art controller for transmission.
1.(.13.1 C7 7scr;t
&t is shown here the accumulator for the step-siBe. %ver a period of +ms the data is accumulated and after ever$ +ms this accumulator content is reset.
--------------------------------------------------------------------- Avera#in# of the 0tep siBe over + ms-------------------------------------------------------------------ssHav#Hadder > ssHav#
The inte#ral multiple of +ms !ased control pulse from the rate-update module is used to reset thisaccumulator and to initiate the transmission of avera#ed step-siBe data to PC.
uartHtHsel is the control parameter selcetd !$ the user over uart) !ased on this control the processed dataat different sta#es o#f this control chain can !e upload to PC.
uartHtHsel SI uHdata+8+ downto K
0elective offset value su!traction from the step-siBe data !efore upload to PC. This is done to eliminate
offset in the data while testin# the linearit$ of the s$stem.
This is the multiplein# lo#ic !ased on the control uartHtHsel.,sin# this multipleer) ADC demodulated data) 0tep-siBe of +ms avera#ed data) :+pi amplitude data andother re"uired value can !e upload to PC.
--------------------------------------------------------------------- This is ,AT data selector 3,=.-------------------------------------------------------------------
with uartHtHsel+ downto select stepHsiBeHtoH,art SI
-- stepHsiBe/+ downto 1 when JJ) -- Default * us-- :pp/1 downto when JJ) -- Checin# :+pi value
:+piHErrorHcompHval when JJ) -- :+pi error -- DE3%DHEFHsi# when J1J) -- Checin# ef-waveform
ssHav#Hs8 downto 4 when J1J)-- + ms
-- stepHsiBeHtoH,artHint when J1J)-- + msssHav#Hs81 downto 1 when J1J)-- 8 msssHav#Hs8+ downto 11 when J11J) -- msssHav#Hs8/ downto 1+ when J1J) -- 19 msssHav#Hs88 downto 1/ when J11J) -- /+ ms
-- ssHav#Hs8* downto 18 when J11J) -- 98 mspropHoutHint when J11J) --ssHav#Hs89 downto 1* when othersK-- 1+ ms
This is the s$nchroniBation lo#ic to #enerate the reset pulse to the accumulator mentioned a!ove andinitiate tri##er pulse for ,art transmitter.
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When rate update module sends +ms control si#nal) usin# this si#nal a reset-control 00Hav#HclrHpulseand tri##er-control stepsiBeHupdateHpulse are #enerated.This is to ensure that the accumulator will !e reset once ever$ +ms) onl$ after its accumulated data is
if 0TH' I thenpulseH+HmsHre#1 SI KpulseH+HmsHre#+ SI KpulseH+HmsHre#/ SI KpulseH+HmsHre#8 SI K
elsif clH+3event and clH+3 I 1 thenpulseH+HmsHre#1 SI pulseH+HmsKpulseH+HmsHre#+ SI pulseH+HmsHre#1KpulseH+HmsHre#/ SI pulseH+HmsHre#+KpulseH+HmsHre#8 SI pulseH+HmsHre#/K
end ifKend processK
stepsiBeHupdateHpulse SI pulseH+HmsHre#1 A'D '%T pulseH+HmsHre#+K00Hav#HclrHpulse SI pulseH+HmsHre#/ A'D '%T pulseH+HmsHre#8K
processclH+3) 0TH'!e#in
if 0TH' I thenstepHsiBeHtoH,artHre# SI others I K
elsif clH+3event and clH+3 I 1 then&f stepsiBeHupdateHpulse I 1 then
stepHsiBeHtoH,artHre# SI stepHsiBeHtoH,artKend ifK
This module used to communicate with user interface over ,art.
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Fi#ure +/> (%C7 D&AGA3 of P&C%(A;E implementation %F ,AT
1.(.14.1 C7 7scr;t
,AT receives data seriall$ from PC on =D si#nal of FPGA.The received data is availa!le in receive!uffer re#ister of ,AT.The Pico !laBe processor checs an$ new data availa!le in ,AT.When ever newdata availa!le in ,AT then processor Rumps &0 routine.
ISR:
&n interrupt service routine processor reads status re#ister of ,AT !$ eecutin# read command andoutputtin# the command on C%33A'DH(ATC<H1 si#nal throu#h out port si#nal. and checs whether DATA EAD2 &T D &T is one or not .When ever D &T is one it reads data from receive !uffer re#ister of ,AT throu#h &'H(ATC<H1 si#nal in address decodin# lo#ic of processor implemented inside
FPGA.Processor stores data one of internal re#ister named as ,ATHDATAHEADHDATA.
*6
&'P%T
%,TP%T
P%T&D
1
%3
&
'(
ATC<
D A T
AH
% , T
D A T A H & '
&'T
ADD Y4>ZDATA Y16>Z
Z
P%T&D1
C3D(
ATC
<1
C0?
A1 A A+
D?WE?
?
=D
T=D
DC3
CT0T0D0
DT0&
DCD DCD
P%T&D1+T%+
,DATA
T%
,DATA/1
E0ET
+* 3<B1.8/+ 3<B
&'T
=D
C(7
& BIT DATA BUS
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Prc7ss s7 ;rc7ssr at7r ISR:Dependin# on portHid in address decodin# lo#ic of processor inside FPGA outputs data to internal si#nalinside data.
$ usin# a!ove lo#ic we enterin# /+ !$tes data from PC to ,AT and processor outputtin# /+ !$tes of data on to /+ internal si#nals named as ,HDATA to ,HDATA/1.
Processor and address decodin# lo#ic in FPGA and ,AT re#ister address-decodin# lo#ic worin# at +*
3<B cloc fre"uenc$.
Address Decodin# (o#ic>
process0TH') cl71!e#in if r0TH' I 1 then
commandHlatchH1 SI J11111111JK inHport SI JJK uHdata SI JJK uHdata1 SI JJK uHdata+ SI JJK uHdata/ SI JJK
uHdata8 SI JJK uHdata* SI JJK uHdata9 SI JJK uHdata6 SI JJK
uHdata SI JJK uHdata4 SI JJK uHdata1 SI JJK uHdata11 SI JJK uHdata1+ SI JJK uHdata1/ SI JJK uHdata18 SI JJK uHdata1* SI JJK
uHdata19 SI JJK
uHdata16 SI JJK uHdata1 SI JJK uHdata14 SI JJK uHdata+ SI JJK uHdata+1 SI JJK uHdata++ SI JJK uHdata+/ SI JJK
uHdata+8 SI JJK uHdata+* SI JJK uHdata+9 SI JJK uHdata+6 SI JJK uHdata+ SI JJK uHdata+4 SI JJK
uHdata/ SI JJK uHdata/1 SI JJK E0ET SIK
elsif cl1 I 1 and cl1event then if writeHstro!e I 1 then
case portHid is
when J1J I commandHlatchH1 SoutHportKwhen J11J I uHdata SI outHportK
when J111J I uHdata1 SI outHportK when J111J I uHdata+ SI outHportK when J1111J I uHdata/ SI outHportK when J1J I uHdata8 SI outHportK when J11J I uHdata* SI outHportK when J11J I uHdata9 SI outHportK
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when J111J I uHdata6 SI outHportK when J11J I uHdata SI outHportK when J111J I uHdata4 SI outHportK when J111J I uHdata1 SI outHportK when J1111J I uHdata11 SI outHportK when J11J I uHdata1+ SI outHportK when J111J I uHdata1/ SI outHportK when J111J I uHdata18 SI outHportK
when J1111J I uHdata1* SI outHportK when J111J I uHdata19 SI outHportK when J1111J I uHdata16SI outHportK when J1111J I uHdata1 SI outHportK when J11111J I uHdata14 SI outHportK when J1J I uHdata+ SI outHportK when J11J I uHdata+1 SI outHportK when J11J I uHdata++ SI outHportK when J111J I uHdata+/SI outHportK
when J11J I uHdata+8 SI outHportK when J111J I uHdata+* SI outHportK when J111J I uHdata+9 SI outHportK
when J1111J I uHdata+6 SI outHportK when J11J I uHdata+ SI outHportK when J111J I uHdata+4 SI outHportK when J111J I uHdata/ SI outHportK when J1111J I uHdata/1 SI outHportK
when others I nullKend caseK
elsif readHstro!e I 1 then case portHid is
when J1J I inHport SI inHlatchH1Kwhen others I nullK
end caseK else
commandHlatchH1 SI commandHlatchH1K end ifK end ifKend processK
&n a!ove lo#ic followin# are Prc7ssr s5a8s are%utHport> -!it vector. This is used for output data from processor to internal data si#nals and to outputcommand si#nals to ,AT.
inHport> !it vector. For input data and status of ,AT to processor form ,AT.
PortHid> -!it vector. This is used to select internal si#nal to which data should write from outHport of
ataG :The Parallel !$te data to !e stored in !uffer. The data will !e captured !$ the !uffer F&F% on the
risin# ed#e of the cl durin# which write is active.
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ataG6t:The Parallel !$te data which has !een received. This data is valid when dataHpresent is active.
r7s7t: An active <&G< input causes the !uffer to !e reset and hence all data currentl$ in !uffer to !e lost.
>rt7: An active <&G< indicates that the data currentl$ !ein# applied to the dataHin port is to !e written
to the internal !uffer on the net risin# ed#e of cl. A write operation will tae place on ever$ risin# ed#e of cl on which this si#nal is active. <ence this si#nal is pulsed <&G< for one cloc c$cle onl$) unless new
data is applied to dataHin ever$ cloc c$cle for a !urst write. The !uffer will i#nore data should it !ecomefull.r7a:
An active <&G< indicates that the data provided at the dataHout port has !een read or will !eread on the net risin# ed#e of the Ncl5 and that !uffer should mae the net data availa!le. The readinput ma$ !e active for consecutive cloc c$cles to perform a !urst of data. An$ attempt to read data whendataHpresent is inactive will have no effect) !ut this ille#al case should !e avoided when possi!le.688:
When the !uffer is full this output !ecomes <&G<. The host s$stem should not attempt to write untilit returns (%W. An$ attempt to write data will mean that new data is i#nored.a8G688:
When !uffer is filled half or more than half this output !ecomes <&G<. This is useful indication tothe host s$stem that the !uffer is approachin# a full condition and that it would !e wise to reduce the rate
at which data is !ein# written to the macro.ataG;r7s7t:
When the !uffer contains one or more !$tes of received data this si#nal will !ecome active <&G<and valid data will !e availa!le at the dataHout port.c8:
,sed !$ all s$nchronous elements of the macro) this si#nal should !e provided via one of the#lo!al low-sew cloc networs and all other si#nals should !e applied and read s$nchronousl$ to thiscloc.
1.(.1.3 FIFO b67r sK5
"at7r ta =78 B6c7t br5a7 FIFO:The operation of a F&F% can !e represented !$ a water tan. 'ew water is added at the top) and
the oldest water is drained from the !ottom. The siBe of the tan or !ucet must !e lar#e enou#h so that itdoes not overflow at times when more water is !ein# added at the top than is !ein# drained from the!ottom. %!viousl$ when a tan is empt$ nothin# can !e drained from the !ottom. As soon as an$ water isadded at the top then that water is availa!le to !e drained from the !ottom.&t has !ecome common practice for people to implement F&F%5s as a sin#le !loc of memor$ of anade"uate siBe to prevent overflow. <owever) Rust as with water tans) such a techni"ue can often results inlar#e or heav$ units that are difficult to mana#e and connect up.
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Fi#ure +*> Water Tan 3odel of ucet ri#ade F&F%
A Nucet ri#ade5 F&F% is constructed in a form that is similar to a series of smaller water tanswhich are connected in a cascaded arran#ement.
1.(.1.4 Cstr6ct5 4&9 FIFO 6s5 tr77 1'9 FIFOs:
&t is also called as 84 !ucet !ri#ade F&F%.
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Fi#ure +9> 84 F&F% usin# three 19 F&F% modules
1.(.1' UART tras=tt7r , r7c7<7r
UART =acr:The ,AT transmitter?receiver macro is provided !$ =ilin. This is havin# the followin#
characteristics>1. 1 start !it+. data !its/. 1 parit$ !it8. 1 stop !it.This macro also contains a 19 !$te F&F%. The F&F% siBe can also etenda!le !$ cascadin# more
!ucet !ri#ade F&F%s.
Ba6 rat7 t=5:
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These macros derive the transmission and receive timin# from a reference si#nal NenH19HH!aud5. As the name su##ests) this si#nal should !e applied to the macro at a rate which is 19 the desired !itrate.
0ince the si#nal is used as a cloc ena!le within the macro) it should !e provided s$nchronous tothe cloc and have a pulse duration of one cloc c$cle onl$ unless the maimum communication rate of cl?19 is re"uired.
Eample>The !aud rate re"uired is 14+<B and the availa!le s$stem cloc is *.9+*3<B. This can !e
achieved !$ *)9+*) ? 19 14+ I 198.6484. The nearest inte#er of 19* is well in ecess of there"uired tolerance e"uivalent !aud rate of 14169<B which is Rust .1+M low. An$ thin# with in 1Mtolerance is #oin# to wor.
------------------------------------------------------------------------------------- aud Timer #eneration for ,AT T= and =-- *.9+* 3<B ? 19 [ 14+ !aud I 198.64 ̂ I 19*-- audHcnt> ran#e to 198. to A8-----------------------------------------------------------------------------------
P%CE00 020HC(7
EG&' &F 020HC(7event and 020HC(7 I 1 T<E'&F !audHcnt I JA8J T<E'
!audHcnt SI others I KenH19HH!aud SI 1K
E(0E!audHcnt SI !audHcnt J1JKenH19HH!aud SI K
E'D &FKE'D &FK
E'D P%CE00K
1.(.1'.1 UART Tras=tt7r >t 1'9 b67r
Fi#ure +6> ,AT transmitter macro
This ,AT transmitter macro will receive parallel data data !its and 1 parit$ !it from host andthis data will !e sent seriall$ on NserialHout5 line of the macro.
1.6.19.1.1 Pin description of ,AT transmitter macro>
DataG:The parallel data -!it data and 1-parit$ !it to !e transmitted seriall$. The data will !e captured !$
the F&F% !uffer on arisin# ed#e of the NCl5 durin# which NwriteH!uffer5 is active."rt7Gb67r:
An active <&G< indicates that the data currentl$ !ein# applied to the NdataHin5 port is to !e written
to the internal !uffer on the net risin# ed#e of NCl5. A wirte operation will tae palce on ever$ risin# cloced#e on which this si#nal is active. <ence this si#nal should !e pulsed <&G< for one cloc c$cle onl$)unless new data applied to NdataHin5 ever$ cloc c$cle for a N!urst write5. The F&F%F will i#nore data shouldit !ecome full.R7s7tGb67r:
An active <&G< input causes the 19-!$te internal !uffer to !e reset and hence all data currentl$ inthe !uffer to !e lost. %peration of this si#nal durin# serial data transmission will potentiall$ result incorrupted data.EG1'GGba6:
Provides the timin# reference for the serial transmission. This should !e pulsed <&G< for one clocc$cle duration onl$ and at a rate which is 19 times or approimatel$ 19 times the rate at which the serialdata transmission is to tae place. Alternativel$) this si#nal ma$ !e set continuousl$ <&G< such that serialdata transmission taes place at the maimum rate of cl?19 !its per second.
S7ra8G6t:This is the serial data conformin# to 1 start !it) data !its (0 first) 1 parit$ !it @ 1 stop !it. &n
accordance with normal ,AT operation) this si#nal is <&G< in the idle no data to transmit condition.
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0erial data transmission commences as soon as there is data in the !uffer and continuous withoutinterruption start !it immediatel$ follows stop !it until the !uffer is empt$.B67rG688:
When 19-!$te F&F% !uffer is full) this output !ecomes active <&G<. The host s$stem should notattempt to write an$ new data until the serial transmission has !een a!le to create a space indicated !$N!ufferHfull5 returnin# low. An$ attempt to write data will mean that the new data is i#nored.B67rGa8G688:
When 19-!$te F&F% !uffer holds ei#ht or more !$tes of data waitin# to !e transmitted) this output
!ecomes active <&G<. This is a useful indication to the host that the F&F% !uffer is approachin# a fullcondition) and that it would !e wise to reduce the rate at which new data is !ein# written to the macro.C8:
,sed !$ all s$nchronous elements of the macro) this si#nal should !e provided via one of the#lo!al low-sew cloc networs and all other si#nals should !e applied and read s$nchronousl$ to thiscloc.
1.6.19.1.+ Timin# dia#rams to write data to ,AT transmit !uffer>
"7 b67r s t 688:The F&F% !uffer is used to accept data for transmission when written to macro. The !uffer is
automaticall$ read !$ the Ncuart4Ht5 circuit to pass the data to the serial line. Data is written to the !uffer on the risin# ed#e of cloc when NwriteH!uffer5 si#nal is active. Data can !e written in isolation) or in a !urstof several !$tes.
Fi#ure +4> Timin# characteristics of ,AT T when !uffer is not full
"7 b67r s 688:When the F&F% !uffer !ecomes full) the N!ufferHfull5 si#nal will !e asserted. This si#nal will remain
asserted until the parit$ !it of the currentl$ !ein# transmitted data is complete i.e. once the net stop !it is!ein# transmitted. 'o data can !e written to the !uffer when it is full.
Fi#ure /> Timin# characteristics of ,AT T when !uffer is full
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1.(.1'.2 UART R7c7<7r >t 1'9 b67r:
Fi#ure /1> ,AT receiver macro
This ,AT receiver macro will receive serial data data !its and 1 parit$ !it from serial line. Thereceived 4 !it data will !e availa!le on NdataHout5 port throu#h a 19-!$te F&F% !uffer.
1.6.19.+.1 Pin description of ,AT transmitter macro
S7ra8G:
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This is the serial data conformin# to 1 start !it) data !its (0 first) 1 parit$ !it @ 1 stop !it. &naccordance with normal ,AT operation this si#nal is <&G< in the idle condition. The fallin# ed#eassociated with a start !it is used to identif$ the !e#innin# of a serial transmission and the NenH19HH!aud5is used to determine the timin# of the transfer. %nce a complete serial transfer has !een received with avalid stop !it) it is automaticall$ written to the F%FF% !uffer unless the !uffer is full.DataG6t:
The parallel data 4-!it) which has !een received. This data is valid when N!ufferHdataHpresent5 isactive.
R7aGb67r: An active <&G< input indicates that the data provided at the NdataHout5 port has !een read or will
!e read on the net risin# ed#e of Ncl5 and that the F&F% should mae the net availa!le data availa!le.The NreadH!uffer5 input ma$ !e active for consecutive cloc c$cles to perform a N!urst5 of data. An$ attemptto read data when N!ufferHdataHpresent5 is inactive will have no effect) !ut this ille#al case should !eavoided when possi!le.R7s7tGb67r:
An active <&G< input causes the 19-!$te internal !uffer to !e reset and hence all data currentl$ inthe !uffer to !e lost.EG1'GGba6:
Provides the timin# reference for the serial transmission. This should !e pulsed <&G< for one clocc$cle duration onl$ and at a rate which is 19 times or approimatel$ 19 times the rate at which the serialdata transmission is to tae place. Alternativel$) this si#nal ma$ !e set continuousl$ <&G< such that serial
data transmission taes place at the maimum rate of cl?19 !its per second.B67rGataG;r7s7t:
When the internal !uffer contains one or more !$tes of received data this si#nal will !ecome <&G<and valid data will !e availa!le at the NdataHout5 port. B67rG688:
When 19-!$te F&F% !uffer is full) this output !ecomes active <&G<. The host s$stem should rapidl$respond to this condition !$ readin# some data from the !uffer so that further serial data is not lost.B67rGa8G688:
When 19-!$te F&F% !uffer holds ei#ht or more !$tes of data waitin# to !e read) this output!ecomes active <&G<. This is a useful indication to the host s$stem that the F&F% !uffer is approachin# afull condition) and that it would !e wise to read some data in the ver$ near future.C8:
,sed !$ all s$nchronous elements of the macro) this si#nal should !e provided via one of the
#lo!al low-sew cloc networs and all other si#nals should !e applied and read s$nchronousl$ to thiscloc.
1.6.19.+.+ Timin# dia#rams to read data from ,AT receive !uffer>
"t ata ;r7s7t:When data is present N!ufferHdataHpresent5 I 1) individual or !urst reads can !e made from the
F&F% !uffer.
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Fi#ure //> Timin# characteristics of ,AT with data present
"7 b67r s 688:The F&F% !uffer is automaticall$ written !$ the Ncuart4Hr5 circuit as each valid seriall$ transmitted
Ncharacter5 is captured !$ the receiver. Data is written to the !uffer as soon as the stop !it has !eenconfirmed as !ein# hi#h) !ut onl$ if the !uffer is not full.
Fi#ure /8> Timin# characteristics of ,AT when !uffer is full
&t can !e seen a!ove that when the F&F% !uffer !ecomes fullK it doesn5t actuall$ prevent the netNcharacter5 from !ein# received. Therefore the host s$stem has the time associated with eleven serial !itsto read at least one !$te from the F&F% !efore data is actuall$ missed.
1.(.1'.3 U;8a5 3*a7s rtat rat7 ata t PC 6s5 s587 UART
94
Pico !laBedHstro!e
WrHstro!e
%utHport&nHport
0lv1Hdata
0lv+Hdata
3asterHdataH
3asterHdataH1
3asterHdataH+
3asterHdataH/
0lvHdatapresentPortHid
0$ncHpulse
uartHtHdata
,AT
194F&F%
0lv1HD 0lv1Hdat
a
0lvHdatapresent
audHenHpulse
,AT
194F&F%
0lv+HD 0lv+Hdat
a
0lvHdatapresent1
audHenHpulse
&nterruptPortHid Decoder
Ce1
Ce+
Ce1
Ce+
,ATT
194F&F%
uartHTD,artHtHdata
audHenHpulse
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Fi#ure /*> 3aster slave communication scheme
C==6cat b7t>77 tr77 bars , PC>To upload /-aes data usin# sin#le ,AT) we are usin# master?slave communication techni"ue. <ere /-
aes data means) data from three WG-DPEC-1. !oards. Amon# these three) one !oard is used as master and the others as slaves. As shown in the a!ove fi#ure) master !oard is havin# one Pico!laBe processor to
communicate with slaves and PC throu#h ,AT.
D7s5 7ta8s =ast7r c==6cat>The master !oard will communicate with the other two slave !oards usin# two ,AT ports. Two 194 F&F%!ased ,AT modules are used to communicate with two slaves and one 194 F&F% !ased ,AT Tmodule to send /-aes rotation rate data to PC. A s$nchroniBin# pulse will !e issued to two slave !oards tos$nchroniBe the data communication !etween master and slave !oards.
Functionalit$ of Pico!laBe>1. + msec pulses #enerated !$ the master will !e used as interrupt to the Pico!laBe.+. Pico!laBe will send rotation rate data of master and slaves in the followin# format.
<eader AAh 3aster data 8!$tes 0lave-1 data8!$tes
0lave-+ data8!$tes
/. With ever$ interrupt Pico!laBe will send a header AAh to PC throu#h ,AT T and then masterand slave data 8-!$tes each.
8. While sendin# master data to PC) Pico!laBe will read /+-!it 8-$te rotation rate data from it5sinput port and sent to PC throu#h ,AT T.
*. After sendin# master data to PC) Pico!laBe will read slave-1 data from one of two ,AT modules and this data will !e sent to PC.
9. 0imilarl$) slave-+ data will also sent to PC.6. While readin# data from slaves) Pico!laBe will read the status of ,AT !uffers to chec the
presence of data. eadin# V0lvHdatapresent input port of Pico!laBe would do this.. ,AT !uffers of two slaves will have *-!$tes of data i.e. header and 8-!$tes of rotation rate
data. While readin# Pico!laBe will first read the header of those five !$tes. &f the header is AAthen Pico!laBe will send the remainin# 8-!$tes to PC.
4. &f the header is not AA) then) Pico!laBe will send 8-!$tes of Beros to PC for that particular slave.
After sendin# Beros) the ,AT !uffer will !e flushed out until it5s data present si#nal !ecomesBero.
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1. After sendin# /-aes data to PC) Pico!laBe 3aster will issue a s$nchroniBation pulse to it5s twoslaves to re"uest net rotation rate data to !e sent to PC.
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1.9.1 T=5 caract7rstcs Pcb8aK7 ;6ts a 6t;6ts >t r7a a >rt7 strb7s
Fi#ure /9> Accessin# Pico!laBe &nput and %utput
1.9.2 T=5 caract7rstcs UART tras=tt7r a r7c7<7r
1.9.2.1 T=5 caract7rstcs UART T >7 b67r s t 688
Fi#ure /6> Timin# characteristics of ,AT T when !uffer is not full
1.9.2.2 T=5 caract7rstcs UART T >7 b67r s 688
Fi#ure /> Timin# characteristics of ,AT T when !uffer is full
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1.9.2.3 T=5 caract7rstcs UART R >t ata ;r7s7t
Fi#ure /4> Timin# characteristics of ,AT with data present
1.9.2.4 T=5 caract7rstcs UART R >7 b67r s 688
Fi#ure 8> Timin# characteristics of ,AT when !uffer is full
• $te-wide Arithmetic (o#ic ,nit A(, with CA2 and ;E% indicator fla#s.
• 98-!$te internal scratchpad A3. &t is etenda!le up to +*9 !$tes.
• +*9 input and +*9 output ports for eas$ epansion and enhancement.
• Automatic /1-location CA((?ET,' stac.
• Predicta!le performance) alwa$s two cloc c$cles per instruction) up to 88 3&P0 in 0partan-/
FPGA.
• Fast interrupt responseK worst-case * cloc c$cles.
• %ptimiBed for =ilin 0partan-/) :irte-&&) and :irte-&& Pro FPGA architectures_Rust49 slices and.* to 1 !loc A3.
• Assem!ler) instruction-set simulator support.
1.12.1.2 Pcb8aK7 a ts ;r5ra= RO! t7rac7:
7CP03/ is a ver$ simple -!it &0C microcontroller primaril$ for the 0partan-/ devices. Althou#hit could !e used for processin# of data) it is most liel$ to !e emplo$ed in applications re"uirin# a comple)!ut non-time critical state machine. <ence it has the name of V7 constant Coded Pro#ramma!le 0tate3achine. This 7CP03/ re"uires Rust 49 slices of FPGA. To#ether with this small amount of lo#ic) a sin#le!loc A3 is used to form a %3 store for a pro#ram of up to 1+8 instructions. Even with such siBeconstraints) the performance is respecta!le at approimatel$ 8/ to 99 3&P0 dependin# on device t$pe andspeed #rade.The Pico!laBe microcontroller core is totall$ em!edded within the tar#et FPGA and re"uires no eternalresources. The Pico!laBe microcontroller is etremel$ flei!le. The !asic functionalit$ is easil$ etendedand enhanced !$ connectin# additional FPGA lo#ic to the microcontroller5s input and output ports.
The Pico!laBe microcontroller is delivered as s$nthesiBa!le :<D( source code) the core is future-proof and can !e mi#rated to future FPGA architectures) effectivel$ eliminatin# product o!solescencefears. ein# inte#rated within the FPGA) the Pico!laBe microcontroller reduces !oard space) desi#n cost)
and inventor$.
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1.12.1.3 %CPS!3 Pcb8aK7 arct7ct6r7:
1.12.1.4 Pcb8aK7 !crctr887r F6cta8 B8cs:
1.1+.1.8.1 General-Purpose e#isters>
• 19 !$te-wide.
• Desi#nated as re#isters s0 throu#h sF.
• The$ can !e renamed usin# an assem!ler directive for !etter pro#ram clarit$.
• All re#ister operations are completel$ interchan#ea!le.
• 'o re#isters are reserved for special tass or have priorit$ over an$ other re#ister
• There is no dedicated accumulatorK each result is computed in a specified re#ister.
1.1+.1.8.+ 1)+8-&nstruction Pro#ram 0tore>
• Eecutes up to 1)+8 instructions from memor$ within the FPGA.
• Each Pico instruction is 1 !its wide) compiled within the FPGA desi#n and automaticall$ loaded
durin# the FPGA confi#uration process.
1.1+.1.8./ Arithmetic (o#ic ,nit A(,>
• asic arithmetic operations such as addition and su!traction.
• itwise lo#ic operations such as A'D) %) and =%.• Arithmetic compare and !itwise test operations.
• Comprehensive shift and rotate operations.
• e#ister s= contains first operand and s2 or an -!it immediate constant contains the second
operand) the result is stored in the re#ister s=.
1.1+.1.8.8 Fla#s>
• A(, operations affect the ;E% and CA2 fla#s.
• ;E% fla# indicates when the result of the last operation resulted in Bero.
• The CA2 fla# indicates various conditions) dependin# on the last instruction eecuted.
• The &'TE,PTHE'A(E fla# ena!les the &'TE,PT input.
1.1+.1.8.* 98-$te 0cratchpad A3>
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• &t is directl$ or indirectl$ addressa!le from the re#ister file usin# the 0T%E and FETC<
instructions.
• The 0T%E instruction writes the contents of an$ of the 19 re#isters to an$ of the 98 A3
locations.
• The complementar$ FETC< instruction reads an$ of the 98 memor$ locations into an$ of the 19
re#isters.
1.1+.1.8.9 &nput?%utput>
• 0upports up to +*9 input ports.
• P%TH&D output provides the port address.
• Durin# an &'P,T operation) the Pico!laBe microcontroller reads data from the &'HP%T port to a
specified re#ister) s=.
• Durin# an %,TP,T operation) the Pico!laBe microcontroller writes the contents of a specified
re#ister) s=) to the %,THP%T port.
1.1+.1.8.6 Pro#ram Counter PC>
• PC alwa$s points to the net instruction to !e eecuted.
• PC alwa$s increments to the net instruction unless encountered !$ ,3P) CA(() ET,') and
ET,'& instructions or &nterrupt and reset events.
• 1-!it PC supports a maimum code space of 1)+8 instructions to /FF he.• &f the PC reaches the top of the memor$ at /FF he) it rolls over to location .
1.1+.1.8. Pro#ram Flow Control>
• An$ default eecution se"uence of the pro#ram can !e modified usin# conditional and non-
conditional pro#ram flow control instructions.
• CA(( and ET,' instructions provide su!routine facilities for commonl$ used sections of code.
• ,3P instructions specif$ an a!solute address an$where in the 1)+8-instruction pro#ram space.
• CA(( instruction specifies the a!solute start address of a su!routine) while the return address is
automaticall$ preserved on the CA((?ET,' stac.
• &f the interrupt input is ena!led) an &nterrupt Event also preserves the address of the preempted
instruction on the CA((?ET,' stac while the PC is loaded with the interrupt vector) /FF he.
• ET,'& instruction instead of the ET,' instruction is used to return from the interrupt service
routine &0.
1.1+.1.8.4 CA((?ET,' 0tac>
• CA((?ET,' hardware stac stores up to /1 instruction addresses) ena!lin# nested CA((
se"uences up to /1 levels deep.
• 0ince the stac is also used durin# an interrupt operation) at least one of these levels should !e
reserved when interrupts are ena!led.
• The stac is implemented as a separate c$clic !uffer.
• When the stac is full) it overwrites the oldest value. 'o pro#ram memor$ is re"uired for the stac.
1.1+.1.8.1&nterrupts>
• Pico!laBe 3C, has an optional &'TE,PT input) allowin# the 3C, to handle as$nchronous
eternal events. As$nchronous events refer to interrupts occurrin# at an$ time durin# theinstruction c$cle.
• Generall$) all inputs to Pico!laBe are s$nchroniBed usin# cloc input.
1.1+.1.8.11eset>
• The Pico!laBe microcontroller is automaticall$ reset immediatel$ after the FPGA confi#uration
process completes.
• After confi#uration) the E0ET input forces the processor into the initial state.
• The PC is reset to address ) the fla#s are cleared) interrupts are disa!led) and the
CA((?ET,' stac is reset.
•The data re#isters and scratchpad A3 are not affected !$ eset.
Pico!laBe processor has 1-!it instruction len#th. Each command will fit into these 1-!its. 0T%E@ FETC< instructions are used to access scratch pad memor$. %p-code or#aniBation of 0T%E @ FETC<
instructions are as follows>
From the a!ove fi#ure it is clear that 9 th @ 6 th !its are not used in 0T%E and FETC< commands)as it re"uires onl$ 9-!its to access 98-!$te scratch pad A3. &f these two !its also used to access thescratch pad A3 a +*9 !$te scratch pad A3 can !e accessi!le !$ the Pico!laBe.
To do this a special assem!ler is needed. This assem!ler is supplied !$ =ilin.
7CP03/ code is havin# onl$ 98 !$te scratch pad memor$. The followin# part of 7CP03/.vhdcode is to form a 98 !$te scratch pad memor$.---------------------------------------------------------------------------------------------------------------A '41 RA! s 6s7 >t Q577rat7 stat7=7t t 57t a '4& scratc ;a RA!.---------------------------------------------------------------------------------------------------------------storeHloop> for i in to 6 #enerate -- -- Attri!ute to define A3 contents durin# implementation
-- The information is repeated in the #eneric map for functional simulation ----------------------------------------------------------------------------- attri!ute &'&T > strin#Kattri!ute &'&T of memor$H!it > la!el is JJK-----------------------------------------------------------------------------
!e#in memor$H!it> A398=10 --s$nthesis translateHoff #eneric map&'&T I =JJ --s$nthesis translateHon port map D I si) WE I memor$Hena!le) WC(7 I cl)
A I secondHoperand) A1 I secondHoperand1) A+ I secondHoperand+) A/ I secondHoperand/) A8 I secondHoperand8) A* I secondHoperand*) % I memor$HdataiK ----------------------------------------------------------------------------- storeHflop> FD port map D I memor$Hdatai) ] I storeHdatai) C I clK ----------------------------------------------------------------------------- end #enerate storeHloopK---------------------------------------------------------------------------------------------------------------
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The followin# modifications are needed to the 7CP03/.vhd module to increase the scratch padsiBe. A +*9 A3 is re"uired for this.---------------------------------------------------------------------------------------------------------------A 2'1 RA! 6s5 strb6t7 85c r7s6rc7s. D7c8ar7 ts c=;7t.---------------------------------------------------------------------------------------------------------------component 7CP03HscratchH+*9=10#eneric&'&T> !itHvector+** downto >I othersIKport
D > in stdHlo#icKWE > in stdHlo#icKWC(7 > in stdHlo#icK A > in stdHlo#icK A1 > in stdHlo#icK A+ > in stdHlo#icK A/ > in stdHlo#icK A8 > in stdHlo#icK A* > in stdHlo#icK A9 > in stdHlo#icK A6 > in stdHlo#icK% > out stdHlo#icK
end componentK---------------------------------------------------------------------------------------------------------------** Ca57 88>5 =cats t t7 %CPS!3 c7. I arct7ct6r7 b.---------------------------------------------------------------------------------------------------------------storeHloop> for i in to 6 #enerate----------------------------------------------------------------------------- Attri!ute to define A3 contents durin# implementation-- The information is repeated in the #eneric map for functional simulation---------------------------------------------------------------------------attri!ute &'&T > strin#Kattri!ute &'&T of memor$H!it > la!el isJJK---------------------------------------------------------------------------
!e#in-------------------------------------------------------------------------------memor$H!it> 7CP03HscratchH+*9=10--s$nthesis translateHoff #eneric map&'&T I =JJ--s$nthesis translateHonport map D I si)
WE I memor$Hena!le)WC(7 I cl) A I secondHoperand) A1 I secondHoperand1) A+ I secondHoperand+) A/ I secondHoperand/)
A8 I secondHoperand8) A* I secondHoperand*) A9 I secondHoperand9) A6 I secondHoperand6)% I memor$Hdatai K---------------------------------------------------------------------------------
