February 1998 1/64This is advance information fromSGS-THOMSON.Detailsaresubject tochange withoutnotice.

R ST63738-BIT ROM/OTP/EPROM MCUs FOR DIGITALLY

CONTROLLED MULTISYNC/MULTISTANDARD MONITORS

n 4.5V to 6V Operating Supply Voltage Rangen Low Current Consumptionn 0 to +70C Operating Temperature Rangen 8 MHz clock Oscillatorn 16K bytes ROM/OTP/EPROM

(8K and 12K ROM versions also available)n 192 bytes RAMn 384 bytes general purpose EEPROMn 128 bytes dedicated EEPROM for DDC SPIn 22 fully programmable I/O pins, offering direct

LED drive capability, as well as interruptgeneration for keyboard inputs

n Digital WATCHDOG timern Three Timers, each comprising an 8-bit counter

and a 7- bit Prescalern SYNC Processor:

12-bits HSYNC Event Counter 12-bits VSYNC Period Counter HSYNC and VSYNC Polarity Detection HSYNC and VSYNC Outputs HFLYBACK and VFLYBACK Inputs CLAMP and BLANK Outputs

n 14-bit (PWM + BRM) D/A Convertern Nine 7-bit PWM D/A Converter Outputsn 8-bit A/D Converter with 8 multiplexed inputsn DDC SPI with interrupt and 4 operating modesn A further SPI with interrupt and 2 operating

modesn Remote Control Signal Input (Non Maskable

Interrupt)n VSYNC Interrupt Inputn Five Interrupt Vectorsn XOR Register (Instruction Set expansion)n MIRROR Register (Instruction Set expansion)

PSDIP42

CSDIP42

(Refer to end of Document for Ordering Information)

1

Table of Contents

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ST6373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61.3 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

1.3.1 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101.3.4 Data RAM/EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.3.5 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.4 MEMORY PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151.4.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151.4.2 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151.4.3 Eprom Erasure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 183.1 ON-CHIP CLOCK OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203.2.4 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203.2.5 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3 HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION . . . . . . . . . . . . . . . . . . . . 213.4 INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.4.1 Interrupt Vectors/Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.4.2 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243.4.3 Interrupt Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243.4.4 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253.4.5 ST6373 Interrupt Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283.5.3 Exit from WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.1.1 Details of I/O Ports A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304.1.2 Details of I/O Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314.1.3 I/O Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

4.2 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354.2.1 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364.2.2 Timer Status Control Registers (TSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.2.3 Timer Counter Registers (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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1

4.2.4 Timer Prescaler Registers (PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.3 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

4.3.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384.4 SYNC PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

4.4.1 Event Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404.4.2 Period Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404.4.3 Polarity Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404.4.4 Output Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404.4.5 Video Blanking Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.5 14-BIT PWM D/A CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444.5.1 Output Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444.5.2 HDA Tuning Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.6 7-BIT PWM D/A CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454.6.1 Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

4.7 SERIAL PERIPHERAL INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464.7.1 SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

4.8 MIRROR REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .514.9 XOR REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .525.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .525.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .525.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

6 ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586.2 RECOMMENDED OPERATING CONDITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .617.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

ST6373

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1 GENERAL DESCRIPTION

1.1 INTRODUCTIONST6373 Microcontrollers are members of the 8-bitHCMOS ST637x family, a series of devices spe-cially intended for Digitally Controlled Multi Fre-quency Monitor applications. All ST637x devicesare based on a building block approach: a com-mon core is surrounded by a combination of on-chip peripherals (macrocells) available from astandard library.ST6373 devices are available in functionally iden-tical ROM, OTP (ST63T73) and EPROM(ST63E73) versions, all with the same pinout.ROM devices are available with 8, 12 or 16K Pro-gram memory, whereas OTP and EPROM ver-sions are both available in 16K versions only. Fordetails relating to sales types, refer to Section 7.2.Since ROM, OTP and EPROM versions arefunctionally identical, the present Datasheetwill refer to the generic ST6373 device, exceptwhere specific versions differ in detail.The ST6373 devices feature: Nine PWM outputs, which can be used as Digital

to Analog converter outputs (with external RC fil-ters). These are suitable for tuning and otherfunctions.

A PWM output with Bit Rate Multiplier, to whichthe above comments apply.

An Event Counter especially designed to calcu-late the HSYNC (or HDRIV) Frequency, usingone of the on-chip timers.

A Period Counter especially designed to calcu-late the VSYNC Period.

A Polarity Detector for HSYNC (or HDRIV) andVSYNC.

HSYNC and VSYNC outputs with controlled po-larity.

Video Blanking and Clamping Outputs. Two I/O ports A & B usable for a keyboard wake-

up feature since an interrupt input ored on eachof their pins.

An Analog to Digital converter connected to portB which can be used to decode an analog key-board or for AFC.

A VSYNC input pin connected to an interruptvector and to the DDC SPI for DDC1 protocol.

An NMI input which can be used, for example, asa Remote Control input for a TV application.

A hardware DDC SPI able to manage DDC1(VSYNC as clock), DDC2B and DDC2AB (I2CBUS Multimaster and Slave). A 128-bytededicated EEPROM memory is available forDDC1 and DDC2B.

Hardware I2C SPI for internal monitor bus and tomanage, for example, an OSD.

A Mirror Register and a XOR Register are includ-ed to complement the basic ST6 instruction set.

Table 1. ST6373 Device Summary

Note: See Ordering Information in Table 23 at the end of the Datasheet.

DEVICECONFIGURATION

ProgramMemory(Bytes)

RAM(Bytes)

EEPROM(Bytes)

A/DInputs

14-bitD/ (PWM)

Output

7-bitD/A (PWM)

OutputEMULATING

DEVICES

ST63738K ROM

12K ROM16K ROM

192 512 8 1 9 ST63E73,ST63T73

ST63T73 16K OTP 192 512 8 1 9 -ST63E73 16K EPROM 192 512 8 1 9 -

ST6373

5/64

Figure 1. ST6373 Block Diagram

TEST

NMI INTERRUPT

16 KBytes

PC

STACK LEVEL 1STACK LEVEL 2STACK LEVEL 3STACK LEVEL 4STACK LEVEL 5STACK LEVEL 6

POWERSUPPLY OSCILLATOR RESET

DATA ROMUSER

SELECTABLE

DATA RAM192 Bytes

PORT A

PORT B

PORT C

8 BIT CORE

TEST/VPP (**)TIMER 1 PA0 -> PA7*

VDD VSS OSCin OSCout RESET

VSYNCPWRIN

USER PROGRAMMEMORY

TIMER 2

DIGITALWATCHDOG/TIMERInputs

DATA EEPROM384 Bytes

PB0 -> PB7*

PC0 -> PC7*

DDC SPI (1)

I C SPI

EEPROM128 Bytes (1)

TIMER 3

SCLD, SDADVSYNC, EXTCLK

SCLI, SDAI

HDA, DA0 -> DA8

AD0 -> AD7

D/A Outputs

A/D Inputs

SYNCPROCESSOR

HSYNCO, VSYNCOHSYNCI, VSYNCIHDRIVHFLY, VFLYCLMPO, BLKO

(*)Refer to Pin Description for Additional Information(**

) VPP

input for OTP/EPROM device programming

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1.2 PIN DESCRIPTIONVDD and VSS. Power is supplied to the MCU usingthese two pins. VDD is power and VSS is theground connection.OSCin, OSCout. These pins are internally con-nected to the on-chip oscillator circuit. A quartzcrystal or a ceramic resonator can be connectedbetween these two pins in order to allow the cor-rect operation of the MCU with various stabili-ty/cost trade-offs. The OSCin pin is the input pin,the OSCout pin is the output pin.RESET. The active lowRESET pin is used to startthe microcontroller to the beginning of its program.Additionally the quartz crystal oscillator will be dis-abled when the RESET pin is low to reduce powerconsumption during reset phase.TEST. The TEST pin must be held at VSS for nor-mal operation.PA0, PA1, PA2/HSYNCO, PA3/VSYNCO,PA4/CLMPO, PA5/BLKO, PA6/SCLI, PA7/SDAI Port A. Software configurable as push-pull out-

put, open-drain output, Schmitt trigger input withor without pull-up. Port A inputs can be alsoORed into the INT1 interrupt. Port A outputshave a LED drive capability (10 mA). Pins PA2and PA3 can be configured respectively asHSYNC and VSYNC outputs.Pins PA4 and PA5can be configured respectively as CLAMP andBLANK Outputs.Pins PA6 and PA7 can be con-figurated as the I2C SPI pins SCLI and SDAI.Thepush-pull output and the input pull-up options donot exist for these two pins. After reset the PA0to PA5 pins are configured as inputs with pull-up.

PB0/AD0, PB1/AD1, PB2/AD2, PB3/AD3,PB4/AD4, PB5/AD5/HFLY, PB6/AD6/VFLY,PB7/AD7 Port B. Each pin can be software configured as

push-pull output, open-drain output, Schmitt trig-ger input with or without pull-up.Port B inputs canbe also ored into the INT1 interrupt. Pins PB5and PB6 can be configured as HFLY and VFLYinputs. In addition, any pin of port B can be soft-ware selected as the Analog-to-Digital converterinput. Only one pin should be selected at a time,otherwise a conflict would result. After reset theport B pins are configured as inputs with pull-up.

PC0/SCLD, PC1/SDAD, PC2, PC3/EXTCLK,PC4/PWRIN, PC5, PC6/HSYNC, PC7/HDRIV Port C. Software configurable as open-drain out-

puts or Schmitt trigger inputs with or without pull-ups. When configured as outputs, pins PC0 toPC3 are configured as 5V open-drain. Pins PC4

to PC7 are configured as open-drain 12V; the in-put pull-up option does not exist for these fourpins. Pins PC0, PC1 and PC3 can be configuredas the DDC SPI pins SCLD, SDAD and EXTCLK.The input pull-up option does not exist for PC0and PC1. Pins PC6 and PC7 can be configuredas HSYNC and HDRIV inputs. After reset: PC3 isconfigured as input with pull-up. PC0, PC1 &PC4 to PC7 are configured in input without pull-up. PC2 is in output mode with the value 1 (highimpedance).

DA0-DA8. These pins are the nine PWM D/A out-puts of the on-chip D/A converters. These lineshave push-pull outputs with 5V drive. The outputrepetition rate is 31.25KHz (with 8MHz clock).VSYNC. This is the Vertical Synchronization pin.This pin is connected to an internal interrupt and isconfigured as input with pull-up and Schmitt trig-ger.HDA. This is the output pin of the on-chip 14-bitPWM D/A Converter. This line is a push-pull out-put with standard drive.NMI. This pin is the Non-Maskable interrupt inputand is configured as input with pull-up and Schmitttrigger.Figure 2. ST6373 Pin configuration

123456789101112131415161718192021

424140393837363534333231302928272625242322

O0/DA0O1/DA1O2/DA2O3/DA3

AD0/PB0AD1/PB1AD2/PB2AD3/PB3AD4/PB4

HFLY/AD5/PB5VFLY/AD6/PB6

AD7/PB7PA0PA1

HSYNCO/PA2VSYNCO/PA3

CLMPO/PA4BLKO/PA5SCLI/PA6SDAI/PA7

VSS

VDDPC0/SCLDPC1/SDADPC2PC3/EXTCLKPC4/PWRINPC5

PC7/HDRIVHDARESETOSCoutOSCinTEST/VPP (1)VSYNCNMIDA4/O4DAR/O5DA6/O6DA7/O7DA8/O8

PC6/HSYNC

(1) This pin is also the VPP input for OTP/EPROM devices

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Table 2. Pin SummaryPin Function Description

DA0 to DA8 Output, Push-PullHDA Output, Push-PullNMI Input, Pull-up, Schmitt Trigger InputVSYNC Input, Pull-up, Schmitt TriggerTEST Input, Pull-DownOSCin Input, Resistive Bias, Schmitt Trigger to Reset Logic OnlyOSCout Output, Push-PullRESET Input, Pull-up, Schmitt Trigger InputPA0-PA5 I/O, Push-Pull/Open Drain, Software Input Pull-up, Schmitt Trigger InputPA6-PA7 I/O, Open-Drain, No Input Pull-up, Schmitt Trigger InputPB0-PB7 I/O, Push-Pull/Open Drain, Software Input Pull-up, Schmitt Trigger Input, Analog InputPC0-PC1 I/O, Open-Drain, No Input Pull-up, Schmitt Trigger InputPC2-PC3 I/O, Open-Drain, 5V, Software Input Pull-up, Schmitt Trigger InputPC4-PC7 I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger InputVDD, VSS Power Supply Pins

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1.3 MEMORY SPACESThe MCU operates in three different memoryspaces: Stack Space, Program Space and DataSpace.1.3.1 Stack SpaceThe stack space consists of six 12 bit registers thatare used for stacking subroutine and interrupt re-turn addresses plus the current program counterregister.1.3.2 Program SpaceThe program space is physically implemented inthe ROM and includes all the instructions that areto be executed, as well as the data required for theimmediate addressing mode instructions, the re-served test area and user vectors. It is addressedthanks to the 12-bit Program Counter register (PCregister) and the ST6 Core can directly address upto 4K bytes of Program Space. Nevertheless, theProgram Space can be extended by the additionof 2-Kbyte memory banks as it is shown inFigure2, in which the 16K bytes memory is described.These banks are addressed by pointing to the000h-7FFh locations of the Program Space thanksto the Program Counter, and by writing the appro-priate code in the Program ROM Page Register(PRPR) located at address CAh in the DataSpace. Because interrupts and common subrour-outines should be available all the time only the

lower 2K byte of the 4K program space are bankswitched while the upper 2K byte can be seen asstatic space. Table 3 gives the different codes thatallows the selection of the corresponding banks.Note that, from the memory point of view, the Page1 and the Static Page represent the same physicalmemory: it is only a different way of addressing thesame location.Figure 3. 16K-Byte Program Space Addressing

Figure 4. Memory Addressing Diagram

Programcounterspace

0FFFh

0800h07FFh

0000h

0000h

StaticPagePage 1

Page 0Page1StaticPage

Page2 3 4 5 6 7

Page Page Page Page Page

1FFFh

PROGRAM SPACE

ROM

INTERRUPT &RESET VECTORS

ACCUMULATOR

DATA RAMBANK SELECT

DATA ROMWINDOW SELECT

RAM

X REGISTERY REGISTERV REGISTER

W REGISTER

DATA ROMWINDOW

RAM / EEPROMBANKING AREA

000h

03Fh040h

07Fh080h081h082h083h084h

0C0h

0FFh

0-63

DATA SPACE

0000h

0FF0h

0FFFh

PROGRAM COUNTER

STACK LEVEL 1

STACK LEVEL 2

STACK LEVEL 3

STACK LEVEL 4

STACK LEVEL 5

STACK LEVEL 6

ST6373

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MEMORY SPACES (Contd)Program ROM Page Register (PRPR)Address: CAh - Write onlyReset Value: XXh

D7-D3. These bits are not used but have to bewritten to 0.PRPR2-PRPR0. These are the program ROMbanking bits and the value loaded selects the cor-responding page to be addressed in the lower partof 4K program address space as specified in Table3.This register is undefined on reset.Note:Only the lower part of address space has beenbankswitched because interrupt vectors and com-mon subroutines should be available all the time.The reason of this structure is due to the fact that itis not possible to jump from a dynamic page to an-other, unless jumping back to the static page,changing contents of PRPR, and, then, jumping toa different dynamic page.

Care is required when handling the PRPR as it iswrite only. For this reason, it is not allowed tochange the PRPR contents while executing inter-rupts drivers, as the driver cannot save and than re-store its previous content. Anyway, this operationmay be necessary if the sum of common routinesand interrupt drivers will take more than 2K bytes;in this case could be necessary to divide the inter-rupt driver in a (minor) part in the static page (startand end), and in the second (major) part in one dy-namic page. If it is impossible to avoid the writing ofthis register in interrupts drivers, an image of thisregister must be saved in a RAM location, and eachtime the program writes the PRPR bit writes alsothe image register. The image register must bewritten first, so if an interrupt occurs between thetwo instructions the PRPR is not affected.

Table 3. Program MemoryPage Register Coding

Table 4. ST6373 Program Memory Map

Note *): all reserved areas must be set to FFh in the ROM code.

7 0

- - - - - PRPR2 PRPR1 PRPR0

PRPR2 PRPR1 PRPR0 PC11 Memory PageX X X 1 Static Page (Page 1)0 0 0 0 Page 00 0 1 0 Page 1 (Static Page)0 1 0 0 Page 20 1 1 0 Page 31 0 0 0 Page 41 0 1 0 Page 51 1 0 0 Page 61 1 1 0 Page 7

Program Memory Page Device Address Description*)

PAGE 0 0000h-007Fh0080h-07FFhReservedUser ROM

PAGE 1STATIC

0800h-0F9Fh0FA0h-0FEFh0FF0h-0FF7h0FF8h-0FFBh0FFCh-0FFDh0FFEh-0FFFh

User ROMReserved

Interrupt VectorsReserved

NMI VectorReset Vector

PAGE 2 0000h-000Fh0010h-07FFhReservedUser ROM

PAGE 3 0000h-000Fh0010h-07FFhReserved

User ROM (End of 8K)PAGE 4 0000h-000Fh0010h-07FFh

ReservedUser ROM

PAGE 5 0000h-000Fh0010h-07FFhReserved

User ROM (End of 12K)PAGE 6 0000h-000Fh0010h-07FFh

ReservedUser ROM

PAGE 7 0000h-000Fh0010h-07FFhReserved

User ROM (End of 16K)

ST6373

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MEMORY SPACES (Contd)1.3.3 Data SpaceThe ST6 Core instruction set operates on a specif-ic space, referred to as the Data Space, whichcontains all the data necessary for the program.

Figure 5. Data Space

The Data Space allows the addressing of RAM(192 bytes), EEPROM (384 bytes plus 128 bytesfor the DDC SPI), ST6 Core and peripheral regis-ters, as well as read-only data such as constantsand look-up tables.

*) These registers contain write only bits, in whichcase the bit operation instructions are not possi-ble.

DATA RAM/EEPROMBANK AREA

000h

03Fh

DATA ROMWINDOW AREA

040h

07FhX REGISTER 080hY REGISTER 081hV REGISTER 082hW REGISTER 083h

DATA RAM084h0BFh

PORT A DATA REGISTER 0C0hPORT B DATA REGISTER 0C1hPORT C DATA REGISTER 0C2h

RESERVED 0C3hPORT A DIRECTION REGISTER 0C4hPORT B DIRECTION REGISTER 0C5hPORT C DIRECTION REGISTER 0C6h

RESERVED 0C7hINTERRUPT OPTION REGISTER 0C8hDATA ROM WINDOW REGISTER 0C9h

PROGRAM ROM PAGE REGISTER 0CAh*)

I C SPI DATA REGISTER 0CBhDDC SPI DATA REGISTER 0CCh

PORT A OPTION REGISTER 0CDhPORT B OPTION REGISTER 0CEh

RESERVED 0CFhADC RESULT REGISTER 0D0h

ADC CONTROL REGISTER 0D1h*)

TIMER 1 PRESCALER REGISTER 0D2hTIMER 1 COUNTER REGISTER 0D3h

TIMER 1 STATUS/CONTROL REGISTER 0D4hTIMER 2 PRESCALER REGISTER 0D5h

TIMER 2 COUNTER REGISTER 0D7hWATCHDOG REGISTER 0D8h

MIRROR REGISTER 0D9hTIMER 3 PRESCALER REGISTER 0DAhTIMER 3 COUNTER REGISTER 0DBh

TIMER 3 STATUS/CONTROL REGISTER 0DChEVENT COUNTER DATA REGISTER 1 0DDhEVENT COUNTER DATA REGISTER 2 0DEh*)

SYNC PROCESSOR CONTROL REGISTER 0DFh*)

D/A 0/4 DATA CONTROL REGISTER 0E0h*)D/A 1/5 DATA CONTROL REGISTER 0E1h*)D/A 2/6 DATA CONTROL REGISTER 0E2h*)D/A 3/7 DATA CONTROL REGISTER 0E3h*)D/A 8 DATA CONTROL REGISTER 0E4h*)

I C SPI CONTROL REGISTER 1 0E5h*)I C SPI CONTROL REGISTER 2 0E6h*)

D/A BANK REGISTER 0E7hDATA RAM BANK REGISTER 0E8h

DDC EEPROM CONTROL REGISTER 0E9hEEPROM CONTROL REGISTER 0EAh

DDC SPI CONTROL REGISTER 1 0EBhDDC SPI CONTROL REGISTER 2 0ECh

NMI/PWRI N/VSYNC INTERRUPT REGISTER 0EDhHDA DATA REGISTER 1 0EEh*)

HDA DATA REGISTER 2 0EFh*)

PERIOD COUNTER DATA REGISTER 0F0hPERIOD COUNTER 1 AND BLANK CTRL REG. 0F1h*)

AUTO-COUNTER REGISTER 0F2hSCL LATCH AND DDC2B ADDRESS CTRL REG. 0F3h*)

XOR REGISTER 0F4h

RESERVED0F5h

0FEhACCUMULATOR 0FFh

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MEMORY SPACES (Contd)Data ROM Addressing. All the read-only data arephysically implemented in the ROM in which theProgram Space is also implemented. The ROMtherefore contains the program to be executed andalso the constants and the look-up tables neededfor the program. The locations of Data Space inwhich the different constants and look-up tablesare addressed by the ST6 Core can be consideredas being a 64-byte window through which it is pos-sible to access to the read-only data stored in theROM. This window is located from the 40h ad-dress to the 7Fh address in the Data space and al-lows the direct reading of the bytes from the 000haddress to the 03Fh address in the ROM. All thebytes of the ROM can be used to store either in-structions or read-only data. Indeed, the windowcan be moved by step of 64 bytes along the ROMin writing the appropriate code in the Write-onlyData ROM Window register (DRWR, locationC9h). The effective address of the byte to be readas a data in the ROM is obtained by the concate-nation of the 6 less significant bits of the address inthe Data Space (as less significant bits) and thecontent of the DRWR (as most significant bits). Sowhen addressing location 40h of data space, and0 is loaded in the DRWR, the physical addressedlocation in ROM is 00h.

Data ROM Window Register (DWR)Address: C9h - Write onlyReset Value: XXh

DWR7-DWR0. These are the Data Rom Windowbits that correspond to the upper bits of data ROMprogram space. This register is undefined after re-set.Note:Care is required when handling the DRWR as it iswrite only. For this reason, it is not allowed tochange the DRWR contents while executing inter-rupts drivers, as the driver cannot save and thanrestore its previous content. If it is impossible toavoid the writing of this register in interrupts driv-ers, an image of this register must be saved in aRAM location, and each time the program writesthe DRWR it writes also the image register. Theimage register must be written first, so if an inter-rupt occurs between the two instructions theDRWR register is not affected.

Figure 6. Data ROM Window Memory Addressing

7 0

DWR7 DWR6 DWR5 DWR4 DWR3 DWR2 DWR1 DWR0

DATA ROMWINDOW REGISTER

CONTENTSDATA SPACE ADDRESS

40h-7FhIN INSTRUCTION

PROGRAM SPACE ADDRESS

6 5 4 3 2 0

5 4 3 2 1 0

5 4 3 2 1 0

READ1

67891011

0 1

VR01573B

12

1

0DATA SPACE ADDRESS

59h

0000

0 1 0 0 1

11

Example:

(DWR)

DWR=28h

1 10 0 0 00 00 01ROM

ADDRESS:A19h 1 1

13

0 1

7

0

0

ST6373

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MEMORY SPACES (Contd)1.3.4 Data RAM/EEPROMIn the ST6373, 64 bytes of data RAM are directlyaddressable in the data space from 80h to BFh ad-dresses. The additional 128 bytes of RAM, and the384 + 128 bytes of EEPROM can be addressedusing the 64-byte banks located between address-es 00H and 3Fh. Bank selection is carried out byprogramming the Data RAM Bank Register (DR-BR) located at address E8h of the Data Space. Inthis way each bank of RAM or EEPROM can se-lect 64 bytes at a time. No more than one bankshould be set at a time.Data RAM Bank Register (DRBR)Address: E8h - Write onlyReset Value: XXh

DRBR6. This bit is reserved and must be held at0.DRBR5, DRBR4. Each of these bits, when set, willselect one page of the EEPROM dedicated to theDDC SPI.DRBR3, DRBR2. Each of these bits, when set, willselect oneRAM page.

DRBR7, DRBR1, DRBR0. These bits select theEEPROM pages.This register is undefined after reset.Table 5 summarizes how to set the Data RAMBank Register in order to select the various banksor pages.Note:Care is required when handling the DRBR as it iswrite only. For this reason, it is not allowed tochange the DRBR contents while executing inter-rupts drivers, as the driver cannot save and thanrestore its previous content. If it is impossible toavoid the writing of this register in interrupts driv-ers, an image of this register must be saved in aRAM location, and each time the program writesthe DRBR it writes also the image register. The im-age register must be written first, so if an interruptoccurs between the two instructions the DRBR isnot affected.1.3.5 EEPROM DescriptionThe data space of ST6373 devices, from 00h to3Fh, is paged as described in Table 5. The 512bytes of EEPROM are located in eight pages of 64bytes (see Table 3 below).

Table 5. Data RAM Bank Register Set-up

7 0

DRBR7

DRBR6

DRBR5

DRBR4

DRBR3

DRBR2

DRBR1

DRBR0

DRBR Value SelectionHex. Binary01h 0000 0001 EEPROM Page 002h 0000 0010 EEPROM Page 103h 0000 0011 EEPROM Page 204h 0000 0100 RAM Page 208h 0000 1000 RAM Page 310h 0001 0000 DDC EEPROM Page 020h 0010 0000 DDC EEPROM Page 181h 1000 0001 EEPROM Page 382h 1000 0010 EEPROM Page 483h 1000 0011 EEPROM Page 5

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MEMORY SPACES (Contd)By programming the Data RAM Bank Register,DRBR, the user can select the bank or page leav-ing unaffected the means of addressing the staticregisters. The way to address the dynamic pageis to set the DRBR as described in Table 5 (e.g. toselect EEPROM page 0, the DRBR has to be load-ed with content 01h, see Data RAM/EEPROM ad-dressing for additional information). Bits 0,1 and4,5,7 of the DRBR are dedicated to the standardEEPROM and DDC EEPROM respectively.The EEPROM pages do not require dedicated in-structions to be accessed in reading or writing.The standard EEPROM is controlled by the EEP-ROM Control Register, EECR, the DDC EEPROMis controlled by the DDC EPROM Control RegisterDEECR, in the same way. Any EEPROM locationcan be read just like any other data location, alsoin terms of access time.To write an EEPROM location takes an averagetime of 5ms and during this time the EEPROM isnot accessible by the Core. A busy flag can beread by the Core to know the EEPROM status be-fore trying any access. In writing the EEPROM canwork in two modes: Byte Mode (BMODE) and Par-allel Mode (PMODE). TheBMODE is the normalway to use the EEPROM and consists in access-ing one byte at a time. The PMODE consists in ac-cessing 8 bytes per time.

EEPROM Control Register (EECR)Address: EAh - Read/WriteReset Value: 00h

DDC EEPROM Control Register (DDCEECR)Address: E9h - Read/WriteReset Value: 00h

D7. Not used

SB. WRITE ONLY. If this bit is set the EEPROM isdisabled (any access will be meaningless) and thepower consumption of the EEPROM is reduced tothe leakage values.D5, D4. Reserved for testing purposes, they mustbe set to zero.PS. SET ONLY. Once in Parallel Mode, as soonas the user software sets the PS bit the parallelwriting of the 8 adjacent registers will start. PS isinternally reset at the end of the programming pro-cedure. Note that less than 8 bytes can be written;after parallel programming the remaining unde-fined bytes will have no particular content.PE. WRITE ONLY. This bit must be set by the userprogram in order to perform parallel programming(more bytes per time). If PE is set and the parallelstart bit (PS) is low, up to 8 adjacent bytes can bewritten at the maximum speed, the content beingstored in volatile registers. These 8 adjacent bytescan be considered as row, whose A7, A6, A5, A4,A3 are fixed while A2, A1 and A0 are the changingbytes. PE is automatically reset at the end of anyparallel programming procedure. PE can be resetby the user software before starting the program-ming procedure, leaving unchanged the EEPROMregisters.BS. READ ONLY. This bit will be automatically setby the CORE when the user program modifies anEEPROM register. The user program has to test itbefore any read or write EEPROM operation; anyattempt to access the EEPROM while busy bit isset will be aborted and the writing procedure inprogress completed.EN. WRITE ONLY. This bit MUST be set to one inorder to write any EEPROM register. If the userprogram will attempt to write the EEPROM whenEN= 0 the involved registers will be unaffectedand the busy bit will not be set.Notes:When the EEPROM is busy (BS = 1) the EECRcannot be accessed in write mode, it is only possi-ble to read BS status. This implies that, as long asthe EEPROM is busy, it is not possible to changethe status of the EEPROM control register. EECRbits 4 and 5 are reserved for test purposes, andmust never be set.

7 0

- SB Re-served

Re-served PS PE BS EN

7 0

- SB Re-served

Re-served PS PE BS EN

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MEMORY SPACES (Contd)Additional Notes on Parallel Mode. If the userwants to perform a parallel programming the firstaction should be the setting of the PE bit; from thismoment, the first time the EEPROM will be ad-dressed in writing, the ROW address will belatched and it will be possible to change it only atthe end of the programming procedure or by reset-setting PE without programming the EEPROM.After the ROW address latching the Core cansee just one EEPROM row (the selected one)and any attempt to write or read other rows willproduce errors. Do not read the EEPROM whilePE is set.As soon as PE bit is set, the 8 volatile ROW latch-es are cleared. From this moment the user canload data in the whole ROW or just in a subset. PSsetting will modify the EEPROM registers corre-sponding to the ROW latches accessed after PE.

For example, if the software sets PE and accessesEEPROM in writing at addresses 18h,1Ah,1Bhand then sets PS, these three registers will bemodified at the same time; the remaining bytes willhave no particular content. Note that PE is inter-nally reset at the end of the programming proce-dure. This implies that the user must set PE bit be-tween two parallel programming procedures. Any-way the user can set and then reset PE withoutperforming any EEPROM programming. PS is aset only bit and is internally reset at the end of theprogramming procedure. Note that if the user triesto set PS while PE is not set there will not be anyprogramming procedure and the PS bit will be un-affected. Consequently PS bit can not be set if ENis low. PS can be affected by the user set if, andonly if, EN and PE bits are also set to one.

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1.4 MEMORY PROGRAMMING1.4.1 Program MemoryThe ST6373 OTP and EPROM MCUs can be pro-grammed with a range of EPROM programmingtools available from SGS-THOMSON.EPROM/OTP programming mode is set by a+12.5V voltage applied to the TEST/VPP pin. Theprogramming flow is described in the User Manualof the EPROM Programming Tool.1.4.2 Option ByteThe Option Byte allows OTP and EPROM ver-sions to be configured to offer the same featuresavailable as mask options in ROM devices. TheOption Bytes content is automatically read, andthe selected options enabled on Reset.The Option Byte can only be accessed during pro-gramming mode. Access is either automatic (copyfrom a master device) or by selecting the OPTIONBYTE PROGRAMMING mode of the programmer.The option byte is located in a non-user map. Noaddress needs to be specified.Option Byte

bit 3 = I2C Clock Speed:

0 = 100KHz (default)1 = 400KHzAll other bits must be programmed as shown in theregister table above.The Option byte is written during programming ei-ther by using the PC menu (PC driven Mode) orautomatically (stand-alone mode).1.4.3 Eprom ErasureThanks to the transparent window present in theEPROM package, its memory contents may beerased by exposure to UV light.Erasure begins when the device is exposed to lightwith a wavelength shorter than 4000. It should benoted that sunlight, as well as some types of artifi-cial light, includes wavelengths in the 3000-4000range which, on prolonged exposure, can causeerasure of memory contents. It is thus recom-mended that EPROM devices be fitted with anopaque label over the window area in order to pre-vent unintentional erasure.The recommended erasure procedure for EPROMdevices consists of exposure to short wave UVlight having a wavelength of 2537. The minimumrecommended integrated dose (intensity x expo-sure time) for complete erasure is 15Wsec/cm2.This is equivalent to an erasure time of 15-20 min-utes using a UV source having an intensity of12mW/cm2 at a distance of 25mm (1 inch) fromthe device window.

7 0

0 0 0 0 X 0 1 0

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2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTIONThe CPU Core of ST6 devices is independent of theI/O or Memory configuration. As such, it may bethought of as an independent central processorcommunicating with on-chip I/O, Memory and Pe-ripherals via internal address, data, and controlbuses. In-core communication is arranged asshown in Figure 1; the controller being externallylinked to both the Reset and Oscillator circuits,while the core is linked to the dedicated on-chip pe-ripherals via the serial data bus and indirectly, forinterrupt purposes, through the control registers.

2.2 CPU REGISTERSThe ST6 Family CPU core features six registersand three pairs of flags available to the program-mer. These are described in the following para-graphs.Accumulator (A). The accumulator is an 8-bitgeneral purpose register used in all arithmetic cal-culations, logical operations, and data manipula-tions. The accumulator can be addressed in Dataspace as a RAM location at address FFh. Thus theST6 can manipulate the accumulator just like anyother register in Data space.

Indirect Registers (X, Y).These two indirect reg-isters are used as pointers to memory locations inData space. They are used in the register-indirectaddressing mode. These registers can be ad-dressed in the data space as RAM locations at ad-dresses 80h (X) and 81h (Y). They can also be ac-cessed with the direct, short direct, or bit direct ad-dressing modes. Accordingly, the ST6 instructionset can use the indirect registers as any other reg-ister of the data space.Short Direct Registers (V, W).These two regis-ters are used to save a byte in short direct ad-dressing mode. They can be addressed in Dataspace as RAM locations at addresses 82h (V) and83h (W). They can also be accessed using the di-rect and bit direct addressing modes. Thus, theST6 instruction set can use the short direct regis-ters as any other register of the data space.Program Counter (PC). The program counter is a12-bit register which contains the address of thenext ROM location to be processed by the core.This ROM location may be an opcode, an oper-and, or the address of an operand. The 12-bitlength allows the direct addressing of 4096 bytesin Program space.

Figure 7. ST6 Core Block Diagram

PROGRAM

RESET

OPCODEFLAG

VALUES2

CONTROLLER

FLAGSALU

A-DATA B-DATA

ADDRESS/READ LINE

DATA SPACE

INTERRUPTS

DATA

RAM/EEPROM

DATAROM/EPROM

RESULTS TO DATA SPACE (WRITE LINE)

ROM/EPROM

DEDICATIONS

ACCUMULATOR

CONTROLSIGNALS

OSCin OSCout

ADDRESSDECODER

256

12Program Counter

and6 LAYER STACK

0,01 TO 8MHz

VR01811

ST6373

17/64

CPU REGISTERS (Contd)However, if the program space contains more than4096 bytes, the additional memory in programspace can be addressed by using the ProgramBank Switch register.The PC value is incremented after reading the ad-dress of the current instruction. To execute relativejumps, the PC and the offset are shifted throughthe ALU, where they are added; the result is thenshifted back into the PC. The program counter canbe changed in the following ways:- JP (Jump) instruction. . . . . PC=Jump address- CALL instruction . . . . . . . . . PC= Call address- Relative Branch Instruction . PC= PC +/- offset- Interrupt . . . . . . . . . . . . . .PC=Interrupt vector- Reset . . . . . . . . . . . . . . . . . PC= Reset vector- RET & RETI instructions . . . . PC= Pop (stack)- Normal instruction . . . . . . . . . . . . .PC= PC + 1Flags (C, Z). The ST6 CPU includes three pairs offlags (Carry and Zero), each pair being associatedwith one of the three normal modes of operation:Normal mode, Interrupt mode and Non MaskableInterrupt mode. Each pair consists of a CARRYflag and a ZERO flag. One pair (CN, ZN) is usedduring Normal operation, another pair is used dur-ing Interrupt mode (CI, ZI), and a third pair is usedin the Non Maskable Interrupt mode (CNMI, ZN-MI).The ST6 CPU uses the pair of flags associatedwith the current mode: as soon as an interrupt (ora Non Maskable Interrupt) is generated, the ST6CPU uses the Interrupt flags (resp. the NMI flags)instead of the Normal flags. When the RETI in-struction is executed, the previously used set offlags is restored. It should be noted that each flagset can only be addressed in its own context (NonMaskable Interrupt, Normal Interrupt or Main rou-tine). The flags are not cleared during contextswitching and thus retain their status.The Carry flag is set when a carry or a borrow oc-curs during arithmetic operations; otherwise it iscleared. The Carry flag is also set to the value ofthe bit tested in a bit test instruction; it also partici-pates in the rotate left instruction.The Zero flag is set if the result of the last arithme-tic or logical operation was equal to zero; other-wise it is cleared.Switching between the three sets of flags is per-formed automatically when an NMI, an interrupt ora RETI instructions occurs. As the NMI mode is

automatically selected after the reset of the MCU,the ST6 core uses at first the NMI flags.Stack. The ST6 CPU includes a true LIFO hard-ware stack which eliminates the need for a stackpointer. The stack consists of six separate 12-bitRAM locations that do not belong to the dataspace RAM area. When a subroutine call (or inter-rupt request) occurs, the contents of each level areshifted into the next higher level, while the contentof the PC is shifted into the first level (the originalcontents of the sixth stack level are lost). When asubroutine or interrupt return occurs (RET or RETIinstructions), the first level register is shifted backinto the PC and the value of each level is poppedback into the previous level. Since the accumula-tor, in common with all other data space registers,is not stored in this stack, management of theseregisters should be performed within the subrou-tine. The stack will remain in its deepest positionif more than 6 nested calls or interrupts are execut-ed, and consequently the last return address willbe lost. It will also remain in its highest position ifthe stack is empty and a RET or RETI is executed.In this case the next instruction will be executed.Figure 8. ST6 CPU Programming Model

SHORTDIRECT

ADDRESSINGMODEV REGISTER

W REGISTER

PROGRAM COUNTER

SIX LEVELSSTACK REGISTER

C ZNORMAL FLAGS

INTERRUPT FLAGS

NMI FLAGS

INDEXREGISTER

VA000423

b7

b7

b7

b7b7

b0

b0

b0

b0

b0

b0b11

ACCUMULATOR

Y REG. POINTER

X REG. POINTER

C Z

C Z

ST6373

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3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

3.1 ON-CHIP CLOCK OSCILLATORThe internal oscillator circuit is designed to requirea minimum of external components. A crystalquartz, a ceramic resonator, or an external signal(provided to the OSCin pin) may be used to gener-ate a system clock with various stability/cost trade-offs. The typical clock frequency is 8MHz. Pleasenote that different frequencies will affect the oper-ation of those peripherals (D/As, SPI) whose refer-ence frequencies are derived from the systemclock.The different clock generator connection schemesare shown in Figure 1 and 2. One machine cycletakes 13 oscillator pulses; 12 clock pulses areneeded to increment the PC while and additional13th pulse is needed to stabilize the internal latch-es during memory addressing. This means thatwith a clock frequency of 8MHz the machine cycleis 1.625Sec.The crystal oscillator start-up time is a function ofmany variables: crystal parameters (especiallyRS), oscillator load capacitance (CL), IC parame-ters, ambient temperature, and supply voltage.Itmust be observed that the crystal or ceramic leadsand circuit connections must be as short as possi-ble. Typical values for CL1 and CL2 are in therange of 15pF to 22pF but these should be chosenbased on the crystal manufacturers specification.Typical input capacitance for OSCin and OSCoutpins is 5pF.The oscillator output frequency is internally dividedby 13 to produce the machine cycle and by 12 toproduce the Timers and the Watchdog clock. Abyte cycle is the smallest unit needed to executeany operation (i.e., increment the program coun-ter). An instruction may need two, four, or five bytecycles to be executed (SeeTable 1).Table 6. Instruction Timing with 8MHz Clock

Figure 9. Clock Generator Option 1

Figure 10. Clock Generator Option 2

Figure 11. OSCin, OSCout Diagram

Instruction Type Cycles ExecutionTimeBranch if set/reset 5 Cycles 8.125sBranch & Subroutine Branch 4 Cycles 6.50sBit Manipulation 4 Cycles 6.50sLoad Instruction 4 Cycles 6.50sArithmetic & Logic 4 Cycles 6.50sConditional Branch 2 Cycles 3.25sProgram Control 2 Cycles 3.25s

OSCin OSCout

CL1 CL2

ST6xxx

CRYSTAL/RESONATOR CLOCK

VA0016B

OSCin OSCout

ST6xxx

EXTERNAL CLOCK

NC

VA0015C

VA00462

OSCoutIn

OSCin, OSCout (QUARTZ PINS)

OSCin

1M VDD

DDV

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3.2 RESETSThe MCU can be reset in three ways: by the external Reset input being pulled low; by Power-on Reset; by the digital Watchdog peripheral timing out.3.2.1 RESET InputThe RESET pin may be connected to a device ofthe application board in order to reset the MCU ifrequired. The RESET pin may be pulled low inRUN, WAIT or STOP mode. This input can beused to reset the MCU internal state and ensure acorrect start-up procedure. The pin is active lowand features a Schmitt trigger input. The internalReset signal is generated by adding a delay to theexternal signal. Therefore even short pulses onthe RESET pin are acceptable, provided VDD hascompleted its rising phase and that the oscillator isrunning correctly (normal RUN or WAIT modes).The MCU is kept in the Reset state as long as theRESET pin is held low.If RESET activation occurs in RUN or WAITmodes, processing of the user program is stopped(RUN mode only), the Inputs and Outputs are con-figured as inputs with pull-up resistors if available.When the level on the RESET pin then goes high,the initialization sequence is executed followingexpiry of the internal delay period.If RESET pin activation occurs in the STOP mode,the oscillator starts up and all Inputs and Outputsare configured as inputs with pull-up resistors ifavailable. When the level of theRESET pin thengoes high, the initialization sequence is executedfollowing expiry of the internal delay period.3.2.2 Power-on ResetThe function of the POR circuit consists in wakingup the MCU at an appropriate stage during thepower-on sequence. At the beginning of this se-quence, the MCU is configured in the Reset state:all I/O ports are configured as inputs with pull-upresistors and no instruction is executed. When thepower supply voltage rises to a sufficient level, theoscillator starts to operate, whereupon an internaldelay is initiated, in order to allow the oscillator tofully stabilize before executing the first instruction.The initialization sequence is executed immediate-ly following the internal delay.The internal delay is generated by an on-chipcounter. The internal reset line is released 2048 in-ternal clock cycles after release of the external re-set.The internal POR device is a static mechanismwhich forces the reset state when VDD is below athreshold voltage in the range 3.4 to 4.2 Volts (seeFigure 1). The circuit guarantees that the MCU will

exit or enter the reset state correctly, without spu-rious effects, ensuring, for example, that EEPROMcontents are not corrupted.Note: This feature is not available on OTP/EPROMDevices.Figure 12. Power ON/OFF Reset operation

Figure 13. Reset and Interrupt ProcessingVR02037

VDD4.2

3.4

t

V

t

POWERON/OFF

Threshold

DD

RESET

INT LATCH CLEAREDNMI MASK SET

RESET

( IF PRESENT )

SELECTNMI MODE FLAGS

IS RESET STILLPRESENT?

YES

PUT FFEHON ADDR ESSBUS

FROM RESET LOCATIONSFFE/FFF

NO

FETCH INSTRUC TION

LOAD PC

VA000427

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RESETS (Contd)3.2.3 Watchdog ResetThe MCU provides a Watchdog timer function inorder to ensure graceful recovery from softwareupsets. If the Watchdog register is not refreshedbefore an end-of-count condition is reached, theinternal reset will be activated. This, amongst oth-er things, resets the watchdog counter.The MCU restarts just as though the Reset hadbeen generated by the RESET pin, including thebuilt-in stabilisation delay period.3.2.4 Application NoteNo external resistor is required between VDD andthe Reset pin, thanks to the built-in pull-up device.3.2.5 MCU Initialization SequenceWhen a reset occurs the stack is reset, the PC isloaded with the address of the Reset Vector (locat-ed in program ROM starting at address 0FFEh). Ajump to the beginning of the user program must becoded at this address. Following a Reset, the In-terrupt flag is automatically set, so that the CPU isin Non Maskable Interrupt mode; this prevents theinitialisation routine from being interrupted. The in-itialisation routine should therefore be terminatedby a RETI instruction, in order to revert to normal

mode and enable interrupts. If no pending interruptis present at the end of the initialisation routine, theMCU will continue by processing the instructionimmediately following the RETI instruction. If, how-ever, a pending interrupt is present, it will be serv-iced.Figure 14. Reset and Interrupt Processing

Figure 15. Reset Circuit

RESET

RESETVECTOR

JP JP:2 BYTES/4 CYCLES

RETIRETI: 1 BYTE/2 CYCLES

INITIALIZATIONROUTINE

VA00181

VA0200E

TO ST6 RESET

ST6INTERNALRESET

OSCILLATORSIGNAL

WATCHDOG RESET

VDD

300k

RESET(ACTIVE LOW)

COUNTER1k

POWER ON/OFF RESET

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3.3 HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTIONThe hardware activated digital watchdog functionconsists of a down counter that is automatically in-itialized after reset so that this function does notneed to be activated by the user program. As thewatchdog function is always activated this downcounter can not be used as a timer. The watchdogis using one data space register (HWDR locationD8h). The watchdog register is set to FEh on resetand immediately starts to count down, requiring nosoftware start. Similarly the hardware activatedwatchdog can not be stopped or delayed by soft-ware.

The watchdog time can be programmed using the6 MSBs in the watchdog register, this gives the

possibility to generate a reset in a time between3072 to 196608 oscillator cycles in 64 possiblesteps. (With a clock frequency of 8MHz this meansfrom 384ms to 24.576ms). The reset is preventedif the register is reloaded with the desired valuebefore bits 2-7 decrement from all zeros to allones.The presence of the hardware watchdog deacti-vates the STOP instruction and a WAIT instructionis automatically executed instead of a STOP. Bit 1of the watchdog register (set to one at reset) canbe used to generate a software reset if cleared tozero). Figure 1 shows the watchdog block diagramwhile Figure 2 shows its working principle.

Figure 16. Hardware Activated Watchdog Block Diagram

RSFF

8

DATA BUSVA00010

-2-12

OSCILLATOR

RESET

WRITERESET

DB0

RS

Q

DB1.7 SETLOAD

7 8-2SET

CLOCK

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HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION (Contd)Hardware Activated Watchdog Register(HWDR)Address: D8h - Read/WriteReset Value: 0FEh

T1-T6. These are the watchdog counter bits. Itshould be noted that D7 (T1) is the LSB of thecounter and D2 (T6) is the MSB of the counter,these bits are in the opposite order to normal.SR. This bit is set to one during the reset phaseand will generate a software reset if cleared to ze-ro.C. This is the watchdog activation bit that is hard-ware set. The watchdog function is always activat-ed independently of changes of value of this bit.The register reset value is FEh (Bit 1-7 set to one,Bit 0 cleared).

Figure 17. Hardware Activated WatchdogWorking Principle

7 0

T1 T2 T3 T4 T5 T6 SR C

BIT0

VA00190

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

8-BITDOWN COUNTER OSC-12

WA

TCH

DO

GC

ON

TRO

LR

EGIS

TER

RESET

D0

D1

D2

D3

D4

D5

D6

D7

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3.4 INTERRUPTThe MCU Core can manage 4 different maskableinterrupt sources, plus one non-maskable interruptsource (top priority level interrupt). Each source isassociated with a particular interrupt vector thatcontains a Jump instruction to the related interruptservice routine. Each vector is located in the Pro-gram Space at a particular address (see Table 7).When a source provides an interrupt request, andthe request processing is also enabled by theMCU Core, then the PC register is loaded with theaddress of the interrupt vector (i.e. of the Jump in-struction). Finally, the PC executes the Jump in-struction and the interrupt routine is processed.The relationship between vector and source andthe associated priority is hardware fixed forST6373 devices. For some interrupt sources it isalso possible to select by software the kind ofevent that will generate the interrupt.All interrupts can be disabled by writing to the GENbit (global interrupt enable) of the interrupt optionregister (address C8h). Following a reset, theST6373 is in non maskable interrupt mode, so nointerrupts will be accepted and NMI flags will beused, until a RETI instruction is executed. If an in-terrupt is executed, one special cycle is made bythe core, during that the PC is set to the related in-terrupt vector address. A jump instruction at thisaddress has to redirect program execution to thebeginning of the related interrupt routine. The in-terrupt detecting cycle, also resets the related in-terrupt flag (not available to the user), so that an-other interrupt can be stored for this current vector,while its driver is under execution.If additional interrupts arrive from the samesource, they will be lost. NMI can interrupt other in-terrupt routines at any time, while other interruptscannot interrupt each other. If more than one inter-rupt is waiting for service, they are executed ac-cording to their priority. The lower the number, thehigher the priority. Priority is, therefore, fixed. In-terrupts are checked during the last cycle of an in-

struction (RETI included). Level sensitive inter-rupts have to be valid during this period.Table 7 details the different interrupt vec-tors/sources relationships.3.4.1 Interrupt Vectors/SourcesThe MCU Core includes 5 different interrupt vec-tors in order to branch to 5 different interrupt rou-tines. The interrupt vectors are located in the fixed(or static) page of the Program Space.Table 7. Interrupt Vectors/Sources

Relationships

The interrupt vector associated with the non-maskable interrupt source is named interrupt vec-tor #0. It is located at the (FFCh, FFDh) addressesin the Program Space. This vector is associatedwith the NMI pin.The interrupt vectors located at addresses(FF6h,FF7h), (FF4h,FF5h), (FF2h,FF3h),(FF0h,FF1h) are named interrupt vectors #1, #2,#3 and #4 respectively. These vectors are associ-ated with TIMER 3, Port A and Port B interrupts(#1), Timer 2, VSYNC and I2C SPI (#2), TIMER 1and the DDC SPI (#3) and the ADC and PC4(PWRIN) (#4).

Interrupt Source AssociatedVectorVector

Address

NMI pin InterruptVector # 0 (NMI) 0FFCh-0FFDhTimer 3

I/O Port A, I/O Port BInterrupt

Vector # 1 0FF6h-0FF7h

Timer 2VSYNC, I2C SPI

InterruptVector #2 0FF4h-0FF5h

Timer 1DDC SPI

InterruptVector #3 0FF2h-0FF3h

ADCPWRIN

InterruptVector #4 0FF0h-0FF1h

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INTERRUPTS (Contd)3.4.2 Interrupt PriorityThe non-maskable interrupt request has the high-est priority and can interrupt any other interruptroutines at any time, nevertheless the other inter-rupts cannot interrupt each other. If more than oneinterrupt request is pending, they are processedby the MCU Core according to their priority level:vector #1 has the higher priority while vector #4the lower. The priority of each interrupt source ishardware fixed.3.4.3 Interrupt Option RegisterThe Interrupt Option Register (IOR register, loca-tion C8h) is used to enable/disable the individualinterrupt sources and to select the operating modeof the external interrupt inputs. This register is ad-dressed in the Data Space as a RAM location ataddress C8h, nevertheless it is write-only registerthat can not be accessed with single-bit opera-tions. The operating modes of the external inter-rupt inputs associated to interrupt vectors #1 and#2 are selected through bits 4 and 5 of the IORregister.Interrupt Option Register (IOR)Address: (C8h) - Write onlyReset Value: XX00XXXXb

D7. Not used.EL1. This is the Edge/Level selection bit of inter-rupt #1. When set to one, the interrupt is generat-ed on low level of the related signal; when clearedto zero, the interrupt is generated on falling edge.The bit is cleared to zero after reset.ES2. This is the edge selection bit on interrupt #2.This bit is used in ST6373 devices for VSYNC de-tection, the interrupt for Timer 2 and the I2C SPI. Itis cleared to zero on reset (falling edge), and mustbe maintained at 0 if the Timer 2 and I2C interruptsare to be used. The VSYNC interrupt may be con-figured to act on the falling edge (ES2=0) or risingedge (ES2=1) according to the system design.GEN. This is the global enable bit. When set toone all interrupts are globally enabled; when thisbit is cleared to zero all interrupts are disabled (ex-cluding NMI) independently to the individual inter-rupt enable bit of each peripheral.D3 - D0. These bits are not used.

NMI/PWR/VSync Interrupt Register (NPVIR)

b7: VSYNCST: (Read & Write, 0 written on Reset)b6: VSYNCEN: (Read & Write, 0 written on Reset)b5:PWRFLAG:(Read &Write,Undefined onReset)b4: PWINTEN: (Write Only, 0 written on Reset)b3: PWREDGE: (Write Only, 0 written on Reset)b2: NMIFLAG:(Read & Write, Undefined on Reset)b1: NMINTEN: (Write Only, 0 written on Reset)b0: NMIEDGE: (Write Only, 0 written on Reset)Note that NO bit operation instructions are possible.The input latch is activated on either the positive ornegative edge of the NMI (respectively PWRIN)signal: if NMIEDGE (resp. PWREDGE) is high thelatch will be triggered on the rising edge of the sig-nal at NMI (resp. PWRIN); if this bit is low the latchwill be triggered on the falling edge.An interrupt can be generated if it is enabled: ifNMINTEN (resp. PWINTEN) is high, then the out-put of the latch may generate an interrupt on vec-tor #0 (resp. vector #4); if this bit is low the inter-rupt is disabled.The status of the latch is read with NMIFLAG (re-sp. PWRFLAG): if NMIFLAG (resp. PWRFLAG) ishigh, a signal has been latched. The latch can bereset by setting NMIFLAG (resp. PWRFLAG).The VSYNC input is linked to the interrupt vector #2 through a latch.If 1 is written in VSYNCST the latch will be trig-gered on the rising edge of the signal at VSYNC, ifVSYNCST is low the latch will be triggered on thefalling edge (0 written on Reset).An interrupt can be generated only if VSYNCEN isat 1. Writing a 1 in VSYNCEN will also reset thelatch (0 written on Reset).The status of the latch is read through the bitVSYNCEN; reading a 1 means that a signal hasbeen latched.The status of the VSYNC pin is read with theVSYNCST bit.

7 0

- EL1 ES2 GEN - - - -

7 0

D7 D6 D5 D4 D3 D2 D1 D0

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INTERRUPTS (Contd)3.4.4 Interrupt ProcedureThe interrupt procedure is very similar to a call pro-cedure; the user can consider the interrupt as anasynchronous call procedure. As this is an asyn-chronous event the user does not know about thecontext and the time at which it occurred. As a re-sult the user should save all the data space regis-ters which will be used inside the interrupt rou-tines. There are separate sets of processor flagsfor normal, interrupt and non-maskable interruptmodes which are automatically switched and sothese do not need to be saved.The following list summarizes the interrupt proce-dure (refer also to Figure 20. Interrupt ProcessingFlow Chart): Interrupt detection The flags C and Z of the main routine are ex-

changed with the flags C and Z of the interruptroutine (resp. the NMI flags)

The value of the PC is stored in the first level ofthe stack - The normal interrupt lines are inhibit-ed (NMI still active)

The edge flip-flop is reset The related interrupt vector is loaded in the PC. User selected registers are saved inside the in-

terrupt service routine (normally on a softwarestack)

The source of the interrupt is found by polling (ifmore than one source is associated to the samevector)

Interrupt servicing Return from interrupt (RETI) Automatically the MCU Core switches back to

the normal flags (resp. the interrupt flags) andpops the previous PC value from the stack

The interrupt routine begins usually by the identifi-cation of the device that has generated the inter-rupt request. The user should save the registerswhich are used inside the interrupt routine (thatholds relevant data) into a software stack.After the RETI instruction execution, the Core car-ries out the previous actions and the main routinecan continue.

Figure 18. Interrupt Processing Flow-Chart

3.4.5 ST6373 Interrupt DetailsInterrupt #0. The NMI Interrupt is connected to thefirst interrupt #0 (NMI, Pin 27). If the NMI interruptis disabled at the latch circuitry, then it will be high.The #0 interrupt input detects a high to low level.Note that once #0 has been latched, then the onlyway to remove the latched #0 signal is to servicethe interrupt. #0 can interrupt the other interrupts.

LOAD PC FROMINTERRUPT VECTOR

( FFC / FFD )

SETINTERRUPT MASK

PUSH THEPC INTO THE STACK

SELECTINTERNAL MODE FLAG

CHECK IF THERE ISAN INTERRUPT REQUEST

AND INTERRUPT MASK

INSTRUCTION

WASTHE INSTRUCTION

A RETI

IS THE COREALREADY IN

NORMAL MODE ?

FETCHINSTRUCTION

EXECUTEINSTRUCTION

CLEARINTERRUPT MASK

SELECTPROGRAM FLAGS

POP THE STACKED PC

NO

NO

YES

YES

?

?NO

YES

VA000014

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INTERRUPTS (Contd)Interrupt #1. The TIMER 3 Interrupt and the PortA and B interrupts are connected by a logical ANDfunction to interrupt #1 (0FF6h). The TIMER 3 in-terrupt generates a low level (which is latched inthe timer) requiring that the Interrupt 1 Edge/Levelbit is set to 1. The I/O Port A and B interrupts maybe set to generate an interrupt on the falling edgeor low level state of the input (EL1 = 1 or EL1 = 0respectively) according to the external connec-tions.Note that if a low level is maintained on anI/O bit configured as acting on a Low Level afterthe interrupt is generated, the MCU will return tothe interrupt state after exiting the RETI instructionfrom the first interrupt service.Interrupt #2. The VSYNC, Timer 2 and I2C SPI In-terrupt are connected by a logical AND function tointerrupt #2. Bit 5 of the interrupt option registerC8h is used to select the negative edge (ES2=0)or the positive edge (ES2=1) to trigger the inter-rupt #2.For the correct operation of the Timer 2and I2C SPI interrupts, the falling edge should beselected (ES2 = 0).For the VSYNC interrupt, eitheredge can be selected, depending on the operationrequired. For example if the rising edge on VSYNCis the trigger, and after receiving the interruptedge, the VSYNC trigger level is switched to thefalling edge, the time between the rising and fallingedge (e.g. the display time) to be determined. TheVSYNC interrupt is controlled in Register NPVIRat address EDh.Note that once an edge has been latched, then theonly way to remove the latched signal is to servicethe interrupt. Care must be taken not to generatespurious interrupts. For example, changing theedge selection bit from falling edge to rising edgewhen the VSYNC input is high (or disabled in NP-

VIR) will cause a spurious interrupt.(see InterruptCircuit Diagram)Interrupt #3. The TIMER 1 and DDC SPI Interruptare connected by a logical AND function to inter-rupt #3. This interrupt is triggered on detection of alow level latched in the timer and DDC SPI.Interrupt #4. The PWRIN and Analog to DigitalConverter Interrupts are connected by a LogicalAND to interrupt #4 (0FF0h). The PWRIN interruptis controlled through the NPVIR Register at ad-dress EDh, and the Phase Unlock interrupt is con-trolled through SPCR at address DFh. The #4 in-terrupt input detects a low level. A simple latch isprovided from the PC4 (PWRIN) pin in order togenerate the PWRINT signal. This latch can betriggered by either the positive or negative edge ofthe PWRIN signal (bit 3, PWREDGE, of registerNPVIR EDh). The latch is reset by software.Notes:Global disable does not reset edge sensitive inter-rupt flags. These edge sensitive interrupts becomepending again when global disabling is released.Moreover, edge sensitive interrupts are stored inthe related flags also when interrupts are globallydisabled, unless each edge sensitive interrupt isalso individually disabled before the interruptingevent happens. Global disable is done by clearingthe GEN bit of Interrupt option register, while anyindividual disable is done in the control register ofthe peripheral. The on-chip Timer peripheralshave an interrupt request flag bit (TMZ), this bit isset to one when the device wants to generate aninterrupt request and a mask bit (ETI) that must beset to one to allow the transfer of the flag bit to theCore.

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INTERRUPTS (Contd)Figure 19. Interrupt Circuit Diagram

FF CLR

CLK

Q I0S

tart

Sta

rt1I

QCL

K CLR

FF

NMI

10 MUX

IOR

REG

.C8

H,bi

t6

IOR

REG.

C8H,

bit5

FF CLR

CLK

Q I 2St

art

INT

#4(FF

0,1)

INT

#3(FF

2,3)

INT

#2(FF

4,5)

INT

#1(FF

6,7)

INT

#0-

NMI(F

FC,D)

IOR

REG

C h,b

it4

:G

EN

RE S

TART

FRO

MST

OP/

WA I

T

FROM

REG

ISTE

RPO

RTA,

BSI

NGLE

BIT

ENAB

LE

VA04

26Q

V DD

PBE

PBE

PBE

PORT

A,B

Bits

NPVI

RBi

t6

DDV

NPV

IRBi

t2

FF CLR

CLK

Q

NPVI

RBI

T1

TIM

ER3

TSCR

3Bi

t6

V SYN

C

DDV

TIM

ER2

TSCR

2Bi

t6

SCR1

Bit5

IC

SPI

2

NPV

IRBi

t0

TIM

ER1

TSCR

1Bi

t6DD

CS P

I

V

PC4/

PWR

IN

DD

NPV

IRBi

t3CL

R NPVI

RBi

t5

QCL

KFF

NPV

IRBi

t4

ADC

ADCR

Bit7

SLAC

RBi

t1SC

R1Bi

t5

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3.5 POWER SAVING MODESSTOP and WAIT modes have been implementedin the ST638x in order to reduce the current con-sumption of the device during idle periods. Thesetwo modes are described in the following para-graphs. Since the hardware activated digitalwatchdog function is present, the STOP instruc-tion is de-activated and any attempt to execute itwill cause the automatic execution of a WAIT in-struction.3.5.1 WAIT ModeThe configuration of the MCU in the WAIT modeoccurs as soon as the WAIT instruction is execut-ed. The microcontroller can also be considered asbeing in a software frozen state where the Corestops processing the instructions of the routine,the contents of the RAM locations and peripheralregisters are saved as long as the power supplyvoltage is higher than the RAM retention voltagebut where the peripherals are still working. TheWAIT mode is used when the user wants to re-duce the consumption of the MCU when it is inidle, while not losing count of time or monitoring ofexternal events. The oscillator is not stopped in or-der to provide clock signal to the peripherals. Thetimers counting may be enabled (writing the PSIbit in TSCR1 register) and the timer interrupt maybe also enabled before entering the WAIT mode;this allows the WAIT mode to be left when timer in-terrupt occurs. If the exit from the WAIT mode isperformed with a general RESET (either from theactivation of the external pin or by watchdog reset)the MCU will enter a normal reset procedure asdescribed in the RESET chapter. If an interrupt isgenerated during WAIT mode the MCU behaviourdepends on the state of the MCU Core before theinitialization of the WAIT sequence, but also of thekind of the interrupt request that is generated. Thiscase will be described in the following paragraphs.In any case, the MCU Core does not generate anydelay after the occurrence of the interrupt becausethe oscillator clock is still available.3.5.2 STOP ModeSince the hardware activated watchdog is presenton the ST638x, the STOP instruction has been de-activated. Any attempt to execute a STOP instruc-tion will cause a WAIT instruction to be executedinstead.3.5.3 Exit from WAIT ModeThe following paragraphs describe the output pro-cedure of the MCU Core from WAIT mode whenan interrupt occurs. It must be noted that the re-start sequence depends on the original state of theMCU (normal, interrupt or non-maskable interrupt

mode) before the start of the WAIT sequence, butalso of the type of the interrupt request that is gen-erated. In all cases the GEN bit of IOR has to beset to 1 in order to restart from WAIT mode. Con-trary to the operation of NMI in the run mode, theNMI is masked in WAIT mode if GEN=0.Normal Mode. If the MCU Core was in the mainroutine when the WAIT instruction has been exe-cuted, the Core exits from WAIT mode as soon asan interrupt occurs; the corresponding interruptroutine is executed, and at the end of the interruptservice routine, the instruction that follows theWAIT instruction is executed if no other interruptsare pending.Non-maskable Interrupt Mode. If the WAIT in-struction has been executed during the executionof the non-maskable interrupt routine, the MCUCore outputs from WAIT mode as soon as any in-terrupt occurs: the instruction that follows theWAIT instruction is executed and the MCU Core isstill in the non-maskable interrupt mode even if an-other interrupt has been generated.Normal Interrupt Mode. If the MCU Core was inthe interrupt mode before the initialization of theWAIT sequence, it outputs from the wait mode assoon as any interrupt occurs. Nevertheless, twocases have to be considered: If the interrupt is a normal interrupt, the interrupt

routine in which the WAIT was entered will becompleted with the execution of the instructionthat follows the WAIT and the MCU Core is still inthe interrupt mode. At the end of this routinepending interrupts will be serviced in accordanceto their priority.

If the interrupt is a non-maskable interrupt, thenon-maskable routine is processed at first. Then,the routine in which the WAIT was entered will becompleted with the execution of the instructionthat follows the WAIT and the MCU Core is still inthe normal interrupt mode.

Notes:If all the interrupt sources are disabled, the restartof the MCU can only be done by a Reset activa-tion. The Wait instruction is not executed if an en-abled interrupt request is pending. In ST638x de-vices, the hardware activated digital watchdogfunction is present. As the watchdog is always ac-tivated, the STOP instruction is de-activated andany attempt to execute the STOP instruction willcause an execution of a WAIT instruction.

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4 ON-CHIP PERIPHERALS4.1 I/O PORTSThe ST6373 microcontroller uses three I/O ports(A,B,C) with up to eight pins on each port. Eachline can be individually programmed either in theinput mode or the output mode with the followingsoftware selectable options: Input without interrupt and without pull-up (Ports

A, B and C) Input with pull-up and with interrupt (PA0-PA5 and

Port B) Input with pull-up without interrupt (PA0-PA5 and

Port B, PC2-PC7) Analog Inputs (PB0-PB7) Open-drain output 12V, no pull-up (PC4-PC7) Open-drain output 5V (PA0-PA7, PB0-PB7,

PC0-PC3) Push-pull output (PA0-PA5, PB0-PB7) SPI control signals (PA6,PA7 for I2C SPI,

PC0,PC1,PC3 for DDC SPI) Horizontal Timing inputs (PC6/HSYNC,

PC7/HDRIV External Power In Interrupt (PC4)The lines are organized in three ports (Ports A, B,C). The ports occupy 8 registers in the data space.Each bit of these registers is associated with a par-ticular line (for instance, the bits 0 of the Port A Da-ta, Direction and Option registers are associatedwith the PA0 line of Port A).

The three Data registers (DRA, DRB, DRC) areused to read the voltage level values of the linesprogrammed in the input mode, or to write the logicvalue of the signal to be output on the lines config-ured in the output mode. The port Data Registerscan be read to get the effective logic levels of thepins, but they can be also written by the user soft-ware, in conjunction with the related Data Direc-tion Register and Option Register (Ports A and Bonly), to select the different input mode options.Single-bit operations on I/O registers (bit set/resetinstructions) are possible but care is necessarybecause reading in input mode is made from I/Opins and therefore might be influenced by the ex-ternal load, while writing will directly affect the Portdata register causing an undesired changes of theinput configuration.The three Data Direction registers (DDRA, DDRB,DDRC) allow the selection of the direction of eachpin (input or output).The two Option registers (ORA and ORB) are usedto select the different port options available both ininput and in output mode for Ports A and B only.All the I/O registers can be read or written as anyother RAM location of the data space, so no extraRAM cell is needed for port data storing and ma-nipulation. During the initialization of the MCU, allthe I/Oregisters are cleared and the input mode withpull-up is selected on all the pins thus avoiding pinconflicts (with the exception of PC2 which is set tooutput mode with the value 1 (high impedance).

Figure 20. I/O Port Block Diagram (PA0-PA5 and Port B)

VA000413

RESET

INPUT/OUTPUT

DATADIRECTIONREGISTER

S CONTROLSIN

DATAREGISTER

S

TO INTERRUPT

REGISTEROPTION

VDD

V DD

OUT

TO ADC

SHIFTREGISTER

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I/O PORTS (Contd)4.1.1 Details of I/O Ports A and BEach pin of Ports A and B can be individually pro-grammed as input or output with different inputand output configurations.This is achieved by writing the relevant bit in thedata register (DR), data direction register (DDR)and option register (OR). Table 8 shows all theport configurations that can be selected by usersoftware.4.1.1.1 Input Option DescriptionPull-up, High Impedance Option. All the inputlines can be individually programmed with or with-out an internal pull-up according to the codes pro-grammed in the OR and DR registers. If the pull-up

is not selected, the input pin is in the high imped-ance state.Interrupt Option. All the input lines can be individ-ually connected by software to the interrupt lines ofthe MCU core according to the codes programmedin the OR and DR registers. The pins of Port A andB are ORed and are connected to the interruptassociated to the vector #1.Analog Input Option. The PB0-PB7 pins can beconfigured to be analog inputs according to thecodes programmed in the OR and DR registers.These analog inputs are connected to the on-chip8-bit Analog to Digital Converter. ONLY ONE pinshould be programmed as analog input at a time,otherwise the selected inputs will be shorted.

Table 8. I/O Port Options Selection (Ports A and B only)

Note X: Means dont care.

DDR OR DR Mode Option0 0 0 Input With pull-up, no interrupt (Reset state)0 0 1 Input No pull-up, no interrupt0 1 0 Input With pull-up, with interrupt

0 1 1 Input No pull-up, no interrupt (Port A pins)Input Analog input (Port B pins)

1 0 X Output Open-drain output (10mA sink current for Port A pins)1 1 X Output Push-pull output (10mA sink current for Port A pins)

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I/O PORTS (Contd)4.1.1.2 Output Option DescriptionOutput OptionPort A and B pins in output modes can be set toOpen Drain or Push-Pull modes (not for PA6 andPA7). Port A bits set to output have a maximum10mA current sink LED drive capability.4.1.1.3 I2C SPI Input/OutputIf the user uses the I2C serial peripheral interface,the I/O lines PA6 and PA7 should be set in outputmode with the open-drain configuration; the corre-sponding data bit must set to one.Note. Switching the I/O ports with interrupt (PortsA and B) from one state to another should be donein a way that no unwanted side effects can hap-pen. The recommended safe transitions areshown below. All other transitions are risky andshould be avoided during change of operationmode as it is most likely that there will be an un-wanted side-effect such as interrupt generation ortwo pins shorted together by the analog inputlines.Single bit instructions (SET, RES, JRR and JRS)should be used very carefully with Port A and Bdata registers because these instructions make animplicit read and write back of the whole ad-dressed register byte. In port input mode howeverdata register address reads from input pins, notfrom data register latches and data register infor-mation in input mode is used to set characteristicsof the input pin (interrupt, pull-up, analog input),

therefore these characteristics may be uninten-tionally reprogrammed, depending on the state ofinput pins. As general rule is better to use single bitinstructions on data register only when the wholeport is in output mode. If input or mixed configura-tion is needed it is recommended to keep a copy ofthe data register in RAM. On this copy it is possibleto use single bit instructions, then the copy registercould be written into the port data register.SET bit, datacopyLD a, datacopyLD DRA, a4.1.2 Details of I/O Port CPort C. When programmed as an input an internalpull-up can be switched active under program con-trol. When programmed as an output the Port CI/O pins will operate in the open-drain mode. PC0-PC3 are available as open-drain capable of with-standing a maximum VDD+0.3V. PC4-PC7 areavailable as open-drain capable of withstanding12V and have no resistive pull-up in input mode.If the user uses the DDC serial peripheral inter-face, the I/O lines PC0 and PC1 should be set inoutput mode while the open-drain configuration ishardware fixed; the corresponding data bit mustset to one.If the latched interrupt functions areused (HSYNC,(HSYNC, HDRIVE, PWRIN) thenthe corresponding pins should be set to inputmode.

Figure 21. State Transition Diagram for Safe Transitions (Ports A and B)

Note*.xxx = DDR, OR, DR bits respectively

Interruptpull-up

OutputOpen Drain

OutputPush-pull

Inputpull-up (Resetstate)

InputAnalog

OutputOpen Drain

OutputPush-pull

Input

010*

000

100

110

011

001

101

111

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I/O PORTS (Contd)Table 9. I/O Port Option Selections

Note 1. Provided the correct configuration has been selected.

MODE AVAILABLE ON(1) SCHEMATIC

InputPA0-PA7PB0-PB7PC0-PC7

Inputwith pull up

PA0-PA5PB0-PB7PC2, PC3

Inputwith pull up

with interrupt

PA0-PA5PB0-PB7

Analog Input PB0-PB7

Open drain output5mA / VDD +0.3VOpen drain output10mA / VDD +0.3VOpen drain output

5mA / 12V

PB0-PB7PC0-PC7PA0-PA7

PC4-PC7

Push-pull output5mA

Push-pull output10mA

PB0-PB7

PA0-PA5

Data in

Interrupt

Data in

Interrupt

Data in

Interrupt

Data out

ADC

Data out

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I/O PORTS (Contd)4.1.2.1 Port C I/O Pin ProgrammingEach Port C pin can be individually programmedas input or output. This is achieved by writing tothe relevant bit in the data (DRC) and data direc-tion register (DDRC). Table 9 shows all the portconfigurations that can be selected by the usersoftware.4.1.2.2 Port C Input/Output ConfigurationsThe following schematics show the I/O lines hard-ware configuration for the different options. Figure31 shows the I/O configuration for an I/O pin withopen-drain 12V capability (standard drive and highdrive). Figure 32 shows the I/O configuration for anI/O pin with open-drain 5V capability.Note:All the Port A, B and C I/O lines have Schmitt-trig-ger input configuration with a typical hysteresis of1V.

Table 10. I/O Port Options Selection (Port C)

Note: X. Means dont care.

Figure 22. I/O Configuration Diagram(Open Drain 12V)

Figure 23. I/O Configuration Diagram (Open Drain 5V)

DDR DR Mode Option0 0 Input With on-chip pull-up resistor0 1 Input Without on-chip pull-up resistor1 X Output Open-drain

VA00342

I/O

N

In

Out

I/O HIGH DRIVE, OPEN DRAIN 12V

(5mA, 1V)

DDV

Out

In

N

I/O (OPEN-DRAIN, 5V)

VA00345A

OPEN-DRAIN OUTPUT

In Input mode only, SW programmable ( 200k )

*

*~

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4.1.3 I/O Port Registers4.1.3.1 Data RegistersPorts A, B, C Data RegisterAddress: C0h (PA), C1h (PB), C2h (PC) -Read/WriteReset Value: 00h

PA7-PA0. These are the I/O Port A data bits. Re-set at power-on.PB7-PB0. These are the I/O Port B data bits. Re-set at power-on.PC7-PC0. These are the I/O Port C data bits. Setto 04H at power-on. Bit 2 (PC2 pin) is set to one(open-drain therefore high impedance).4.1.3.2 Data Direction RegistersPorts A, B, C Data Direction RegisterAddress: C4h (PA), C5h (PB), C6h (PC) -Read/WriteReset Value: 00h

PA7-PA0. These are the I/O Port A data directionbits. When a bit is cleared to zero the related I/Oline is in input mode, if bit is set to one the relatedI/O line is in output mode. Reset at power-on.PB7-PB0. These are the I/O Port B data directionbits. When a bit is cleared to zero the related I/O

line is in input mode, if bit is set to one the relatedI/O line is in output mode. Reset at power-on.PC7-PC0. These are the I/O Port C data directionbits. When a bit is cleared to zero the related I/Oline is in input mode, if bit is set to one the relatedI/O line is in output mode. Set to 04H at power-on.Bit 2 (PC2 pin) is set to one (output mode select-ed).4.1.3.3 Option RegistersPort A, B, C Option RegisterAddress: CCh (PA), CDh (PB) - Read/WriteReset value:00h

PA7-PA0. These are the I/O Port A option bits.These are set in conjunction with the correspond-ing data and data direction bits to set the individualPort A bit I/O mode.PB7-PB0. These are the I/O Port B option bits.These are set in conjunction with the correspond-ing data and data direction bits to set the individualPort B bit I/O mode.Notes: The WAIT instruction allows the MCU to beused in situations where low power consumption isrequired. This can only be achieved, however, ifthe I/O pins are programmed as inputs with welldefined logic levels or have no power consumingresistive loads in output mode.Single-bit operations on I/O registers are possiblebut care is necessary because reading in inputmode is from I/O pins while writing will directly af-fect the Port data register.

7 0

PA/PB/PC7

PA/PB/PC6

PA/PB/PC5

PA/PB/PC4

PA/PB/PC3

PA/PB/PC2

PA/PB/PC1

PA/PB/PC0

7 0

PA/PB/PC7

PA/PB/PC6

PA/PB/PC5

PA/PB/PC4

PA/PB/PC3

PA/PB/PC2

PA/PB/PC1

PA/PB/PC0

7 0

PA/PB7 PA/PB6 PA/PB5 PA/PB4PA/PB3 PA/PB2 PA/PB1 PA/PB0

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4.2 TIMERSThe ST638x devices offer two on-chip Timer pe-ripherals consisting of an 8-bit counter with a 7-bitprogrammable prescaler, thus giving a maximumcount of 215, and a control logic that allows config-uration the peripheral operating mode. Figure 1shows the Timer block diagram. The content of the8-bit counters can be read/written in the Tim-er/Counter registers TCR that are addressed inthe data space as RAM locations at addressesD3h (Timer 1), DBh (Timer 2). The state of the 7-bit prescaler can be read in the PSC register at ad-dresses D2h (Timer 1) and DAh (Timer 2). Thecontrol logic is managed by TSCR registers at D4h(Timer 1) and DCh (Timer 2) addresses as de-scribed in the following paragraphs.The following description applies to all Timers. The8-bit counter is decrement by the output (risingedge) coming from the 7-bit prescaler and can beloaded and read under program control. When itdecrements to zero then the TMZ (timer zero) bit inthe TSCR is set to one. If the ETI (enable timer in-terrupt) bit in the TSCR is also set to one an inter-rupt request, associated to interrupt vector #3 forTimer 1 and #1 for Timer 2, is generated. The in-terrupt of the timer can be used to exit the MCUfrom the WAIT mode.

The prescaler decrements on rising edge. Theprescaler input is the oscillator frequency dividedby 12. Depending on the division factor pro-grammed by PS2/PS1/PS0 (seeTable 1 ) bits inthe TSCR, the clock input of the timer/counter reg-ister is multiplexed to different sources. On divi-sion factor 1, the clock input of the prescaler isalso that of timer/counter; on factor 2, bit 0 of pres-caler register is connected to the clock input ofTCR.This bit changes its