EE136
STABILITY AND CONTROL LOOP COMPENSATION IN
SWITCH MODE POWER SUPPLY
Present By Huyen Tran
STABILITY AND CONTROL LOOP COMPENSATION IN SWITCH MODE POWER SUPPLY
potential risk for oscillation in a closed loop control system methods of stabilizing the loop
Methods of stabilizing the loop
• By Circuit and Mathematical Analysis-Required “fine tuning”
• Interrogative Methods of Loop Stabilization
-A “difference techniques” can be used to establish the required characteristics of the compensated control amplifier.
Methods of stabilizing the loop
Type 1 Compensation
+
-
OUT
R1
C1
Vi
VREF
0
Vo
11
1
CsRV
V
I
O
Methods of stabilizing the loop
• Type 2 Compensation
+
-
.
R1
C1
Vi
VREF
0
Vo
R2
C2
PZ
I
OC ss
s
CRV
VH
21
1
Methods of stabilizing the loop
• Type 3 Compensation
+
-
.
R1
C1
Vi
VREF
0
Vo
R2
C2
R3C3
21
21233211
33112
11
11
CC
CCsRCRCCsR
CRRsCsR
V
VF
I
OC
Stability testing methods
• One of these method is transient load testing
-the transfer function changes under different loading conditions.
Set up the transient load test
Analysis for transient test
Analysis for transient test
• For an under damped response, it will have a poor gain and phase margins and maybe only conditional stable. With this performance, the oscillation may occur.
• For an over damped response, it is very stable, but does not give the best transient recovery performance.
• For waveform c, it is stable transient response, and it will provide enough gain and phase margin for most application.
Measurement procedure for the closed- loop
power supply systems
Measurement procedure for the closed- loop power supply systems
• voltmeter V1 is used to measure the ac input of control amplifier
• voltmeter V2 is used to measure the ac output voltage of power supply for each time changing the frequency
A typical Bode plot
Design example
Stabilizing a Forward Converter Feedback Loop with a Type 2 Error Amplifier
• V0 = 5V• I0(nom) =10A• Minimum I0 = 1A• Switching frequency = 100 kHz• Minimum out put ripple = 50mV
Design example
• calculate Lo and Co
onI
TVL 0
0
3 H6
6
101510
1053
orO V
dIC 61065 F2600
0.05
21065 6-
And the cutoff frequency of the output LC filter Is
HzCL OO
80610260010152
1
2
1f
66o
Design example
• the frequency of the ESR zero is
HzCR Oesr
250010652
1
2
1f
6esr
Then the modulator gain :
dBV
G SPm 5.467.1
3
)111(5.0
3
)1(5.0
DVT
DTV
T
TVSP
onSPonSP )1()1()1(
VO
Design example• Then the total open
loop gain Gt = Glc + Gm +Gs is draw in fig.1
Design example
• At very low frequency, it is a straight line with -1.5dB and then it hit 2 poles at the frequency which is 806 Hz and start rolling down with slope of -40dB/dec until it hit a zero at 2500 Hz, and the line still rolling down but the slope only -20dB/dec.
Design example
U 1
O P A M P
+
-
O U T
R 1
1 k
R 2
1 0 0 k
C 1
3 1 8 p
0
V 11 V a c0 V d c
C 3
2 0 p
fz = 5kHz, fp =80 kHz, gain 40