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TRM

CY8C22x45CY8C21345

PSoC® Programmable System-on-Chip™Technical Reference Manual (TRM)

PSoC TRM, Spec. # 001-48461 Rev. *B

July 15, 2011Cypress Semiconductor

198 Champion CourtSan Jose, CA 95134-1709

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2 PSoC TRM, Spec. # 001-48461 Rev. *B

Copyrights

Copyrights

Copyright © 2008-2011 Cypress Semiconductor Corporation. All rights reserved.

PSoC® and CapSense® are registered trademarks and PSoC Designer™ and Programmable System-on-Chip™ are trade-marks of Cypress Semiconductor Corporation (Cypress), along with Cypress® and Cypress Semiconductor™. All othertrademarks or registered trademarks referenced herein are the property of their respective owners.

Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Phil-ips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C StandardSpecification as defined by Philips. As from October 1st, 2006, Philips Semiconductors has a new trade name - NXP Semi-conductors.

The information in this document is subject to change without notice and should not be construed as a commitment byCypress. While reasonable precautions have been taken, Cypress assumes no responsibility for any errors that may appearin this document. No part of this document may be copied or reproduced in any form or by any means without the prior writtenconsent of Cypress. Made in the U.S.A.

Disclaimer

CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PAR-TICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein.Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypressdoes not authorize its products for use as critical components in life-support systems where a malfunction or failure may rea-sonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems appli-cation implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Flash Code Protection

Note the following details of the Flash code protection features on Cypress devices.

Cypress products meet the specifications contained in their particular Cypress Data Sheets. Cypress believes that its family ofproducts is one of the most secure families of its kind on the market today, regardless of how they are used. There may bemethods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, wouldbe dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security oftheir code. Code protection does not mean that we are guaranteeing the product as "unbreakable."

Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantlyevolving. We at Cypress are committed to continuously improving the code protection features of our products.



PSoC TRM, Spec. # 001-48461 Rev. *B 3

Contents Overview

Section A: Overview 191. Pin Information .................................................................................................................. 25

Section B: PSoC Core 292. CPU Core (M8C) ............................................................................................................... 353. Supervisory ROM (SROM) ................................................................................................. 454. RAM Paging ...................................................................................................................... 555. Interrupt Controller ............................................................................................................ 636. General Purpose IO (GPIO) ............................................................................................... 717. Internal Main Oscillator (IMO) ............................................................................................ 798. Internal Low Speed Oscillator (ILO) ................................................................................... 839. External Crystal Oscillator (ECO) ....................................................................................... 8510. Phase-Locked Loop (PLL) ............................................................................................... 9111. Sleep and Watchdog ........................................................................................................ 95

Section C: Register Reference 10712. Register Details ..............................................................................................................111

Section D: Digital System 27713. Global Digital Interconnect (GDI) ................................................................................... 28114. Array Digital Interconnect (ADI) ..................................................................................... 28915. Row Digital Interconnect (RDI) ....................................................................................... 29116. Digital Blocks ................................................................................................................ 299

Section E: Analog System 34517. Two Column Limited Analog System .............................................................................. 34918. Two Column Analog Compare System............................................................................ 369

Section F: System Resources 38519. Digital Clocks ................................................................................................................ 38920. Multiply Accumulate (MAC) ............................................................................................ 39921. I2C ................................................................................................................................ 40522. Internal Voltage Reference ............................................................................................ 42523. System Resets .............................................................................................................. 42724. POR and LVD ................................................................................................................ 43525. IO Analog Multiplexer .................................................................................................... 43926. CSD Logic System......................................................................................................... 44727. Real Time Clock (RTC) .................................................................................................. 45528. 10-Bit SAR ADC Controller ............................................................................................ 45929. MISC Logic ................................................................................................................... 467

Section G: Glossary 473



Contents Overview





Contents

Section A: Overview 19Document Organization ..................................................................................................................19Top-Level Architecture ....................................................................................................................20

PSoC Core ..............................................................................................................................20Digital System .........................................................................................................................20 ................................................................................................................................................20Analog System ........................................................................................................................20System Resources ..................................................................................................................20

PSoC Device Characteristics ..........................................................................................................22Getting Started ...............................................................................................................................22

Support ...................................................................................................................................22Product Upgrades ...................................................................................................................22Development Kits ...................................................................................................................22

Document History .............................................................................................................................22Documentation Conventions ..........................................................................................................23

Register Conventions ............................................................................................................23Numeric Naming ....................................................................................................................23Units of Measure ..................................................................................................................23Acronyms ...............................................................................................................................23

1. Pin Information 251.1 Pinouts ..................................................................................................................................25

1.1.1 28-Pin Part Pinout .......................................................................................................261.1.2 44-Pin Part Pinout .......................................................................................................271.1.3 56-Pin Part Pinout .......................................................................................................28

Section B: PSoC Core 29Top Level Core Architecture ............................................................................................................29Interpreting the Core Documentation ...............................................................................................30Core Register Summary ...................................................................................................................31

2. CPU Core (M8C) 352.1 Overview.................................................................................................................................352.2 Internal Registers .................................................................................................................352.3 Address Spaces ....................................................................................................................352.4 Instruction Set Summary ........................................................................................................362.5 Instruction Formats ...............................................................................................................38

2.5.1 One-Byte Instructions..................................................................................................382.5.2 Two-Byte Instructions..................................................................................................382.5.3 Three-Byte Instructions ...............................................................................................39

2.6 Addressing Modes ................................................................................................................392.6.1 Source Immediate .......................................................................................................39




Contents

2.6.2 Source Direct ..............................................................................................................402.6.3 Source Indexed...........................................................................................................402.6.4 Destination Direct .......................................................................................................412.6.5 Destination Indexed ...................................................................................................412.6.6 Destination Direct Source Immediate .........................................................................412.6.7 Destination Indexed Source Immediate......................................................................422.6.8 Destination Direct Source Direct.................................................................................422.6.9 Source Indirect Post Increment ..................................................................................432.6.10 Destination Indirect Post Increment............................................................................43

2.7 Register Definitions ...............................................................................................................442.7.1 CPU_F Register .........................................................................................................44

3. Supervisory ROM (SROM) 453.1 Architectural Description ........................................................................................................45

3.1.1 Additional SROM Feature...........................................................................................463.1.2 SROM Function Descriptions ....................................................................................46

3.1.2.1 SWBootReset Function...............................................................................463.1.2.2 ReadBlock Function ....................................................................................473.1.2.3 WriteBlock Function ....................................................................................473.1.2.4 EraseBlock Function ...................................................................................483.1.2.5 ProtectBlock Function .................................................................................493.1.2.6 TableRead Function ...................................................................................493.1.2.7 EraseAll Function ........................................................................................493.1.2.8 Checksum Function.....................................................................................503.1.2.9 Calibrate0 Function .....................................................................................503.1.2.10 Calibrate1 Function .....................................................................................50

3.2 PSoC Device Distinctions.......................................................................................................503.3 Register Definitions ..............................................................................................................50

3.3.1 STK_PP Register .......................................................................................................513.3.2 MVR_PP Register ......................................................................................................513.3.3 MVW_PP Register .....................................................................................................513.3.4 CPU_SCR1 Register .................................................................................................523.3.5 FLS_PR1 Register .....................................................................................................53

3.4 Clocking ................................................................................................................................543.4.1 DELAY Parameter.......................................................................................................543.4.2 CLOCK Parameter......................................................................................................54

4. RAM Paging 554.1 Architectural Description ........................................................................................................55

4.1.1 Basic Paging ..............................................................................................................554.1.2 Stack Operations .......................................................................................................554.1.3 Interrupts ....................................................................................................................574.1.4 MVI Instructions .........................................................................................................574.1.5 Current Page Pointer .................................................................................................574.1.6 Index Memory Page Pointer ......................................................................................57

4.2 Register Definitions ...............................................................................................................594.2.1 TMP_DRx Registers ..................................................................................................594.2.2 CUR_PP Register ......................................................................................................594.2.3 STK_PP Register .......................................................................................................604.2.4 IDX_PP Register ........................................................................................................614.2.5 MVR_PP Register ......................................................................................................614.2.6 MVW_PP Register .....................................................................................................62




Contents

4.2.7 CPU_F Register ..........................................................................................................62

5. Interrupt Controller 635.1 Architectural Description.........................................................................................................63

5.1.1 Posted versus Pending Interrupts ...............................................................................645.2 Application Description ..........................................................................................................655.3 Register Definitions ................................................................................................................66

5.3.1 INT_CLRx Registers ..............................................................................................665.3.1.1 INT_CLR0 Register .....................................................................................665.3.1.2 INT_CLR1 Register .....................................................................................665.3.1.3 INT_CLR2 Register .....................................................................................675.3.1.4 INT_CLR3 Register .....................................................................................67

5.3.2 INT_MSKx Registers ..............................................................................................685.3.2.1 INT_MSK3 Register.....................................................................................685.3.2.2 INT_MSK2 Register.....................................................................................685.3.2.3 INT_MSK0 Register.....................................................................................685.3.2.4 INT_MSK1 Register.....................................................................................69

5.3.3 INT_VC Register ........................................................................................................695.3.4 CPU_F Register .........................................................................................................69

6. General Purpose IO (GPIO) 716.1 Architectural Description.........................................................................................................71

6.1.1 Digital IO ....................................................................................................................716.1.2 Global IO ....................................................................................................................726.1.3 Analog Input ...............................................................................................................736.1.4 GPIO Block Interrupts ...............................................................................................74

6.2 Register Definitions ................................................................................................................756.2.1 PRTxDR Registers .....................................................................................................756.2.2 PRTxIE Registers .......................................................................................................756.2.3 PRTxGS Registers .....................................................................................................756.2.4 PRTxDMx Registers ................................................................................................766.2.5 PRTxICx Registers ...................................................................................................77

7. Internal Main Oscillator (IMO) 797.1 Architectural Description.........................................................................................................797.2 PSoC Device Distinctions .......................................................................................................797.3 Application Description ...........................................................................................................80

7.3.1 Trimming the IMO .......................................................................................................807.3.2 Engaging Slow IMO ....................................................................................................80

7.4 Register Definitions ................................................................................................................817.4.1 CPU_SCR1 Register ..................................................................................................817.4.2 OSC_CR2 Register ....................................................................................................827.4.3 IMO_TR Register .......................................................................................................82

8. Internal Low Speed Oscillator (ILO) 838.1 Architectural Description.........................................................................................................838.2 Register Definitions ................................................................................................................83

8.2.1 ILO_TR Register ........................................................................................................83

9. External Crystal Oscillator (ECO) 859.1 Architectural Description.........................................................................................................85




Contents

9.1.1 ECO External Components.........................................................................................869.2 PSoC Device Distinctions.......................................................................................................869.3 Register Definitions ...............................................................................................................87

9.3.1 CPU_SCR1 Register .................................................................................................879.3.2 OSC_CR0 Register ...................................................................................................889.3.3 ECO_TR Register ......................................................................................................89

10. Phase-Locked Loop (PLL) 9110.1 Architectural Description.........................................................................................................9110.2 Register Definitions ..............................................................................................................91

10.2.1 OSC_CR0 Register ....................................................................................................9210.2.2 OSC_CR2 Register ...................................................................................................93

11. Sleep and Watchdog 9511.1 Architectural Description.........................................................................................................95

11.1.1 32 kHz Clock Selection ..............................................................................................9511.1.2 Sleep Timer ..............................................................................................................95

11.2 Application Description ...........................................................................................................9611.3 Register Definitions ...............................................................................................................97

11.3.1 INT_MSK0 Register ...................................................................................................9711.3.2 RES_WDT Register ...................................................................................................9711.3.3 CPU_SCR1 Register .................................................................................................9811.3.4 CPU_SCR0 Register .................................................................................................9911.3.5 OSC_CR0 Register .................................................................................................10011.3.6 OSC_CR2 Register ...............................................................................................10111.3.7 ILO_TR Register ......................................................................................................10211.3.8 ECO_TR Register ....................................................................................................102

11.4 Timing Diagrams ..................................................................................................................10311.4.1 Sleep Sequence .......................................................................................................10311.4.2 Wake Up Sequence ..................................................................................................10411.4.3 Bandgap Refresh......................................................................................................10511.4.4 Watchdog Timer........................................................................................................105

11.5 Power Consumption .............................................................................................................106

Section C: Register Reference 107Register General Conventions .......................................................................................................107Register Naming Conventions .......................................................................................................107Register Mapping Tables ...............................................................................................................107

Register Map Bank 0 Table: User Space ..........................................................................108Register Map Bank 1 Table: Configuration Space .............................................................109

12. Register Details 11112.1 Maneuvering Around the Registers ......................................................................................111

Register Conventions .........................................................................................................11112.1.1 Register Naming Conventions ................................................................................. 111

12.2 Bank 0 Registers .................................................................................................................11312.2.1 PRTxDR ...................................................................................................................11312.2.2 PRTxIE ....................................................................................................................11412.2.3 PRTxGS ...................................................................................................................11512.2.4 PRTxDM2 ................................................................................................................11612.2.5 DxCxxDR0 ...............................................................................................................11712.2.6 DxCxxDR1 ...............................................................................................................118




Contents

12.2.7 DxCxxDR2 ...............................................................................................................11912.2.8 DxCxxCR0 (Timer Control:000) ...............................................................................12012.2.9 DxCxxCR0 (Counter Control:001) ............................................................................12112.2.10DxCxxCR0 (Dead Band Control:100) .....................................................................12212.2.11DxCxxCR0 (CRCPRS Control:010) .........................................................................12312.2.12DxCxxCR0 (IPWM Control:011) ..............................................................................12412.2.13DCCxxCR0 (SPIM Control:0-110) ...........................................................................12512.2.14DCCxxCR0 (SPIS Control:1-110) ............................................................................12612.2.15DxCxxCR0 (DSM Control:111) ................................................................................12712.2.16DCCxxCR0 (UART Transmitter Control) .................................................................12812.2.17DCCxxCR0 (UART Receiver Control) .....................................................................12912.2.18CSDx_DR0_L, CSDx_DR0_H .................................................................................13012.2.19CSDx_DR1_L, CSDx_DR1_H .................................................................................13112.2.20CSDx_CNT_L, CSDx_CNT_H .................................................................................13212.2.21CSDx_CR0 ..............................................................................................................13312.2.22CSDx_CR1 ..............................................................................................................13412.2.23AMX_IN ...................................................................................................................13512.2.24AMUX_CFG .............................................................................................................13612.2.25PWM_CR .................................................................................................................13712.2.26ARF_CR ..................................................................................................................13812.2.27CMP_CR0 ................................................................................................................13912.2.28CMP_CR1 ................................................................................................................14012.2.29ADCx_CR ................................................................................................................14112.2.30ADC_DH ..................................................................................................................14212.2.31ADC_DL ...................................................................................................................14312.2.32TMP_DRx ................................................................................................................14412.2.33ACExxCR1 ...............................................................................................................14512.2.34ACExxCR2 ...............................................................................................................14712.2.35ASExxCR0 ...............................................................................................................14812.2.36RDIxRI .....................................................................................................................14912.2.37RDIxSYN .................................................................................................................15012.2.38RDIxIS .....................................................................................................................15112.2.39RDIxLT0 ...................................................................................................................15212.2.40RDIxLT1 ...................................................................................................................15312.2.41RDIxRO0 .................................................................................................................15412.2.42RDIxRO1 .................................................................................................................15512.2.43RDIxDSM .................................................................................................................15612.2.44PWMVREF0 ............................................................................................................15712.2.45PWMVREF1 ............................................................................................................15812.2.46IDAC_MODE ...........................................................................................................15912.2.47PWMSRC ................................................................................................................16012.2.48TS_CR0 ...................................................................................................................16112.2.49TS_CMPH ................................................................................................................16212.2.50TS_CMPL ................................................................................................................16312.2.51TS_CR1 ...................................................................................................................16412.2.52CUR_PP ..................................................................................................................16512.2.53STK_PP ...................................................................................................................16612.2.54IDX_PP ....................................................................................................................16712.2.55MVR_PP ..................................................................................................................16812.2.56MVW_PP .................................................................................................................16912.2.57I2C_CFG ..................................................................................................................17012.2.58I2C_SCR ..................................................................................................................17112.2.59I2C_DR ....................................................................................................................173




Contents

12.2.60I2C_MSCR ..............................................................................................................17412.2.61INT_CLR0 ................................................................................................................17512.2.62INT_CLR1 ................................................................................................................17712.2.63INT_CLR2 ................................................................................................................17912.2.64INT_CLR3 ................................................................................................................18012.2.65INT_MSK3 ...............................................................................................................18112.2.66INT_MSK2 ...............................................................................................................18212.2.67INT_MSK0 ...............................................................................................................18312.2.68INT_MSK1 ...............................................................................................................18412.2.69INT_VC ....................................................................................................................18512.2.70RES_WDT ...............................................................................................................18612.2.71DEC_CR0 ...............................................................................................................18712.2.72DEC_CR1 ................................................................................................................18812.2.73MULx_X ...................................................................................................................18912.2.74MULx_Y ...................................................................................................................19012.2.75MULx_DH ................................................................................................................19112.2.76MULx_DL .................................................................................................................19212.2.77MACx_X/ACCx_DR1 ...............................................................................................19312.2.78MACx_Y/ACCx_DR0 ...............................................................................................19412.2.79MACx_CL0/ACCx_DR3 ...........................................................................................19512.2.80MACx_CL1/ACCx_DR2 ...........................................................................................19612.2.81CPU_F ................................................................................................................19712.2.82IDACx_D ..................................................................................................................19812.2.83CPU_SCR1 ........................................................................................................19912.2.84CPU_SCR0 .............................................................................................................200

12.3 Bank 1 Registers .................................................................................................................20112.3.1 PRTxDM0 ................................................................................................................20112.3.2 PRTxDM1 ................................................................................................................20212.3.3 PRTxIC0 ..................................................................................................................20312.3.4 PRTxIC1 ..................................................................................................................20412.3.5 DxCxxFN .................................................................................................................20512.3.6 DxCxxIN ...................................................................................................................20712.3.7 DxCxxOU .................................................................................................................20912.3.8 DxCxxCR1 (Timer Control:000) ...............................................................................21112.3.9 DxCxxCR1 (Counter Control:001) ...........................................................................21212.3.10DxCxxCR1 (CRCPRS Control:010) .........................................................................21312.3.11DxCxxCR1 (IPWM Control:011) ..............................................................................21412.3.12DxCxxCR1 (Dead Band Control:100) ......................................................................21512.3.13DxCxxCR1 (SPIM Control:0-110) ............................................................................21612.3.14DxCxxCR1 (SPIS Control:0-110) ............................................................................21712.3.15DxCxxCR1 (DSM Control:111) ................................................................................21812.3.16CMPxCR1 ................................................................................................................21912.3.17CMPxCR2 ................................................................................................................22012.3.18VDAC5xCR0 ............................................................................................................22112.3.19CSCMPCR0 ............................................................................................................22212.3.20CSCMPGOEN .........................................................................................................22312.3.21CSLUTCR0 ..............................................................................................................22412.3.22CMPCOLMUX .........................................................................................................22512.3.23CMPPWMCR ...........................................................................................................22612.3.24CMPFLTCR .............................................................................................................22712.3.25CMPCLK1 ................................................................................................................22812.3.26CMPCLK0 ................................................................................................................22912.3.27CLK_CR0 ................................................................................................................230




Contents

12.3.28CLK_CR1 .................................................................................................................23112.3.29ABF_CR0 .............................................................................................................23212.3.30AMD_CR0 ................................................................................................................23312.3.31CMP_GO_EN ..........................................................................................................23412.3.32AMD_CR1 ................................................................................................................23512.3.33ALT_CR0 .................................................................................................................23612.3.34AMUX_CFG1 ...........................................................................................................23812.3.35CLK_CR3 .................................................................................................................23912.3.36GDI_O_IN_CR .........................................................................................................24012.3.37GDI_E_IN_CR .........................................................................................................24112.3.38GDI_O_OU_CR .......................................................................................................24212.3.39GDI_E_OU_CR .......................................................................................................24312.3.40RTCH .......................................................................................................................24412.3.41RTCM ......................................................................................................................24512.3.42RTCS .......................................................................................................................24612.3.43RTCCR ....................................................................................................................24712.3.44ADC_CR0 ................................................................................................................24812.3.45ADC_CR1 ................................................................................................................24912.3.46ADC_CR2 ................................................................................................................25012.3.47ADC_CR3TRIM .......................................................................................................25112.3.48ADC_CR4 ................................................................................................................25212.3.49I2C_ADDR ...............................................................................................................25312.3.50GDI_O_IN ................................................................................................................25412.3.51GDI_E_IN ................................................................................................................25512.3.52GDI_O_OU ..............................................................................................................25612.3.53GDI_E_OU ...............................................................................................................25712.3.54MUX_CRx ................................................................................................................25812.3.55IDAC_CR1 ...............................................................................................................25912.3.56OSC_GO_EN ..........................................................................................................26012.3.57OSC_CR4 ................................................................................................................26112.3.58OSC_CR3 ................................................................................................................26212.3.59OSC_CR0 ............................................................................................................26312.3.60OSC_CR1 ................................................................................................................26412.3.61OSC_CR2 .............................................................................................................26512.3.62VLT_CR ...................................................................................................................26612.3.63VLT_CMP ................................................................................................................26712.3.64ADCx_TR .................................................................................................................26812.3.65VDAC_TRIM ............................................................................................................26912.3.66IMO_TR ...................................................................................................................27012.3.67ILO_TR ....................................................................................................................27112.3.68BDG_TR .................................................................................................................27212.3.69ECO_TR ..................................................................................................................27312.3.70FLS_PR1 ................................................................................................................27412.3.71IDAC_CR0 ...............................................................................................................275

Section D: Digital System 277Top-Level Digital Architecture ........................................................................................................277Interpreting the Digital Documentation ...........................................................................................277Digital Register Summary ..............................................................................................................278

13. Global Digital Interconnect (GDI) 28113.1 Architectural Description ......................................................................................................281




Contents

13.1.1 28-Pin Global Interconnect .......................................................................................28113.1.2 44-Pin Global Interconnect .....................................................................................28213.1.3 56-Pin Global Interconnect ......................................................................................283

13.2 Register Definitions .............................................................................................................28413.2.1 GDI_x_IN Registers/GDI_x_IN_CR Registers .........................................................28413.2.2 GDI_x_OU/GDI_x_OU_CR Registers .....................................................................286

14. Array Digital Interconnect (ADI) 28914.1 Architectural Description.......................................................................................................289

15. Row Digital Interconnect (RDI) 29115.1 Architectural Description.......................................................................................................29115.2 PSoC Device Distinctions.....................................................................................................29215.3 Register Definitions .............................................................................................................293

15.3.1 RDIxRI Register .......................................................................................................29315.3.2 RDIxSYN Register ...................................................................................................29415.3.3 RDIxIS Register .......................................................................................................29515.3.4 RDIxLTx Registers .................................................................................................29615.3.5 RDIxROx Registers ...............................................................................................297

15.3.5.1 RDIxRO0 Register.....................................................................................29715.3.5.2 RDIxRO1 Register.....................................................................................297

15.3.6 RDIxDSM Register ..................................................................................................29815.4 Timing Diagram ..................................................................................................................298

16. Digital Blocks 29916.1 Architectural Description.......................................................................................................299

16.1.1 Input Multiplexers .....................................................................................................30016.1.2 Input Clock Resynchronization ................................................................................300

16.1.2.1 Clock Resynchronization Summary ..........................................................30116.1.3 Output De-Multiplexers ............................................................................................30116.1.4 Block Chaining Signals ............................................................................................30116.1.5 Input Data Synchronization.......................................................................................30116.1.6 Timer Function .........................................................................................................301

16.1.6.1 Usability Exceptions ..................................................................................30216.1.6.2 Block Interrupt ...........................................................................................302

16.1.7 Counter Function .....................................................................................................30216.1.7.1 Counter Timing..........................................................................................30216.1.7.2 Usability Exceptions ..................................................................................30316.1.7.3 Block Interrupt ...........................................................................................303

16.1.8 Dead Band Function ................................................................................................30316.1.8.1 Usability Exceptions ..................................................................................30416.1.8.2 Block Interrupt ...........................................................................................304

16.1.9 IPWM Function .........................................................................................................30416.1.9.1 Usability Exceptions ..................................................................................30516.1.9.2 Block Interrupt ...........................................................................................305

16.1.10CRCPRS Function ...................................................................................................30516.1.10.1 Usability Exceptions ..................................................................................30616.1.10.2 Block Interrupt ...........................................................................................306

16.1.11SPI Protocol Function ..............................................................................................30616.1.11.1 SPI Protocol Signal Definitions..................................................................307

16.1.12SPI Master Function ................................................................................................30716.1.12.1 Usability Exceptions ..................................................................................308




Contents

16.1.12.2 Block Interrupt ...........................................................................................30816.1.13SPI Slave Function ..................................................................................................308

16.1.13.1 Usability Exceptions ..................................................................................30816.1.13.2 Block Interrupt ...........................................................................................308

16.1.14Asynchronous Transmitter and Receiver Functions .............................................30916.1.14.1 Asynchronous Transmitter Function..........................................................30916.1.14.2 Usability Exceptions ..................................................................................30916.1.14.3 Block Interrupt ...........................................................................................30916.1.14.4 Asynchronous Receiver Function..............................................................30916.1.14.5 Usability Exceptions ..................................................................................31016.1.14.6 Block Interrupt ...........................................................................................310

16.1.15DSM function ...........................................................................................................31016.1.15.1 Usability Exception ....................................................................................31016.1.15.2 Block interrupt............................................................................................310

16.2 Register Definitions ..............................................................................................................31116.2.1 DxCxxDRx Registers ...............................................................................................312

16.2.1.1 Timer Register Definitions .........................................................................31216.2.1.2 Counter Register Definitions......................................................................31316.2.1.3 Dead Band Register Definitions ................................................................31316.2.1.4 IPWM Register Definitions.........................................................................31416.2.1.5 CRCPRS Register Definitions ...................................................................31516.2.1.6 SPI Master Register Definitions.................................................................31516.2.1.7 SPI Slave Register Definitions...................................................................31616.2.1.8 Transmitter Register Definitions ................................................................31616.2.1.9 Receiver Register Definitions ....................................................................31616.2.1.10 DSM Register Definitions ..........................................................................317

16.2.2 DxCxxCR0 Register ..................................................................................................31816.2.3 DxCxxCR1 Register ..................................................................................................32116.2.4 INT_MSK1 Register ...............................................................................................32416.2.5 DxCxxFN Registers ..................................................................................................32516.2.6 DxCxxIN Registers ...................................................................................................32616.2.7 DxCxxOU Registers .................................................................................................326

16.3 Timing Diagrams ..................................................................................................................32816.3.1 Timer Timing ............................................................................................................32816.3.2 Counter Timing .........................................................................................................33116.3.3 Dead Band Timing ...................................................................................................331

16.3.3.1 Changing the PWM Duty Cycle .................................................................33216.3.3.2 Kill Operation .............................................................................................332

16.3.4 IPWM Timing.............................................................................................................33316.3.5 CRCPRS Timing ......................................................................................................33416.3.6 SPI Mode Timing ......................................................................................................33416.3.7 SPIM Timing .............................................................................................................33416.3.8 SPIS Timing .............................................................................................................33816.3.9 Transmitter Timing ...................................................................................................34016.3.10Receiver Timing .......................................................................................................34216.3.11DSM Timing .............................................................................................................344

Section E: Analog System 345Top-Level Analog Architecture .......................................................................................................345Interpreting the Analog Documentation ..........................................................................................345Application Description ...................................................................................................................346

Defining the Analog Blocks ...................................................................................................346Analog Functionality ..............................................................................................................346




Contents

Analog Register Summary .............................................................................................................347

17. Two Column Limited Analog System 34917.1 Architectural Description ......................................................................................................349

17.1.1 Analog Interface .......................................................................................................34917.1.1.1 Analog Comparator Bus Interface ............................................................35017.1.1.2 Analog Column Clock Generation ............................................................35017.1.1.3 Single Slope ADC .....................................................................................35017.1.1.4 PWM ADC Interface..................................................................................35217.1.1.5 Analog Modulator Interface (Mod Bits) .....................................................35217.1.1.6 Sample and Hold Feature .........................................................................352

17.1.2 Analog Array ............................................................................................................35317.1.2.1 NMux Connections ...................................................................................35317.1.2.2 PMux Connections ....................................................................................35417.1.2.3 Temperature Sensing Capability ..............................................................354

17.1.3 Analog Input Configuration ......................................................................................35417.1.4 Analog Reference ....................................................................................................35817.1.5 Continuous Time PSoC Block ..................................................................................35817.1.6 Switched Capacitor PSoC Block ..............................................................................359

17.1.6.1 Application Description for the SC Block...................................................35917.2 PSoC Device Distinctions.....................................................................................................35917.3 Register Definitions .............................................................................................................360

17.3.1 Summary Table for 2 Column Limited Analog System Registers ............................36017.3.2 Analog Interface Registers .......................................................................................36117.3.3 Analog Input Configuration Registers .......................................................................36617.3.4 Continuous Time PSoC Block Registers ..................................................................36717.3.5 Switched Capacitor PSoC Block Register ................................................................368

18. Two Column Analog Compare System 36918.1 Architectural Description ......................................................................................................369

18.1.1 Analog Interface .......................................................................................................36918.1.1.1 Analog Comparator Bus Interface ............................................................37018.1.1.2 Analog Column Clock Generation ............................................................371

18.1.2 Analog Array ............................................................................................................37118.1.2.1 NMux Connections ...................................................................................37218.1.2.2 PMux Connections ....................................................................................372

18.1.3 Analog Input Configuration ......................................................................................37318.1.4 Analog Reference ....................................................................................................37518.1.5 Continuous Time PSoC Block ..................................................................................37518.1.6 VDAC .......................................................................................................................376

18.2 PSoC Device Distinctions.....................................................................................................37618.3 Register Definitions .............................................................................................................377

18.3.1 Summary Table for Analog System Registers .........................................................37718.3.2 Analog Interface Registers .......................................................................................37818.3.3 Analog Input Configuration Registers .......................................................................38118.3.4 Continuous Time PSoC Block Registers ..................................................................38218.3.5 VDAC5 Block Register..............................................................................................383

Section F: System Resources 385Top-Level System Resources Architecture ....................................................................................385Interpreting the System Resources Documentation ......................................................................385System Resources Register Summary ..........................................................................................386




Contents

19. Digital Clocks 38919.1 Architectural Description.......................................................................................................389

19.1.1 Internal Main Oscillator ............................................................................................38919.1.2 Internal Low Speed Oscillator ..................................................................................38919.1.3 32.768 kHz Crystal Oscillator....................................................................................39119.1.4 External Clock ........................................................................................................391

19.1.4.1 Clock Doubler ............................................................................................39119.1.4.2 Switch Operation .......................................................................................391

19.2 PSoC Device Distinctions .....................................................................................................39219.3 Register Definitions ..............................................................................................................392

19.3.1 INT_CLR0 Register ..................................................................................................39319.3.2 INT_MSK0 Register .................................................................................................39319.3.3 OSC_GO_EN Register ............................................................................................39319.3.4 OSC_CR4 Register ..................................................................................................39419.3.5 OSC_CR3 Register ..................................................................................................39419.3.6 OSC_CR0 Register ................................................................................................39619.3.7 OSC_CR1 Register ..................................................................................................39719.3.8 OSC_CR2 Register ................................................................................................398

20. Multiply Accumulate (MAC) 39920.1 Architectural Description ......................................................................................................39920.2 Application Description .........................................................................................................400

20.2.1 Multiplication with No Accumulation .........................................................................40020.2.2 Accumulation After Multiplication ..............................................................................400

20.3 Register Definitions ..............................................................................................................40020.3.1 MULx_X Register .....................................................................................................40020.3.2 MULx_Y Register .....................................................................................................40120.3.3 MULx_DH Register ..................................................................................................40220.3.4 MULx_DL Register ...................................................................................................40220.3.5 MACx_X/ACCx_DR1 Register .................................................................................40220.3.6 MACx_Y/ACCx_DR0 Register .................................................................................40320.3.7 MACx_CL0/ACCx_DR3 Register .............................................................................40320.3.8 MACx_CL1/ACCx_DR2 Register .............................................................................403

21. I2C 40521.1 Architectural Description.......................................................................................................405

21.1.1 Basic I2C Data Transfer ............................................................................................40621.2 Application Description .........................................................................................................406

21.2.1 Slave Operation .......................................................................................................40621.2.2 Master Operation .....................................................................................................408

21.3 Register Definitions ..............................................................................................................40921.3.1 I2C_ADDR Register .................................................................................................40921.3.2 I2C_CFG Register ....................................................................................................41021.3.3 I2C_SCR Register ....................................................................................................41221.3.4 I2C_DR Register ......................................................................................................41421.3.5 I2C_MSCR Register .................................................................................................415

21.4 Timing Diagrams...................................................................................................................41721.4.1 Clock Generation ......................................................................................................41721.4.2 Basic Input/Output Timing.........................................................................................41721.4.3 Status Timing ............................................................................................................41821.4.4 Master Start Timing ...................................................................................................41921.4.5 Master Restart Timing ...............................................................................................421




Contents

21.4.6 Master Stop Timing ..................................................................................................42121.4.7 Master/Slave Stall Timing ........................................................................................42221.4.8 Master Lost Arbitration Timing .................................................................................42221.4.9 Master Clock Synchronization ..................................................................................423

22. Internal Voltage Reference 42522.1 Architectural Description.......................................................................................................42522.2 PSoC Device Distinctions.....................................................................................................42522.3 Register Definitions .............................................................................................................425

22.3.1 BDG_TR Register ....................................................................................................425

23. System Resets 42723.1 Architectural Description.......................................................................................................42723.2 Pin Behavior During Reset ...................................................................................................427

23.2.1 GPIO Behavior on Power Up....................................................................................42723.2.2 GPIO Behavior on External Reset ............................................................................428

23.3 Register Definitions .............................................................................................................42923.3.1 CPU_SCR1 Register ...............................................................................................42923.3.2 CPU_SCR0 Register ...............................................................................................430

23.4 Timing Diagrams .................................................................................................................43123.4.1 Power On Reset ......................................................................................................43123.4.2 External Reset .........................................................................................................43123.4.3 Watchdog Timer Reset ............................................................................................43123.4.4 Reset Details.............................................................................................................433

23.5 Power Consumption ............................................................................................................433

24. POR and LVD 43524.1 Architectural Description.......................................................................................................43524.2 PSoC Device Distinctions.....................................................................................................43524.3 Register Definitions .............................................................................................................435

24.3.1 VLT_CR Register .....................................................................................................43624.3.2 VLT_CMP Register ..................................................................................................437

25. IO Analog Multiplexer 43925.1 Architectural Description ......................................................................................................439

25.1.1 IOMUX and GPIO .....................................................................................................43925.1.2 Dual Channel 8-Bit IDAC ..........................................................................................440

25.2 PSoC Device Distinctions.....................................................................................................44025.3 Application Description .........................................................................................................441

25.3.1 Capacitive Sensing ..................................................................................................44125.3.2 Chip-Wide Analog Input ...........................................................................................44225.3.3 Crosspoint Switch ....................................................................................................44225.3.4 Charging Current ......................................................................................................442

25.4 Register Definitions .............................................................................................................44325.4.1 AMUX_CFG Register ..............................................................................................44325.4.2 IDACx_D Registers ..................................................................................................44325.4.3 AMUX_CFG1 Register ............................................................................................44425.4.4 MUX_CRx Registers ................................................................................................44425.4.5 IDAC_CR0 Register..................................................................................................44525.4.6 IDAC_CR1 Register .................................................................................................445




Contents

26. CSD Logic System 44726.1 Architectural Description.......................................................................................................447

26.1.1 System Bus Interface ................................................................................................44726.1.2 Local Data Bus DBDRV signal ..................................................................................44726.1.3 CSD Clocks Generation ............................................................................................44826.1.4 16-bit Timer/PRS Function........................................................................................448

26.1.4.1 Timer Function...........................................................................................44826.1.4.2 PRS Function ............................................................................................448

26.1.5 4-bit Multi-shot Function............................................................................................44826.1.6 16-bit Counter/Capture Function...............................................................................448

26.1.6.1 Counter mode............................................................................................44826.1.6.2 Capture mode............................................................................................448

26.1.7 Interrupt and Primary Output.....................................................................................44826.2 Application Description .........................................................................................................449

26.2.1 CSD Usage ...............................................................................................................44926.2.2 General Timer Usage................................................................................................450

26.3 Register Definitions...............................................................................................................45126.3.1 CSDx_DR0_L, CSDx_DR0_H ..................................................................................45126.3.2 CSDx_DR1_L, CSDx_DR1_H ..................................................................................45126.3.3 CSDx_CNT_L, CSDx_CNT_H ..................................................................................45126.3.4 CSDx_CR0................................................................................................................45226.3.5 CSDx_CR1................................................................................................................452

26.4 Clocking ................................................................................................................................45226.5 Reuse Information ................................................................................................................45226.6 Symbol/Representation ........................................................................................................45326.7 Block Pin Description............................................................................................................45326.8 Block Level Interfaces...........................................................................................................453

26.8.1 CSD Logic Register Space Assignment....................................................................45326.8.2 PRS related Block Level Interface Configuration ......................................................453

26.8.2.1 Seed[15:0] .................................................................................................45326.8.2.2 DR0_O[15:0] and DR0_I[15:0] ..................................................................45326.8.2.3 SEL[7:0] and MASK_I[7:0].........................................................................453

27. Real Time Clock (RTC) 45527.1 Architectural Description.......................................................................................................455

27.1.1 BCD Code Counter ...................................................................................................45527.1.2 User Data Writing......................................................................................................45527.1.3 RTC Data Reading....................................................................................................45527.1.4 General Timer ...........................................................................................................456

27.2 Register Definitions ..............................................................................................................45627.2.1 RTC_H ......................................................................................................................45627.2.2 RTC_M......................................................................................................................45627.2.3 RTC_S ......................................................................................................................45627.2.4 RTC_CR....................................................................................................................457

28. 10-Bit SAR ADC Controller 45928.1 Architectural Description.......................................................................................................459

28.1.1 System Bus Interface and Local Data Bus DBDRV signal........................................45928.1.2 ADC Clock Generation..............................................................................................45928.1.3 Voltage Doubler Clock Generation............................................................................46028.1.4 ADC FSM..................................................................................................................46028.1.5 SAR Algorithm and Data Process .............................................................................460




Contents

28.1.6 A-D-C Operation Mode ...............

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