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778 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 4, AUGUST 1979

[5]

[6]

[7]

[8]

Y. Cho, Calculation of the rise and fall times in the alloy junc-tion transistor switch based on the charge analysis, Proc. IRE,vol. 49, pp. 636-637, Mar. 1961.S. Krishna and P. L. Hewer, Second breakdown of transistorsduring inductive turn off, Proc. IEEE, vol. 61, pp. 393-395, Mar.1973.L. A. Hahn, The effect of collector resistance upon the highcurrent capability of n-p-v-n transistors, IEEE Trans. ElectronDevices, vol. ED-16, PP. 654-656, JUIY 1969.C. T. Kirk, A theory of transistor cutoff frequency (fT) fall offat high current densities, IRE Trans. Electron Devices, vol. ED-9,pp. 164-174, Mar. 1962.

A Two-Stage Weighted Capacitor Networkfor D/A-A/D Conversion

Y. S. YEE, L. M. TERMAN, AND L. G. HELLER

Abstract-A two-stage weighted capacitor network for A/D and D/Aconversion utilizing a feedback amplifier is descr ibed. The two-stageweighted capacitor DAC requires a smaJler range of capacitor valuesthan the conventional weighted capacitor DAC and is not subject tothe nonlinear effects of parasitic capacitance. Experimental results ofsuch a DAC implemented using a conventional n-channel metal-gateMOS process axe presented. A discussion of the comparative accuracyand area of one- and two-stage weighted capacitor DACS on the basisof capacitor t racking is given.

I. INTRODUCTIONThe use of a weighted capacitor network for A to D con-

version has been reported by McCreary and Gray [ 1 ]. Morerecently, the use of a two-stage weighted capacitor D to Aconverter (WCDAC) has been discussed by Yee [2] and Ohriand Callahan [31, [41. This paper describes the design andoperation of a two-stage WCDAC that is somewhat differentfrom that given by Ohri and Callahan, and also presents a dis-cussion of the comparative accuracy and area of one- and two-stage WCDAC networks.The circuit is shown in Fig. 1. It consists of two weighted

capacitor stages connected by a coupling capacitor CS. Ahigh-gain amplifier is connected in its inverting configurationwith the 2 C capacitor fed back from the output to the nega-tive input. Because of the negative feedback and high gain ofthe amplifier, the input node of the amplifier is a virtualground during a DAC operation, and the amplifier serves tointegrate charge injected onto the input node. Nonlinear ca-pacitor effects ate virtually eliminated since the input nodeof the amplifier is a virtual ground, and the common node ofthe second stage is fabricated on the metal side of the capac-it ors, eliminating nonlinear cliff usion capacitance on the node.The function of charge integration while the input node actsas a virtual ground potential can also be accomplished by con-necting the node to the source of a bucket brigade device.However, this allows only a single polarity output.

Manuscript received September 20, 1978; revised February 10, 1979.Y. S. Yee and L. M. Terman are with the IBM T. J. Watson ResearchCenter, Yorktown Heights, NY 10598.L. G. Heller was with the IBM T. J. Watson Research Center, York-town Heights, NY 10598. He is now with the IBM General TechnologyDivision, Essex Junction, VT 05452.

-hb hDIC/8 lC/4 lC/2W

c~QRMDINPUT NODE - 2C+ VxFig. 1. A two-stage weighted capacitor DAC. D indicates the dif-fused capacitor plate, and M indicates the metal capacitor plate.

In the circuit of Fig. 1 all capacitor values are an integralmultiple of the smallest capacitor. This permits fabricationof the larger capacitors by replication of the minimum capac-itor, which is advantageous to eliminate capacitor trackingerrors due to process biases [ 1]. The D to A conversion cycleis accomplished by initially resetting the 2C capacitor withSR and setting the input switches to Vre f. After SR is opened,the switches associated with input 1 s are switched to ground,and the amplifier integrates the charge coupled into the inputnode. Inputs 5-8 couple the correct charge to the input nodebecause it is a virtual ground.Offsets in the DAC system can be cancelled by adding suf-

ficient low-order bits to the DAC to achieve the desiredgranularity, determining the necessary input bit pattern tocancel the offset in a preconditioning cycle, and then addingthat input to subsequent conversions. The low-order bits maybe added by extending the range of the DAC with additionalcapacitors, or by a network connected in parallel to the in-put node of the amplifier. The preconditioning cycle can beperformed periodically to adaptively take into account changesdue to ambient or aging.

II. EXPERIMENTAL RESULTSAn 8-bit DAC with two four-capacitor stages was fabricatedand tested. An extra bit of dynamic range is achievable since

the DAC can provide both positive and negative outputssimply by initializing the digital input switches at either Vr ~or ground during the reset phase of a DAC operation.On the test chip metal-to-diffusion capacitors were used,

with the metal plates connected as indicated in Fig, 1 to re-duce nonlinear effects. More specifically, the series capacitorCs is fabricated with the diffused plate connected to the in-put node, and the metal plate of the 2C feedback capacitoris also connected to the input node. In the test circuit, SRis implemented with a simple MOS device switch, and adummy device is included for first-order cancellation of theturn- off transient coupled into the 2C capacitor. The ele-mental capacitor in the two-stage network consists of twosquare MO S capacitor structures with the diffused plates con-nected together on one side to form a rectangular capacitorelement. All other capacitors in the network are formed byrepeating this basic element. This layout approach is takento enhance accuracy by canceling edge etch bias effects andeffects due to unwanted thick oxide capacitance, as well asundesirable effects due to mask misalignment.Only the t we-stage weighted network was fabricated on the

test site. The amplifier and the switching arrangements wereprovided off-chip, although these could be put on-chip in

001 8-9200/79/0800-0778$00.75 @ 1979 IEEE

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0.5

Fig. 2. Photomicrograph of the two-stage weighted capacitor DAC testsite.

Fig. 3. DAC output. Full scale is 2 V.

practice [5], [6]. Although not included on this test site, theaddition of a metal border structure surrounding all the MOScapacitors to provide identical etching boundary conditionsfor each side of every capacitor should further enhance track-ing accuracy.

The test site was fabricated using a conventional metal-gaten-channel MOSFET process with 0.22 mil (5,5 pm) metallinewidths and 680 ~ thin oxide. Capacitor C has a value ofabout 16 PF. The silicon area occupied by the DAC networkis about 40 X 25 roils. A photomicrograph of the test site isshown in Fig. 2. The experimental waveform for cumulativeDAC output as progressively lower order bits are switched inis shown in Fig. 3. As indicated in Fig. 4 and Table I, experi-mental results showed that the DAC has a linearity better than8 bits, and an overall accuracy of approximately 8 bits (f~LSB). The accuracy was measured by sampling and holdingeach step and measuring the step sizes with an accurate digitalvoltmeter.

III. EFFECT OF CAPACITOR TRACKING ON ACCURACYIt is of interest to compare the potential accuracy and area

of the two-stage weighted capacitor DAC and the conventionalsingle-stage approach, both implemented using the feedbackamplifier, shown in Fig. 5. Nonlinear capacitance effects arevirtually eliminated with the pinning of the input node by theamplifier and appropriate e layout. The major remaining sourceof error is capacitor tracking, The two-stage WCDAC requiresa range of capacitor values smaller by 2n12 for n bits, Thismay, or may not, result in a significant area or accuracy im-provement, depending upon the sources of tracking errors,their distribution, variation with capacitor size, etc.

One limiting case occurs as tracking error between capacitorsapproaches zero; adequate DAC accuracy can be obtained us-ing equal minimum capacitors in both circuits, and the total

0,0

),,,/,,~,/.,/,,/,,/,

,/,,*,/,/ ,/,,/,,#_.,.,d,,*

0.0 0.1 0.2 0.3 0.4 0.5EXPECTED OUTPUT (V)(a)

779

.o,,~0.0 0.1 0.2 0.3 0,4 0.5LSB TO MSB(b)

Fig. 4. (a) 8-bit two-stage weighted capacitor DAC overall accuracy.(b) 8-bi t two-stage weighted capaci tor DAC bit-scan l inearity plot.

TABLE I8-BIT TWO-STAGEWEIGHTEDCAPACITORDAC OVERALL ACCURACYMeasured Expected Erroroutput output AV

(: (3 (mV)

1 (MSB) .5000 .5000 02 .2503 .2500 + .33 .1251 .1250 + .14 .0612 .0625 -1.35 .0305 .03125 - .76 .0153 ,0156 - .37 .0079 .0078 + .18 (LSB) .0044 .0039 + .5

Total (+) Error = 1.0 mV -1/4 LSBTotal ( -) Error = 2.3 mV ? 1 /2 LSB

capacitance required for the two-stage WCDAC will be smallerby approximately (~) 2/2. The area will be small by essen-tially the same ratio.

An alternate model is to assume that wafer dimensions havesome random variation AL which is independent of L and isnormally distributed (this will be called the constant ALmodel). The resulting variation in capacitor values will thenalso be normally distributed. Since larger capacitors are

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780 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 4, AUGUST 1979

(a)

J.2,2C _ ]2w ~pj,c ~p-,ccw-:--_~J---: -Zn/zc +(b)Fig. 5. (a) One-stage WCDAC. (b) Two-stage WCDAC.

made by replicating an elemental capacitor, any consistenterror (such as from process biases) will not affect accuracy;only random variations between capacitors will contribute,and for tracking considerations the mean of AL may betaken as zero. The effective standard deviation o of a sumof normally distributed elements is the square root of thesum of the squares of the standard deviations of the individualelements:

Let ACO be the standard deviation of the elemental capacitor.A capacitor made up of n elemental capacitors will have astandard deviation given by AC = fiA Co. It follows that

ACia& (2a)ACi 1T& (2b)

These expressions are valid whether a large capacitor is madeup of n smaller capacitors or is one capacitor with dimensionsW larger. For the single capacitor case, C m L, AC a 2LAL,and thus AC a @ as in (2a).For the single-stage WCDAC the standard deviation of thesmallest capacitor is A Co, that of the next is ~A Co, and soforth up to that of the largest capacitor WACO. Apply-ing (1), and normalizing the resulting output error voltageAt to the nominal maximum output signal VMAX,

-iF3TF3 a)2ni2 ACO(2n - 1) cowhere VMAX is the signal when all the input capacitors areswitched. The subscript I refers to the one-stage WCDAC;the subscript II used below refers to the two-stage WCDAC.In the first parenthetical expression under the radical sign,the 1 and 1/2n12 terms are the contributions of the high-order n/2 capacitors and the low-order n/2 capacitors, respec-tively. It is evident that the contribution of the low-ordergroup is minor for practical values of n.

Similarly, for the t we-stage WCDAC

ignoring, for simplicity, the error due to the coupling capacitorbetween stages. As before, the two terms in the first paren-thetical expression under the radical are the contributions dueto the high-order and low-order stages. Again the effect ofthe low- order capacitors is minor.

For the constant AL model, if a two-stage WCDAC is de-signed with a given accuracy, a one-stage WCDAC can be de-signed with the same size high- order capacitor which willhave essentially the same accuracy, but which will requireabout half the area (since area is proportional to the totalcapacitance in the network). This is quite plausible, as thehigher order capacitors dominate the error voltage A V, andif the n/2 low-order capacitors are disregarded, the two cir-cuits are identical, and thus will have the same error for thesame size capacitors. If the areas are made the same by re-ducing the size of the capacitors in the two-stage WCDAC bya factor of two, the error will increase by W, as seen from(2a).

Some limited data which we have obtained indicate thatAL decreases as L increases. A simple model is to take ALproportional to 1/L. This results in AC being constant, in-dependent of capacitor size, and ACi/Cj is proportional toI /Ci. Then, for the singIe-stage WCDAC -

AV1 -ii++)(+)

212 ACOVMAX 1 (2n - 1) co

as before, and for the two-stage WCDAC

.x.!! --%{w.V1MAX II (2n - 1) co

(4a)

(4b)

Thus,

for the same areas; increasing the elemental capacitor size inthe one-stage WCDAC to give the same accuracy, the area ratiobecomes

&zzn/4-lA 11

The advantage for the two-stage WCDAC in this model arisesfrom making the elemental capacitor as a single capacitor largerby 2n/2 than the elemental capacitor for the sin#e-stage case.

It is not clear which of the above models most closely approxi-matees reality. No data on capacitor tracking are available inthe literature, and in any case it could vary, depending uponthe individual facility and process used. Our measurementsof capacitor tracking were made on a small sample. However,because it requires a smaller range of capacitor values for agiven number of bits, the two-stage WCDAC may permitsmaller area or better accuracy than the singIe-stage WCDACin a practical manufacturing environment.

ACKNOWLEDGMENTThe authors would like to thank D. L. Critchlow for his en-

couragement and support. They would like to express theirAV

1A Co .

MAX II (2n - l)CO2-1 +2n- +.. . +2Wz)+~(2n-1 +2n-z +.. . + 242)

212 ACO. (2n - 1) co 2 (b)

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 4, AUGUST 1979 781

appreciation to H. Drake, who did the layout, E. Wurst andP. Evenrides, in whose facility the processing was done, andM. B. Pettigrew, who made many of the measurements.

Q ~CC

References[1]

[2]

[3][4][5]

[6]

J. L. McCreary and P. R. Gray, Ail -MOS charge redist ributionanalog-to-digital conversion techniquesPart I, IEEE J. Solid-State Circuits, vol. SC-10, pp. 371-379, Dec. 1975.Y. S. Yee, Two-stage weighted capaci tor circui t for analog-to-digi tal and digi tal- to-analog converters, U.S. Patent 4077035,Feb. 28, 1978.K. B. Ohri and M. J. Callahan, C-MOS codec splits transmit ting,receiving sections, Electronics, pp. 141-144, Sept. 28, 1978.

VI-1 L A r I r?

Integrated PCM codec, IEEE J. Solid-state (%cuits, VO1.SC-;4, pp. 38-46, Feb. 1979.Y. P. Tsividis, P. R. Gray, D. A. Hodges, and J. Chacko, Jr., Anall -MOS companded PCM voice encoder , in ZSSCCDig., vol. 1 !9,Feb. 1976, pp. 24-25.B. J. Hostica, R. W. Brodersen, and P. R. Gray, MOS sampled

I Trl 41--+ -4?.data recursive titers using switched capacitor integrators, IEEEJ. Solid-State Circuits, vol. SC-12, pp. 600-608, Dec. 1977,

I I u IRealization of an All-Pass Network with aNew Simple Circuit

YUJI SHIRAI, TAKAHIRO INOUE, AND FUMIO UENOI

l______ .___JIT.&.

Fig. 1. Alt-pass network circuit .AbstractThis correspondence shows the realization of the first-

order alI-pass network with a new simple circuit. This circuit can beintegrated and used at frequencies lessthan about 4 MHz.

VI

o

All-pass networks have been usually constructed by usingoperational amplifiers [11 - [41. We constructed the networkusing a new simple circuit. Fig. 1 shows an all-pass network.7rl and Tr2 which form a p-n-p-n structure constitute nega-tive impedance circuit. Tr2 is constructed by two matchedhigh a n-p-n transistors, as shown in Fig. 1, to provide a com-pound n-p-n transistor whose equivalent a is almost equal toO.5. Rgl and R.gz are bias resistors for the negative impedancecircuit. The cucuit formed by Tr3, Rbl, Rb2, and Re is avoltage- controlled current source in an ac operation and is aconstant current source in a dc operation. Fig. 2 shows itsac equivalent circuit. The voltage transfer function of thenetwork in Fig. 2 is

Rb=RblllRbzFig. 2. AC equivalent circuit of Fig. 1,

in the derivation of Fig. 2 are given byRp . (I1 +a~ 1 re ~+ ) RgI-a* Rgi-re2

(Rg + r~~ )2Cp .{(al +CY2 - l)(Rg+Pez)+(l -~2)7e2}Rgcc

(4)rezRgrd=iel + re2 i-Rg

(3)V2 a3 (Rp - RC - rd) -@CpRp(llC rd).VI Re 1 + juCp Rp (1)

When(5)c + rd =RP/2

and a3RP/2Re is set equal to H, then ( 1 ) can be written aswhere(2) R. RgtRg2g Rgl +Rg2Thus (2) is exhibiting the all-pass property of this network.

RP, Cp, and rd which are equivalent network elements defined al = common-base small-signal current gain of the p-n-ptransistor Trl,

% = equivalent common-base small-signal current gainof the compound n-p-n transistor Tr2,rel = emitter resistance of the p-n-p transistor Trl,re2 = equivalent emitter resistance of the compound n-p-n

t ransistor Tr2.

Maimw.ipt ,e.aived Novemba~ 1, 197g ; .evi..d Mach 12, 1979.Y. Shirai is with the Department of Information and Electronic

Engineering, Yatsushiro Technical College, Yatsushiro, 866, Japan.T. Inoue and F. Ueno are with the Department of Electronic Engi-

neering, Kumamoto University, Kumamoto, 860, Japan.0018-9200/79/0800-0781 $00.75 @ 1979 IEEE