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State Of The Art Software Defined

Radio Platforms By:

Omer Anjum

PhD student at Tampere University of Technology

Finland

Department of Computer Systems

Supervisor: Jari Nurmi

Trends in Digital Communication

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SDR may be defined as:

A piece of reusable hardware that can work with different

standards and protocols at different times to provide service

providers and users an effective solution in terms of

• Low Cost

• Low Power

• Reduced Area

• High Spectral Efficiency

• High Throughput

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Block Diagram

Software Defined Radio

Variable

Frequency

Oscillator

Local

Oscillator

(fixed)

Antenna

Bandpass

Filter

RF IF Baseband

ADC/DAC

DSP

Local

Oscillator

(fixed)

Antenna

RF IF Baseband

DSP ADC/DAC

Block Diagram

Software Defined Radio

Antenna

RF IF Baseband

DSP ADC/DAC

Block Diagram

Software Defined Radio

Overview of existing SDR solutions

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Processor Centered Architectures

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LeoCore by CoreSonic

• Basic philosophy is: • Identify the baseband processing operations on algorithmic level of abstraction

• Map them on suitable

processing cores

• Processors are categorized as: • Digital Front End

• SIMD processor

• Function accelerator

• Processor for control signals

and miscellaneous functions

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Sandblaster by SandBridge

• Sandblaster includes a combination of three units • Instruction fetch and branch unit

• Load/Store unit

• SIMD unit

• Sandblaster 1.0 targeted: • 3G standard

• Sandblaster 2.0 targeted: • 4G standard

• Vector registers connected

to 64-bit data path were extended

from 16-bit to 256-bit connected to

256-bit data path in version 2.0

• Mask and Accumulator registers

expanded from 4 and 40 bits to 32

and 64 bits

• SIMD can operate on 8 (integer) values in parallel in contrast to 4 values in

version 1.0

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ConnX BBE by Tensilica

• Different processor configurations according to the application

requirements are generated using tools like Xtensa Processor

Generator and Tensilica Instruction Extension.

• The configuration includes: • Choice of memory

system

• Optional instructions

• Custom instructions

• Xtensa C and C++

compiler can also

analyze the application

for vectorization

• Sixteen 18-bit

multiplications eight

20 bit additions or four 40 bit additions in parallel

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ConnX BBE by Tensilica

• 3-way VLIW instructions • First slot for Load/Store operation or Xtensa core instructions

• Second slot is for real and complex multiply, FFT or any vector operation

• Third slot uses the second Load/Store unit or is for arithmetic and logical

operations

• A wide range of instructions they have developed specializing the

domain of operations particularly for SDR

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EVP (Embedded Vector Processor) by

NXP

• Basic philosophy is to split SDR in three fundamental parts:

• Filter stage as configurable as

possible

• Modem stage most effected by

switching standards

• Codec stage demands high

processing and implemented in

ASIC accelerators

• VLIW parallelism is also provided

on top of vector parallelism

• Supported vector length is 256 bits

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Many Core SDR Platforms

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SODA (Signal-Processing On-demand

Architecture)

• Does not adopt multithreading approach

• Whole DSP kernel is pipelined and

statically assigned to one of the ultra-wide

SIMD SODA processing elements

• Idea is to avoid higher intra-kernel comm-

unication overhead

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Tomahawk MPSoC

• As many other solutions it also exploits instruction, data and

task level parallelism

• CoreManager might be

its distinct feature from

others

• The tasks are basically

converted to task descript-

ions at compile time

• Descriptions are continuously sent by the control unit to

CoreManager with maximum queue length of 16 tasks

• Spatial and temporal mapping of these tasks onto the PEs is

then done automatically by the CoreManager

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MuSIC by Infineon

• MuSIC is also powered by microprocessors, DSPs and

accelerators

• DSPs are SIMD Capable

• Each of the SIMD cores cluster consists of four Processing

Elements (PEs)

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RECONFIGURABLE

ARCHITECTURES FOR SDR

PLATFORMS

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Montium by Recore Systems

• Resembles more like an ASIC as it does not fetch the instructions

• 10 global buses to provide the interconnect flexibility which can

be changed in even every clock cycle

• ALU is multi-level and can be configured

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BUTTER and CREMA

• BUTTER is a coarse-grain reconfigurable array

• Consists of a parametric template

to gain any matrix size for PEs

• Meant to be used as a co-processor

with a GP core

• CREMA allows the adaptability of

each PE according to application needs

• Different algorithms like FFT and

WCDMA cell search have been imple-

mented

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ADRES by IMEC

• Hybrid CGA-SIMD processor design based on ADRES/DRESC

framework

• Architecture consists of:

• Global Control Unit

• 3 VLIW Functional

Units

• Coarse Grain Array (CGA)

module

• Machine is able

to switch on the fly at run time

between VLIW and CGRA

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Transport Triggered Architecture

• No particular instruction set architecture is defined for TTA

• Based ona single instruction called “MOVE”

• FU is triggered as soon as the data arrives

• A typical architecture consists of several number of buses,

functional units, register files and load store units

• More closely resembles to a VLIW architecture

• Scaling up TTA is much less complex because the functional

units and interconnection network are independent of each other.

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Transport Triggered Architecture

• TTA codesign environment (TCE) allows the TTA architecture to

be built and tested gradually according to the application needs

• Trade-off between flexibility and performance can easily be

translated by the programmer by making the right choices for the

required functional units, their granularity level, other supporting

units and the interconnection among the units

• Highly modular structure makes it easy to scale and add or delete

FUs

• Several algorithms like LTE (20MHz) channel estimation, 2k point

FFT have been tested on TTA meeting the real time constraints

and lower power consumption as compared to some other

architectures

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Heterogeneous SoC for SDR

• The basic idea is to develop a Heterogeneous SoC

• Different TTA nodes will be connected to the nodes of an NoC

• The central Node acts

as master for functions

other than DSP

• Shared memory space

is used for communicating

with each other

• The TTA nodes execute

different task for LTE

baseband processing like

• TURBO decoding, FFT, Carrier synchronization, Channel

estimation and equilization etc.

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TTA CGRA TTA

TTA COFFEE TTA

TTA CGRA TTA

Trends and Future Predictions

• Mostly the proposals from the industry remain anchored to the

DSP-based approach

• Approaches regarding reconfigurable architecture mostly came

from academia

• For some time systems still likely to follow this paradigm

• A programmable microprocessor acts as a system controller and is

connected via a multilayer hierarchical bus to a series of

subsystems hosting either ASIC components, ASIPs or VLIW DSP

processors with SIMD capabilities

• In the near future, it is likely that we will witness an evolution

of this paradigm consisting of adopting NoCs to interconnect

an increasing number of subsystems

• In order to facilitate programming such huge systems probably

industry needs to put more efforts in developing the tools and

environments and may follow some standards to make the portability

among different platforms feasible.

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Reference:

Omer Anjum et. al; “State of the art baseband DSP platforms for

Software Defined Radio: A survey”; EURASIP Journal on

Wireless Communications and Networking, Volume 2011, Issue 1

Link: http://jwcn.eurasipjournals.com/content/2011/1/5

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Thank You

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