StaticRoute: A novel router for the dynamic partial

reconfiguration of FPGAsBrahim Al Farisi,

Karel Bruneel, Dirk Stroobandt

Overview

2

• Dynamic reconfiguration of FPGAs:• Modular dynamic reconfiguration (MDR)• Dynamic circuit specialization (DCS)

• Novel tool flow• Experiments and results• Conclusions

FPGA

3

FFLUT

0

1

1

0

1

0

0

1

01 0

0 0

10

1 0

0 1

00

0

0

0

1

0

1

1

1

0

Conventional FPGA tool flow

4

• Input: textual description of functionality

SYNTHESIS

MAP

PLACE

HDL design

Configuration

ROUTE

entity multiplexer isport( sel : in std_logic_vector(1 downto 0); in : in std_logic_vector(3 downto 0); out : out std_logic);end multiplexer;

architecture behavior of multiplexer isbegin out <= in(conv_integer(sel));end behavior;

Textual description: HDL design

5

in0

in1

in2

in3

sel0

sel1

out

Conventional FPGA tool flow

6

SYNTHESIS

MAP

• Input: Textual description of functionality• Output: FPGA configuration

PLACE

HDL design

Configuration

ROUTE

100101011100001111

Dynamic reconfiguration of FPGAs

7

• Advantages:• Smaller area• Lower power usage

M1 M2 M3

• Goal: area reduction with reduced reconfiguration time

M1M2M3

• Disadvantage:• Reconfiguration

time

Dynamic reconfiguration of FPGAs

8

M1 M2 M3

• 2 tool flows:• Modular Dynamic Reconfiguration (MDR)• Dynamic Circuit Specialization (DCS)

M1M2M3

Modular Dynamic Reconfiguration (MDR)

9

Mode 1

SYNTHESIS

MAP

PLACE

Configuration 1

ROUTE

Mode 2

SYNTHESIS

MAP

PLACE

Configuration 2

ROUTE

MDR

• Different modes are implemented independently• Complete area is rewritten Results in long reconfiguration times

10

Dynamic Circuit specialization

• Design with parameters: input signals that only change once a while

• Implement dependency on parameters using dynamic reconfiguration

11

Dynamic circuit specialization

12

• Input: annotated textual description of functionality

SYNTHESIS

Param. HDL

TMAP

TPLACE

Param. Conf.

TROUTE

entity multiplexer isport( --BEGIN PARAM sel : in std_logic_vector(1 downto 0); --END PARAM in : in std_logic_vector(3 downto 0); out : out std_logic);end multiplexer;

architecture behavior of multiplexer isbegin out <= in(conv_integer(sel));end behavior;

Parameterised HDL design

13

in0

in1

in2

in3

sel0

sel1

out

Dynamic circuit specialization

14

SYNTHESIS

• Input: Annotated textual description of functionalityParam. HDL

TMAP

TPLACE

Param. Conf.

TROUTE

Dynamic circuit specialization

15

• Input: Annotated textual description of functionality

• Output: Parameterised configurationParam. HDL

SYNTHESIS

TMAP

TPLACE

Param. Conf.

TROUTE

1A01010111B00C1111

A = sel0 AND sel1

B = sel1 C = sel0 OR sel1

TRoute

16

Dynamic Circuit Specialization

• Reduced reconfiguration time• Takes as input 1 parameterised design• How to implement several modes with DCS?

17

Goal of our research

• Develop tool flow for dynamic reconfiguration of multi-mode circuits

• Reduce reconfiguration time • Combined routing of different modes using TRoute:

Increase correlation between configurations of the different modes

18

Novel tool flow

19

Mode 1

SYNTHESIS

MAP

Mode 2

SYNTHESIS

MAP

Param. Conf.

TROUTE

Merge

PLACE

Configuration 1

ROUTE

PLACE

Configuration 2

ROUTE

Experiments

21

• Regular expression matching hardware and general MCNC benchmarks

• Circuits of 200-400 LBs• 2 to 5 modes considered• Comparison of MDR and DCS (this work)• Metrics:• Reconfiguration time• Wire length (of each mode separately)

Results – Reconfiguration time

22

• Speed-up of routing reconfiguration time • Speed-up of total reconfiguration time

Results – Reconfiguration time routing (MDR)

23

Results – Total reconfiguration time (MDR)

25

Results – Wire length

28

Conclusions

27

• Using novel tool flow that uses TRoute:• Total reconfiguration speed-up of 3X to 5X• Increase in wire length between 10 to 25 percent

A novel tool flow for increased routing configuration similarity in

multi-mode circuitsBrahim Al Farisi,

Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt