Date post: | 02-Jun-2018 |
Category: |
Documents |
Upload: | casyan-knss |
View: | 235 times |
Download: | 0 times |
of 27
8/10/2019 statii radio fm
1/27
8/10/2019 statii radio fm
2/27
Library of Congress Cataloging-in-Publication Data
The VLSI handbook / edited by Wai-Kai Chen.
p. cm.
Includes bibliographical references and index.
ISBN 0-8493-8593-8 (alk. paper)
1. Integrated circuits--Very large scale integration. I. Chen,Wai-Kai, 1936
TK7874.75.V573 1999
621.395dc21 99-047682
CIP
This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with
permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish
reliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materials
or for the consequences of their use.
Neither this book nor any part may be reproduced or transmitted in any form or by any means, electronic or mechanical,
including photocopying, microfilming, and recording, or by any information storage or retrieval system, without prior
permission in writing from the publisher.
All rights reserved. Authorization to photocopy items for internal or personal use, or the personal or internal use of
specific clients, may be granted by CRC Press LLC, provided that $.50 per page photocopied is paid directly to Copyright
Clearance Center, 222 Rosewood Drive, Danvers, MA 01923 USA. The fee code for users of the Transactional Reporting
Service is ISBN 0-8493-8593-8/00/$0.00+$.50. The fee is subject to change without notice. For organizations that havebeen granted a photocopy license by the CCC, a separate system of payment has been arranged.
The consent of CRC Press LLC does not extend to copying for general distribution, for promotion, for creating new
works, or for resale. Specific permission must be obtained in writing from CRC Press LLC for such copying.
Direct all inquiries to CRC Press LLC, 2000 Corporate Blvd., N.W., Boca Raton, Florida 33431.
Trademark Notice:Product or corporate names may be trademarks or registered trademarks, and are used only for
identification and explanation, without intent to infringe.
2000 by CRC Press LLC
No claim to original U.S. Government works
International Standard Book Number 0-8493-8593-8
Library of Congress Card Number 99-047682Printed in the United States of America 1 2 3 4 5 6 7 8 9 0
Printed on acid-free paper
8/10/2019 statii radio fm
3/27
2000 by CRC Press LLC
Preface
Purpose
The purpose of The VLSI Handbook is to provide in a single volume a comprehensive reference workcovering the broad spectrum of VLSI technology. It is written and developed for the practicing electrical
and computer engineers in industry, government, and academia. The goal is to provide the most up-
to-date information in IC technology, devices and their models, circuit simulations, amplifiers, logic
design, memory, registers and system timing, microprocessor and ASIC, test and testability, design
automation, and design languages. The handbook is not an all-encompassing digest of everything taught
within an electrical and computer engineering curriculum on VLSI technology. Rather, it is the engineer's
first choice in looking for a solution. Therefore, full references to other sources of contributions are
provided. The ideal reader is a B.S.-level engineer with a need for a one-source reference to keep abreast
of new techniques and procedures as well as review standard practices.
Background
The handbook stresses fundamental theory behind professional applications. In order to do so, it is
reinforced with frequent examples. Extensive development of theory and details of proofs have been
omitted. The reader is assumed to have a certain degree of sophistication and experience. However, brief
reviews of theories, principles and mathematics of some subject areas are given. These reviews have been
done concisely with perception. The handbook is not a textbook replacement, but rather a reinforcement
and reminder of material learned as a student. Therefore, important advancement and traditional as well
as innovative practices are included.
Since the majority of professional electrical engineers graduated before powerful personal computers
were widely available, many computational and design methods may be new to them. Therefore,computers and software use are thoroughly covered. Not only does the handbook use traditional refer-
ences to cite sources for the contributions, it also contains all relevantsources of information and toolsthat would assist the engineer in performing his/her job. This may include sources of software, databases,
standards, seminars, conferences, etc.
Organization
Over the years, the fundamentals of VLSI technology have evolved to include a wide range of topics and
a broad range of practice. To encompass such a wide range of knowledge, the handbook focuses on the
key concepts, models, and equations that enable the electrical or computer engineer to analyze, design
and predict the behavior of very large-scale integrated circuits. While design formulas and tables arelisted, emphasis is placed on the key concepts and theories underlying the applications.
8/10/2019 statii radio fm
4/27
2000 by CRC Press LLC
The information is organized into 13 major sections, which encompass the field of VLSI technology.
Each section is divided into chapters, each of which was written by a leading expert in the field to enlighten
and refresh knowledge of the mature engineer, and to educate the novice. Each chapter contains intro-
ductory material, leading to the appropriate applications, and references. The referencesprovide a list ofuseful books and articles for following reading.
Locating Your Topic
Numerous avenues of access to information contained in the handbook are provided. A complete table
of contents is presented at the front of the book. In addition, an individual table of contents precedes
each of the thirteen sections. Finally, each chapter begins with its own table of contents. The reader isurged to look over these tables of contents to become familiar with the structure, organization, and
content of the book. For example, see Section VIII: Microprocessor and ASIC, then Chapter 61: Micro-
processor Design Verification, and then Section 61.8: Emulation. This tree-like structure enables the
reader to move up the tree to locate information on the topic of interest.
A combined subject and author index has been compiled to provide means of accessing information.
It can also be used to locate definitions; the page on which the definition appears for each key defining
term is given in this index.
The VLSI Handbookis designed to provide answers to most inquiries and direct inquirers to furthersources and references. We trust that it will meet your needs.
Acknowledgments
The compilation of this book would not have been possible without the dedication and efforts of the
Editorial Board of Advisors, the section editors, the publishers, and most of all the contributing authors.
I wish to thank them all and also my wife, Shiao-Ling, for her patience and understanding.
Wai-Kai ChenEditor-in-Chief
8/10/2019 statii radio fm
5/27
2000 by CRC Press LLC
Editor-in-Chief
Wai-Kai Chen, Professor and Head of the Department of Electrical
Engineering and Computer Science at the University of Illinois at
Chicago, teaches graduate and undergraduate courses in electrical
engineering in the fields of circuits and systems. He received his B.S.
and M.S. in electrical engineering at Ohio University where he was
later recognized as a Distinguished Professor. He earned his Ph.D.
in electrical engineering at the University of Illinois at Urbana-
Champaign.
Professor Chen has extensive experience in education and industry
and is very active professionally in the fields of circuits and systems.
He has served as a visiting professor at Purdue University and the
University of Hawaii at Manoa. He was Editor of the IEEE Transac-
tions on Circuits and Systems, both Series I and IIand President ofthe IEEE Circuits and Systems Society. Currently, he is Editor-in-
Chief of the Journal of Circuits, Systems and Computersand EditoroftheAdvanced Series in Electrical and Computer Engineering, Imperial College Press. He received theLester R. Ford Awardfrom the Mathematical Association of America, the Alexander von Humboldt Awardfrom Germany, the Ohio University Alumni Medal of Merit for Distinguished Achievement in EngineeringEducation, the Senior University Scholar Awardfrom University of Illinois at Chicago, the DistinguishedAlumnus Awardfrom the University Illinois at Urbana-Champaign, and theSociety Meritorious ServiceAwardand theEducation Awardfrom IEEE Circuits and Systems Society. He also received more than adozen honorary professor awards from major institutions in China.
A Fellow of the Institute of Electrical and Electronics Engineers and the American Association for the
Advancement of Science, Professor Chen is widely known in the profession for his Applied Graph Theory(North-Holland), Theory and Design of Broadband Matching Networks(Pergamon Press), Active Networkand Feedback Amplifier Theory(McGraw-Hill), Linear Networks and Systems(Brooks/Cole), Passive andActive Filters: Theory and Implementations(John Wiley), Theory of Nets(John Wiley), and The Circuitsand Filters Handbook(Editor-in-Chief, CRC Press).
8/10/2019 statii radio fm
6/27
2000 by CRC Press LLC
Advisory Board
Professor Steve M. KangDepartment of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
Urbana, Illinois
Professor Saburo MurogaComputer Science Department
University of Illinois at Urbana-Champaign
Urbana, Illinois
Dr. Bing J. SheuAvant! Corporation
Fremont, California
8/10/2019 statii radio fm
7/27
2000 by CRC Press LLC
Contributors
Ramachandra AcharCarleton University
Ottawa, Ontario, Canada
James H. AylorUniversity of Virginia
Charlottesville, Virginia
R. Jakob BakerUniversity of Idaho
Boise, Idaho
David L. BartonIntermetrics, Inc.Vienna, Virginia
Andrea BaschirottoUniversit di Pavia
Pavia, Italy
Charles R. BaughC. R. Baugh and Associates
Bellevue, Washington
J. BhaskerCadence Design Systems
Allentown, Pennsylvania
David BlaauwMotorola, Inc.
Austin, Texas
Marc BorremansKatholieke Universiteit Leuven
Leuven-Heverlee, Belgium
Victor BoyadzhyanJet Propulsion Laboratory
Pasadena, California
Charles E. ChangConexant Systems, Inc.
Newbury Park, California
Wai-Kai ChenUniversity of Illinois
Chicago, Illinois
Kuo-Hsing ChengTamkang UniversityTamsui, Taipei Hsien, Taiwan
John Choma, Jr.University of Southern
California
Los Angeles, California
Amy Hsiu-Fen ChouNational Tsing-Hua University
Hsin-Chu, Taiwan
Moon Jung ChungMichigan State University
East Lansing, Michigan
David J. ComerBrigham Young University
Provo, Utah
Donald T. ComerBrigham Young UniversityProvo, Utah
Daniel A. ConnorsUniversity of Illinois
Urbana, Illinois
Donald CottrellSilicon Integration Initiative,
Inc. (Si2, Inc.)
Austin, Texas
John D. CresslerAuburn University
Auburn, Alabama
Sorin CristoloveanuInstitut National Polytechnique
de Grenoble
Grenoble, France
Bram De MuerKatholieke Universiteit Leaven
Leuven-Heverlee, Belgium
Geert A. De VeirmanSilicon Systems, Inc.
Tustin, California
Maria del MarHershenson
Stanford University
Stanford, California
Allen M. DeweyDuke University
Durham, North Carolina
8/10/2019 statii radio fm
8/27
2000 by CRC Press LLC
Abhijit DharchoudhuryMotorola, Inc.
Austin, Texas
Donald B. EstreichHewlett-Parkard Company
Santa Rosa, California
John W. FattarusoTexas Instruments,
Incorporated
Dallas, Texas
Eby G. FriedmanUniversity of Rochester
Rochester, New York
Thad GabaraLucent Technologies
Murray Hill, New Jersey
Stantanu GangulyIntel Corp.
Austin, Texas
Yosef GavrielVirginia Polytechnic Institute
and State University
Blacksburg, Virginia
Jan V. GrahnRoyal Institute of Technology
Kista-Stockholm, Sweden
Rajesh K. GuptaUniversity of California
Irvine, California
Sumit GuptaUniversity of California
Irvine, California
Peter J. HeskethThe Georgia Institute
of Technology
Atlanta, Georgia
Karl HessUniversity of Illinois
Urbana, Illinois
Charles Ching-HsiangHsu
National Tsing-Hua University
Hsinchu, Taiwan
Jen-Sheng HwangNational Science Council
Hsinchu, Taiwan
Wen-mei HwuUniversity of Illinois
Urbana, Illinois
Kazumi InohToshiba Corporation
Isogo-ku, Yokohama, Japan
Hidemi IshiuchiToshiba Corporation
Isogo-ku, Yokohama, Japan
Mohammed IsmailThe Ohio State UniversityColumbus, Ohio
Hiroshi IwaiToshiba Corporation
Isogo-ku, Yokohama, Japan
Vikram IyengarUniversity of Illinois
Urbana, Illinois
Johan JanssensKatholieke Universiteit Leuven
Leuven-Heverlee, Belgium
Dimitri KagarisSouthern Illinois University
Carbondale, Illinois
Steve M. KangUniversity of Illinois
Urbana, Illinois
Nick KanopoulosAtmel, Multimedia and
CommunicationsMorrisville, North Carolina
Tanay KarnikIntel Corporation
Hillsboro, Oregon
Yasuhiro KatsumataToshiba Corporation
Isogo-ku, Yokohama, Japan
Pankaj KhandelwalUniversity of Illinois
Chicago, Illinois
John M. KhouryLucent Technologies
Murray Hill, New Jersey
Heechul KimHankuk University of Foreign
StudiesYongin, Kyung Ki-Do, Korea
Hideki KimijimaToshiba Corporation
Isogo-ku, Yokohama, Japan
Isik C. KizilyalliLucent Bell Laboratories
Orlando, Florida
8/10/2019 statii radio fm
9/27
2000 by CRC Press LLC
Robert H. KlenkeVirginia Commonwealth
University
Richmond, Virginia
Ivan S. KourtevUniversity of Pittsburgh
Pittsburgh, Pennsylvania
Thomas H. LeeStanford UniversityStanford, California
Harry W. LiUniversity of Idaho
Moscow, Idaho
Chi-Hung LinThe Ohio State University
Columbus, Ohio
Frank Ruei-Ling LinNational Tsing-Hua University
Hsin-Chu, Taiwan
John W. LockwoodWashington University
St. Louis, Missouri
Stephen I. LongUniversity of California
Santa Barbara, California
Flavio LorenzelliST Microelectronics, Inc.
San Diego, California
Ashraf LotfiLucent Technologies
Murray Hill, New Jersey
Joseph W. LydingUniversity of IllinoisUrbana, Illinois
Martin MargalaUniversity of Alberta
Edmonton, Alberta, Canada
Samuel S. MartinLucent Technologies
Murray Hill, New Jersey
Erik A. McShaneUniversity of Illinois
Chicago, Illinois
Shin-ichi MinatoNTT Network Innovation
Laboratories
Yokosuka-shi, Japan
Sunderarajan S. MohanStanford University
Stanford, California
Hisayo S. MomoseToshiba Corporation
Isogo-ku, Yokohama, Japan
Eiji MorifujiToshiba Corporation
Isogo-ku, Yokohama, Japan
Toyota MorimotoToshiba Corporation
Isogo-ku, Yokohama, Japan
Saburo MurogaUniversity of Illinois
Urbana, Illinois
Akio NakagawaToshiba Corporation
Saiwai-ku, Kawasaki, Japan
Yuichi NakamuraNEC CorporationMiyamae-ku, Kawasaki, Japan
Michel S. NakhlaCarleton University
Ottawa, Ontario, Canada
Zainalabedin NavabiNortheastern University
Boston, Massachusetts
Philip G. NeudeckNASA Glenn Research Center
Cleveland, Ohio
Kwok NgLucent Technologies
Murray Hill, New Jersey
Hideaki NiiToshiba Corporation
Isogo-ku, Yokohama, Japan
Tatsuya OhguroToshiba CorporationIsogo-ku, Yokohama, Japan
Mikael stlingRoyal Institute of Technology
Kista-Stockholm, Sweden
Alice C. ParkerUniversity of Southern
California
Los Angeles, California
Alison PayneImperial College
University of London
London, England
Massoud PedramUniversity of Southern
California
Los Angeles, California
8/10/2019 statii radio fm
10/27
2000 by CRC Press LLC
J. Gregory RollinsAntrim Design Systems
Scotts Valley, California
Elizabeth M. RudnickUniversity of Illinois
Urbana, Illinois
Kirad SamavatiStanford University
Stanford, California
Rolf SchaumannPortland State University
Portland, Oregon
Rick Shih-Jye ShenNational Tsing-Hua University
Hsinchu, Taiwan
Krishna ShenaiUniversity of IllinoisChicago, Illinois
Bing J. SheuAvant! Corporation
Los Angeles, California
Bang-Sup SongUniversity of California
La Jolla, California
Michiel SteyaertKatholieke Universiteit Leuven
Leuven-Heverlee, Belgium
Haruyuki TagoToshiba Semiconductor
Company
Saiwai-ku, Kawasaki-shi, Japan
Naofumi TakagiNagoya University
Nagoya, Japan
Donald C. ThelenAnalog Interfaces
Bozeman, Montana
Chris ToumazouImperial College
University of LondonLondon, England
Spyros TragoudasSouthern Illinois University
Carbondale, Illinois
Yuh-Kuang TsengIndustrial Research and
Technology Institute
Chutung, Hsinchu, Taiwan
Meera VenkataramanTroika Networks, Inc.
Calabasas Hills, California
Suhrid A. WadekarIBM Corp.
Hopewell Junction, New York
Chorng-kuang WangNational Taiwan UniversityTaipei, Taiwan
R. F. WassenaarUniversity of Twente
Enschede, The Netherlands
Louis A. Williams IIITexas Instruments,
Incorporated
Dallas, Texas
Wayne WolfPrinceton University
Princeton, New Jersey
Chung-Yu WuNational Chiao Tung University
Hsinchu, Taiwan
Evans Ching-Song YangNational Tsing-Hua University
Hsinchu, Taiwan
Kazuo YanoHitachi Ltd.
Kokubunji, Tokyo, Japan
Kung YaoUniversity of California
Los Angeles, California
Ko YoshikawaNEC CorporationFuchu, Tokyo, Japan
Kuniyoshi YoshikawaToshiba Corporation
Isogo-ku, Yokohama, Japan
Takashi YoshitomiToshiba Corporation
Isogo-ku, Yokohama, Japan
Min-shueh YuanNational Taiwan University
Taipei, Taiwan
C. Patrick YueStanford University
Stanford, California
8/10/2019 statii radio fm
11/27
2000 by CRC Press LLC
Contents
SECTION I VLSI Technology
1 VLSI Technology: A System Perspective Krishna ShenaiandErik A. McShane1.1 Introduction
1.2 Contemporary VLSI Systems
1.3 Emerging VLSI Systems
1.4 Alternative Technologies
2 CMOS/BiCMOS Technology Yasuhiro Katsumata, Tatsuya Ohguro, KazumiInoh, Eiji Morifuji, Takashi Yoshitomi, Hideki Kimijima, Hideaki Nii, Toyota
Morimoto, Hisayo S. Momose, Kuniyoshi Yoshikawa, Hidemi Ishiuchi, andHiroshi Iwai2.1 Introduction
2.2 CMOS Technology
2.3 BiCMOS Technology
2.4 Future Technology
2.5 Summary
3 Bipolar Technology Jan V. Grahnand Mikael stling3.1 Introduction
3.2 Bipolar Process Design
3.3 Conventional Bipolar Technology3.4 High-Performance Bipolar Technology
3.5 Advanced Bipolar Technology
4 Silicon on Insulator Technology Sorin Cristoloveanu4.1 Introduction
4.2 Fabrication of SOI Wafers
4.3 Generic Advantages of SOI
4.4 SOI Devices
4.5 FullyDepleted SOI Transistors
4.6 Partially Depleted SOI Transistors
4.7 ShortChannel Effects4.8 SOI Challenges
4.9 Conclusion
http://s1.pdf/http://chp01.pdf/http://chp01.pdf/http://chp01.pdf/http://chp01.pdf/http://chp01.pdf/http://chp01.pdf/http://chp02.pdf/http://chp02.pdf/http://chp02.pdf/http://chp02.pdf/http://chp02.pdf/http://chp02.pdf/http://chp02.pdf/http://chp03.pdf/http://chp03.pdf/http://chp03.pdf/http://chp03.pdf/http://chp03.pdf/http://chp03.pdf/http://chp03.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp04.pdf/http://chp03.pdf/http://chp03.pdf/http://chp03.pdf/http://chp03.pdf/http://chp03.pdf/http://chp03.pdf/http://chp02.pdf/http://chp02.pdf/http://chp02.pdf/http://chp02.pdf/http://chp02.pdf/http://chp02.pdf/http://chp01.pdf/http://chp01.pdf/http://chp01.pdf/http://chp01.pdf/http://chp01.pdf/http://s1.pdf/8/10/2019 statii radio fm
12/27
2000 by CRC Press LLC
5 SiGe Technology John D. Cressler5.1 Introduction
5.2 SiGe Strained Layer Epitaxy
5.3 The SiGe Heterojunction Bipolar Transistor (HBT)
5.4 The SiGe Heterojunction Field Effect Transistor (HFET)
5.5 Future Directions
6 SiC Technology Philip G. Neudeck6.1 Introduction
6.2 Fundamental SiC Material Properties
6.3 Applications and Benefits of SiC Electronics6.4 SiC Semiconductor Crystal Growth
6.5 SiC Device Fundamentals
6.6 SiC Electronic Devices and Circuits
6.7 Further Recommended Reading
7 Passive Components Ashraf Lotfi7.1 Magnetic Components
7.2 Air Core Inductors
7.3 Resistors
7.4 Capacitors
8 Power IC Technologies Akio Nakagawa8.1 Introduction
8.2 Intelligent Power ICs
8.3 High-Voltage Technology
8.4 High-Voltage Metal Interconnection
8.5 High-Voltage SOI Technology
8.6 High-Voltage Output Devices
8.7 Sense and Protection Circuit
8.8 Examples of High-Voltage SOI Power ICs with LIGBT Outputs
8.9 SOI Power ICs for System Integration
8.10 High-Temperature Operation of SOI Power ICs
9 Noise in VLSI Technologies Samuel S. Martin, Thad Gabara,and Kwok Ng9.1 Introduction
9.2 Microscopic Noise
9.3 Device Noise
9.4 Chip Noise
9.5 Future Trends
9.6 Conclusions
10 Micromachining Peter J. Hesketh10.1 Introduction
10.2 Micromachining Processes
http://chp05.pdf/http://chp05.pdf/http://chp05.pdf/http://chp05.pdf/http://chp05.pdf/http://chp05.pdf/http://chp05.pdf/http://chp06.pdf/http://chp06.pdf/http://crcfsn01/MAC38_1/PRODUCTION/WB004/8593/pdf/chp06.pdfhttp://chp06.pdf/http://chp06.pdf/http://chp06.pdf/http://chp06.pdf/http://chp06.pdf/http://chp06.pdf/http://chp07.pdf/http://chp07.pdf/http://chp07.pdf/http://chp07.pdf/http://chp07.pdf/http://chp07.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp09.pdf/http://chp09.pdf/http://chp09.pdf/http://chp09.pdf/http://chp09.pdf/http://chp09.pdf/http://chp09.pdf/http://chp09.pdf/http://chp10a.pdf/http://chp10a.pdf/http://chp10a.pdf/http://chp10a.pdf/http://chp10a.pdf/http://chp10a.pdf/http://chp10a.pdf/http://chp09.pdf/http://chp09.pdf/http://chp09.pdf/http://chp09.pdf/http://chp09.pdf/http://chp09.pdf/http://chp09.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp08.pdf/http://chp07.pdf/http://chp07.pdf/http://chp07.pdf/http://chp07.pdf/http://chp07.pdf/http://chp06.pdf/http://chp06.pdf/http://chp06.pdf/http://chp06.pdf/http://chp06.pdf/http://chp06.pdf/http://crcfsn01/MAC38_1/PRODUCTION/WB004/8593/pdf/chp06.pdfhttp://chp06.pdf/http://chp05.pdf/http://chp05.pdf/http://chp05.pdf/http://chp05.pdf/http://chp05.pdf/http://chp05.pdf/8/10/2019 statii radio fm
13/27
2000 by CRC Press LLC
10.3 Bulk Micromachining of Silicon
10.4 Surface Micromachining
10.5 Advanced Processing
10.6 CMOS and MEMS Fabrication Process Integration
10.7 Wafer Bonding
10.8 Optical MEMS
10.9 Actuators for MEMS Optics
10.10 Electronics
10.11 Chemical Sensors
11 Microelectronics Packaging Pankaj Khandelwaland Krishna Shenai11.1 Introduction
11.2 Packaging Hierarchy
11.3 Package Parameters
11.4 Packaging Substrates
11.5 Package Types
11.6 Hermetic Packages
11.7 Die Attachment Techniques
11.8 Package Parasitics
11.9 Package Modeling
11.10 Packaging in Wireless Applications11.11 Future Trends
12 Multichip Module Technologies Victor Boyadzhyanand John Choma, Jr.12.1 Introduction
12.2 Multi-Chip Module Technologies
12.3 Materials for HTCC Aluminum Packages
12.4 LTCC Substrates
12.5 Aluminum Nitride
12.6 Materials for Multi-layered AlN Packages
12.7 Thin Film Dielectrics
12.8 Carrier Substrates
12.9 Conductor Metallization
12.10 Choosing Substrate Technologies and Assembly Techniques
12.11 Assembly Techniques
12.12 Summary
13 Channel Hot ElectronDegradation-Delay in MOS Transistors Dueto Deuterium Anneal Isik C. Kizilyalli, Karl Hess, and Joseph W. Lyding13.1 Introduction
13.2 Post-Metal Forming Gas Anneals in Integrated Circuits
13.3 Impact of Hot Electron Effects on CMOS Development13.4 The Hydrogen/Deuterium Isotope Effect and CMOS Manufacturing
13.5 Summary
http://chp10a.pdf/http://chp10a.pdf/http://chp10a.pdf/http://chp10a.pdf/http://chp10a.pdf/http://chp10a.pdf/http://chp10b.pdf/http://chp10b.pdf/http://chp10b.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp13.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp12.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp11.pdf/http://chp10b.pdf/http://chp10b.pdf/http://chp10b.pdf/http://chp10a.pdf/http://chp10a.pdf/http://chp10a.pdf/http://chp10a.pdf/http://chp10a.pdf/http://chp10a.pdf/8/10/2019 statii radio fm
14/27
2000 by CRC Press LLC
SECTION II Devices and Their Models
14 Bipolar Junction Transistor (BJT) Circuits David J. Comerand Donald T. Comer14.1 Introduction
14.2 Physical Characteristics and Properties of the BJT
14.3 Basic Operation of the BJT
14.4 Use of the BJT as an Amplifier
14.5 Representing the Major BJT Effects by an Electronic Model
14.6 Other Physical Effects in the BJT14.7 More Accurate BJT Models
14.8 Heterojunction Bipolar Junction Transistors
14.9 Integrated Circuit Biasing Using Current Mirrors
14.10 The Basic BJT Switch
14.11 High-Speed BJT Switching
14.12 Simple Logic Gates
14.13 Emitter-Coupled Logic
15 RF Passive IC Components Thomas H. Lee, Maria del Mar Hershenson,Sunderarajan S. Mohan, Kirad Samavati, and C. Patrick Yue15.1 Introduction15.2 Fractal Capacitors
15.3 Spiral Inductors
15.4 On-Chip Transformers
SECTION III Circuit Simulations
16 Analog Circuit Simulation J. Gregory Rollins16.1 Introduction
16.2 Purpose of Simulation
16.3 Netlists
16.4 Formulation of the Circuit Equations
16.5 Modified Nodal Analysis
16.6 Active Device Models
16.7 Types of Analysis
16.8 Verilog-A
16.9 Fast Simulation Methods
16.10 Commercially Available Simulators
17 Interconnect Modeling and Simulation Michel S. Nakhlaand Ramachandra Achar17.1 Introduction
17.2 Interconnect Models
http://s2.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp15.pdf/http://chp15.pdf/http://chp15.pdf/http://chp15.pdf/http://chp15.pdf/http://chp15.pdf/http://s3.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp17.pdf/http://chp17.pdf/http://chp17.pdf/http://chp17.pdf/http://chp17.pdf/http://chp17.pdf/http://chp17.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://chp16.pdf/http://s3.pdf/http://chp15.pdf/http://chp15.pdf/http://chp15.pdf/http://chp15.pdf/http://chp15.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://chp14.pdf/http://s2.pdf/8/10/2019 statii radio fm
15/27
2000 by CRC Press LLC
17.3 Distributed Transmission Line Equations
17.4 Interconnect Simulation Issues
17.5 Interconnect Simulation Techniques
18 Power Simulation and Estimation in VLSI Circuits Massoud Pedram18.1 Introduction.
18.2 Software-Level Power Estimation
18.3 Behavioral-Level Power Estimation
18.4 RT-Level Power Estimation
18.5 Gate-Level Power Estimation
18.6 Transistor-Level Power Estimation
18.7 Conclusion
SECTION IV Amplifiers
19 CMOS Amplifier Design Harry W. Li, R. Jakob Baker, andDonald C. Thelen19.1 Introduction
19.2 Biasing Circuits
19.3 Amplifiers
20 Bipolar Amplifier Design Geert A. De Veirman20.1 Introduction
20.2 Single-Transistor Amplifiers
20.3 Differential Amplifiers
20.4 Output Stages
20.5 Bias Reference
20.6 Operational Amplifiers
20.7 Conclusion
21 High-Frequency Amplifiers Chris Toumazou and Alison Payne21.1 Introduction
21.2 The Current Feedback Op-Amp
21.3 RF Low-Noise Amplifiers
21.4 Optical Low-Noise Preamplifiers
21.5 Fundamentals of RF Power Amplifier Design
21.6 Applications of High-Q Resonators in IF-Sampling Receiver Architectures
21.7 Log-Domain Processing
22 Operational Transconductance Amplifiers R. F. Wassenaar,
Mohammed Ismail, and Chi-Hung Lin22.1 Introduction
22.2 Noise Behavior of the OTA
http://chp17.pdf/http://chp17.pdf/http://chp17.pdf/http://chp18.pdf/http://chp18.pdf/http://chp18.pdf/http://chp18.pdf/http://chp18.pdf/http://chp18.pdf/http://chp18.pdf/http://chp18.pdf/http://chp18.pdf/http://s4.pdf/http://chp19.pdf/http://chp19.pdf/http://chp19.pdf/http://chp19.pdf/http://chp19.pdf/http://chp20.pdf/http://chp20.pdf/http://chp20.pdf/http://chp20.pdf/http://chp20.pdf/http://chp20.pdf/http://chp20.pdf/http://chp20.pdf/http://chp20.pdf/http://chp21.pdf/http://chp21.pdf/http://chp21.pdf/http://chp21.pdf/http://chp21.pdf/http://chp21.pdf/http://chp21.pdf/http://chp21.pdf/http://chp21.pdf/http://chp22.pdf/http://chp22.pdf/http://chp22.pdf/http://chp22.pdf/http://chp22.pdf/http://chp22.pdf/http://chp22.pdf/http://chp21.pdf/http://chp21.pdf/http://chp21.pdf/http://chp21.pdf/http://chp21.pdf/http://chp21.pdf/http://chp21.pdf/http://chp21.pdf/http://chp20.pdf/http://chp20.pdf/http://chp20.pdf/http://chp20.pdf/http://chp20.pdf/http://chp20.pdf/http://chp20.pdf/http://chp20.pdf/http://chp19.pdf/http://chp19.pdf/http://chp19.pdf/http://chp19.pdf/http://s4.pdf/http://chp18.pdf/http://chp18.pdf/http://chp18.pdf/http://chp18.pdf/http://chp18.pdf/http://chp18.pdf/http://chp18.pdf/http://chp18.pdf/http://chp17.pdf/http://chp17.pdf/http://chp17.pdf/8/10/2019 statii radio fm
16/27
2000 by CRC Press LLC
22.3 An OTA with an Improved Output Swing
22.4 OTAs with High Drive Capability
22.5 Common-Mode Feedback
22.6 Filter Applications with Low-Voltage OTAs
SECTION V Logic Design
23 Expressions of Logic Functions Saburo Muroga23.1 Introduction to Basic Logic Operations
23.2 Truth Tables23.3 Karnaugh Maps
23.4 Binary Decision Diagrams
24 Basic Theory of Logic Functions Saburo Muroga24.1 Basic Theorems
24.2 Implication Relations and Prime Implicants
25 Simplification of Logic Expressions Saburo Muroga25.1 Minimal Sums
25.2 Derivation of Minimal Sums by Karnaugh Map25.3 Derivation of Minimal Sums for a Single Function by Other Means
25.4 Prime Implicates, Irredundant Conjunctive Forms, and Minimal Products
25.5 Derivation of Minimal Products by Karnaugh Map
26 Binary Decision Diagrams Shin-ichi Minatoand Saburo Muroga26.1 Basic Concepts
26.2 Construction of BDD Based on a Logic Expression
26.3 Data Structure
26.4 Ordering of Variable for Compact BDDs
26.5 Remarks
27 Logic Synthesis with AND and OR Gates in Two LevelsSaburo Muroga27.1 Introduction
27.2 Design of Single-Output Minimal Networks with AND
and OR Gates in Two Levels
27.3 Design of Multiple-Output Networks with AND and OR Gates in Two Levels
28 Sequential Networks with AND and OR Gates Saburo Muroga28.1 Introduction
28.2 Flip-Flops and Latches28.3 Sequential Networks in Fundamental Mode
28.4 Malfunctions of Asynchronous Sequential Networks
28.5 Different Tables for the Description of Transitions of Sequential Networks
http://chp22.pdf/http://chp22.pdf/http://chp22.pdf/http://chp22.pdf/http://s5.pdf/http://chp23.pdf/http://chp23.pdf/http://chp23.pdf/http://chp23.pdf/http://chp23.pdf/http://chp23.pdf/http://chp24.pdf/http://chp24.pdf/http://chp24.pdf/http://chp24.pdf/http://chp25.pdf/http://chp25.pdf/http://chp25.pdf/http://chp25.pdf/http://chp25.pdf/http://chp25.pdf/http://chp25.pdf/http://chp26.pdf/http://chp26.pdf/http://chp26.pdf/http://chp26.pdf/http://chp26.pdf/http://chp26.pdf/http://chp26.pdf/http://chp27.pdf/http://chp27.pdf/http://chp27.pdf/http://crcfsn01/MAC38_1/PRODUCTION/WB004/8593/pdf/chp27.pdfhttp://crcfsn01/MAC38_1/PRODUCTION/WB004/8593/pdf/chp27.pdfhttp://crcfsn01/MAC38_1/PRODUCTION/WB004/8593/pdf/chp27.pdfhttp://chp28.pdf/http://chp28.pdf/http://chp28.pdf/http://chp28.pdf/http://chp28.pdf/http://chp28.pdf/http://chp28.pdf/http://chp28.pdf/http://chp28.pdf/http://chp28.pdf/http://chp28.pdf/http://chp28.pdf/http://chp28.pdf/http://crcfsn01/MAC38_1/PRODUCTION/WB004/8593/pdf/chp27.pdfhttp://crcfsn01/MAC38_1/PRODUCTION/WB004/8593/pdf/chp27.pdfhttp://chp27.pdf/http://chp27.pdf/http://chp26.pdf/http://chp26.pdf/http://chp26.pdf/http://chp26.pdf/http://chp26.pdf/http://chp26.pdf/http://chp25.pdf/http://chp25.pdf/http://chp25.pdf/http://chp25.pdf/http://chp25.pdf/http://chp25.pdf/http://chp24.pdf/http://chp24.pdf/http://chp24.pdf/http://chp23.pdf/http://chp23.pdf/http://chp23.pdf/http://chp23.pdf/http://chp23.pdf/http://s5.pdf/http://chp22.pdf/http://chp22.pdf/http://chp22.pdf/http://chp22.pdf/8/10/2019 statii radio fm
17/27
8/10/2019 statii radio fm
18/27
2000 by CRC Press LLC
36 CMOS Saburo Muroga36.1 CMOS (Complementary MOS)
36.2 Logic Design of CMOS Networks
36.3 Logic Design in Differential CMOS Logic
36.4 Layout of CMOS
36.5 Pseudo-nMOS
36.6 Dynamic CMOS
37 Pass Transistors Kazuo Yanoand Saburo Muroga37.1 Introduction
37.2 Electronic Problems of Pass Transistors37.3 Top-down Design of Logic Functions with Pass-Transistor Logic
38 Adders Naofumi Takagi, Haruyuki Tago, Charles R. Baugh,and Saburo Muroga38.1 Introduction
38.2 Addition in the Binary Number System
38.3 Serial Adder
38.4 Ripple Carry Adder
38.5 Carry Skip Adder
38.6 Carry Look-Ahead Adder38.7 Carry Select Adder
38.8 Carry Save Adder
39 Multipliers Naofumi Takagi, Charles R. Baugh, and Saburo Muroga39.1 Introduction
39.2 Sequential Multiplier
39.3 Array Multiplier
39.4 Multiplier Based on Wallace Tree
39.5 Multiplier Based on a Redundant Binary Adder Tree
40 Dividers Naofumi Takagiand Saburo Muroga40.1 Introduction
40.2 Subtract-And-Shift Dividers
40.3 Higher Radix Subtract-And-Shift Dividers
40.4 Even Higher Radix Dividers with a Multiplier
40.5 Multiplicative Dividers
41 Full-Custom and Semi-Custom Design Saburo Muroga41.1 Introduction
41.2 Full-Custom Design Sequence of a Digital System
42 Programmable Logic Devices Saburo Muroga42.1 Introduction
42.2 PLAs and Variations
http://chp36.pdf/http://chp36.pdf/http://chp36.pdf/http://chp36.pdf/http://chp36.pdf/http://chp36.pdf/http://chp36.pdf/http://chp36.pdf/http://chp37.pdf/http://chp37.pdf/http://chp37.pdf/http://chp37.pdf/http://chp37.pdf/http://chp38.pdf/http://chp38.pdf/http://chp38.pdf/http://chp38.pdf/http://chp38.pdf/http://chp38.pdf/http://chp38.pdf/http://chp38.pdf/http://chp38.pdf/http://chp38.pdf/http://chp39.pdf/http://chp39.pdf/http://chp39.pdf/http://chp39.pdf/http://chp39.pdf/http://chp39.pdf/http://chp39.pdf/http://chp40.pdf/http://chp40.pdf/http://chp40.pdf/http://chp40.pdf/http://chp40.pdf/http://chp40.pdf/http://chp40.pdf/http://chp41.pdf/http://chp41.pdf/http://chp41.pdf/http://chp41.pdf/http://chp42.pdf/http://chp42.pdf/http://chp42.pdf/http://chp42.pdf/http://chp42.pdf/http://chp42.pdf/http://chp42.pdf/http://chp41.pdf/http://chp41.pdf/http://chp41.pdf/http://chp40.pdf/http://chp40.pdf/http://chp40.pdf/http://chp40.pdf/http://chp40.pdf/http://chp40.pdf/http://chp39.pdf/http://chp39.pdf/http://chp39.pdf/http://chp39.pdf/http://chp39.pdf/http://chp39.pdf/http://chp38.pdf/http://chp38.pdf/http://chp38.pdf/http://chp38.pdf/http://chp38.pdf/http://chp38.pdf/http://chp38.pdf/http://chp38.pdf/http://chp38.pdf/http://chp37.pdf/http://chp37.pdf/http://chp37.pdf/http://chp37.pdf/http://chp36.pdf/http://chp36.pdf/http://chp36.pdf/http://chp36.pdf/http://chp36.pdf/http://chp36.pdf/http://chp36.pdf/8/10/2019 statii radio fm
19/27
2000 by CRC Press LLC
42.3 Logic Design with PLAs
42.4 Dynamic PLA
42.5 Advantages and Disadvantages of PLAs
42.6 Programmable Array Logic
43 Gate Arrays Saburo Muroga43.1 Mask-Programmable Gate Arrays
43.2 CMOS Gate Arrays
43.3 Advantages and Disadvantages of Gate Arrays
44 Field-Programmable Gate Arrays Saburo Muroga44.1 Introduction
44.2 Basic Structures of FPGAs
44.3 Various Field-Programmable Gate Arrays
44.4 Features of FPGAs
45 Cell-Library Design Approach Saburo Muroga45.1 Introduction
45.2 Polycell Design Approach
45.3 Hierarchical Design Approach
46 Comparison of Different Design Approaches Saburo Muroga46.1 Introduction
46.2 Design Approaches with Off-the-Shelf Packages
46.3 Full-and Semi-Custom Design Approaches
46.4 Comparison of All Different Design Approaches
SECTION VI Memory, Registers, and System Timing
47 System Timing Ivan S. Kourtev and Eby G. Friedman47.1 Introduction47.2 Synchronous VLSI Systems
47.3 Synchronous Timing and Clock Distribution Networks
47.4 Timing Properties of Synchronous Storage Elements
47.5 A Final Note
Appendix
48 ROM/PROM/EPROM Jen-Sheng Hwang48.1 Introduction
48.2 ROM
48.3 PROM
49 SRAM Yuh-Kuang Tseng49.1 Read/Write Operation
http://chp42.pdf/http://chp42.pdf/http://chp42.pdf/http://chp42.pdf/http://chp43.pdf/http://chp43.pdf/http://chp43.pdf/http://chp43.pdf/http://chp43.pdf/http://chp44.pdf/http://chp44.pdf/http://chp44.pdf/http://chp44.pdf/http://chp44.pdf/http://chp44.pdf/http://chp45.pdf/http://chp45.pdf/http://chp45.pdf/http://chp45.pdf/http://chp45.pdf/http://chp46.pdf/http://chp46.pdf/http://chp46.pdf/http://chp46.pdf/http://chp46.pdf/http://chp46.pdf/http://s6.pdf/http://chp47.pdf/http://chp47.pdf/http://chp47.pdf/http://chp47.pdf/http://chp47.pdf/http://chp47.pdf/http://chp47.pdf/http://chp47.pdf/http://chp48.pdf/http://chp48.pdf/http://chp48.pdf/http://chp48.pdf/http://chp48.pdf/http://chp49.pdf/http://chp49.pdf/http://chp49.pdf/http://chp47.pdf/http://chp47.pdf/http://chp47.pdf/http://chp47.pdf/http://chp47.pdf/http://chp47.pdf/http://chp47.pdf/http://chp49.pdf/http://chp49.pdf/http://chp48.pdf/http://chp48.pdf/http://chp48.pdf/http://chp48.pdf/http://s6.pdf/http://chp46.pdf/http://chp46.pdf/http://chp46.pdf/http://chp46.pdf/http://chp46.pdf/http://chp45.pdf/http://chp45.pdf/http://chp45.pdf/http://chp45.pdf/http://chp44.pdf/http://chp44.pdf/http://chp44.pdf/http://chp44.pdf/http://chp44.pdf/http://chp43.pdf/http://chp43.pdf/http://chp43.pdf/http://chp43.pdf/http://chp42.pdf/http://chp42.pdf/http://chp42.pdf/http://chp42.pdf/8/10/2019 statii radio fm
20/27
8/10/2019 statii radio fm
21/27
2000 by CRC Press LLC
SECTION VII Analog Circuits
54 Nyquist-Rate ADC and DAC Bang-Sup Song54.1 Introduction
54.2 ADC Design Arts
55.3 ADC Architectures
54.4 ADC Design Considerations
54.5 DAC Design Arts
54.6 DAC Architectures
54.7 DAC Design Considerations
55 Oversampled Analog-to-Digital and Digital-to-Analog ConvertersJohn W. Fattarusoand Louis A. Williams III55.1 Introduction
55.2 Basic Theory of Operation
55.3 Alternative Sigma-Delta Architectures
55.4 Filtering for Sigma-Delta Modulators
55.5 Circuit Building Blocks
55.6 Practical Design Issues
55.7 Summary
56 RF Communication Circuits Michiel Steyaert, Marc Borremans,Johan Janssens, and Bram De Muer56.1 Introduction
56.2 Technology
56.3 The Receiver
56.4 The Synthesizer
56.5 The Transmitter
56.6 Towards Fully Integrated Transceivers
56.7 Conclusions
57 PLL Circuits Min-shueh Yuanand Chorng-Kuang Wang57.1 Introduction
57.2 PLL Techniques
57.3 Building Blocks of the PLL Circuit
57.4 PLL Applications
58 Continuous-Time Filters John M. Khoury58.1 Introduction
58.2 State-Variable Synthesis Techniques
58.3 Realization of VLSI Integrators58.4 Filter Tuning Circuits
58.5 Conclusion
http://s7.pdf/http://chp54.pdf/http://chp54.pdf/http://chp54.pdf/http://chp54.pdf/http://chp54.pdf/http://chp54.pdf/http://chp54.pdf/http://chp54.pdf/http://chp54.pdf/http://chp55.pdf/http://chp55.pdf/http://chp55.pdf/http://chp55.pdf/http://chp55.pdf/http://chp55.pdf/http://chp55.pdf/http://chp55.pdf/http://chp55.pdf/http://chp56.pdf/http://chp56.pdf/http://chp56.pdf/http://chp56.pdf/http://chp56.pdf/http://chp56.pdf/http://chp56.pdf/http://chp56.pdf/http://chp56.pdf/http://chp57.pdf/http://chp57.pdf/http://chp57.pdf/http://chp57.pdf/http://chp57.pdf/http://chp57.pdf/http://chp58.pdf/http://chp58.pdf/http://chp58.pdf/http://chp58.pdf/http://chp58.pdf/http://chp58.pdf/http://chp58.pdf/http://chp58.pdf/http://chp58.pdf/http://chp58.pdf/http://chp58.pdf/http://chp58.pdf/http://chp58.pdf/http://chp57.pdf/http://chp57.pdf/http://chp57.pdf/http://chp57.pdf/http://chp57.pdf/http://chp56.pdf/http://chp56.pdf/http://chp56.pdf/http://chp56.pdf/http://chp56.pdf/http://chp56.pdf/http://chp56.pdf/http://chp56.pdf/http://chp55.pdf/http://chp55.pdf/http://chp55.pdf/http://chp55.pdf/http://chp55.pdf/http://chp55.pdf/http://chp55.pdf/http://chp55.pdf/http://chp54.pdf/http://chp54.pdf/http://chp54.pdf/http://chp54.pdf/http://chp54.pdf/http://chp54.pdf/http://chp54.pdf/http://chp54.pdf/http://s7.pdf/8/10/2019 statii radio fm
22/27
2000 by CRC Press LLC
59 Switched-Capacitor Filters Andrea Baschirotto59.1 Introduction
59.2 Sampled-Data Analog Filters
59.3 The Principle of SC Technique
59.4 First-Order SC Stages
59.5 Second-Order SC Circuit
59.6 Implementation Aspects
59.7 Performance Limitations
59.8 Compensation Technique (Performance Improvements)
59.9 Advanced SC Filter Solutions
SECTION VIII Microprocessor and ASIC
60 Timing and Signal Integrity Analysis Abhijit Dharchoudhury,David Blaauw, and Stantanu Ganguly60.1 Introduction
60.2 Static Timing Analysis
60.3 Noise Analysis
60.4 Power Grid Analysis
61 Microprocessor Design Verification Vikram Iyengarand Elizabeth M. Rudnick61.1 Introduction
61.2 Design Verification Environment
61.3 Random and Biased-Random Instruction Generation
61.4 Correctness Checking
61.5 Coverage Metrics
61.6 Smart Simulation
61.7 Wide Simulation
61.8 Emulation61.9 Conclusion
62 Microprocessor Layout Method Tanay Karnik62.1 Introduction
62.2 Layout Problem Description
62.3 Manufacturing
62.4 Chip Planning
63 Architecture Daniel A. Connorsand Wen-mei Hwu
63.1 Introduction63.2 Types of Microprocessors
63.3 Major Components of a Microprocessor
63.4 Instruction Set Architecture
http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://s8.pdf/http://chp60.pdf/http://chp60.pdf/http://chp60.pdf/http://chp60.pdf/http://chp60.pdf/http://chp60.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp62.pdf/http://chp62.pdf/http://chp62.pdf/http://chp62.pdf/http://chp62.pdf/http://chp62.pdf/http://chp63.pdf/http://chp63.pdf/http://chp63.pdf/http://chp63.pdf/http://chp63.pdf/http://chp63.pdf/http://chp63.pdf/http://chp63.pdf/http://chp63.pdf/http://chp63.pdf/http://chp63.pdf/http://chp62.pdf/http://chp62.pdf/http://chp62.pdf/http://chp62.pdf/http://chp62.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp61.pdf/http://chp60.pdf/http://chp60.pdf/http://chp60.pdf/http://chp60.pdf/http://chp60.pdf/http://s8.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/http://chp59.pdf/8/10/2019 statii radio fm
23/27
2000 by CRC Press LLC
63.5 Instruction Level Parallelism
63.6 Industry Trends
64 ASIC Design Sumit Gupta and Rajesh K. Gupta64.1 Introduction
64.2 Design Styles
64.3 Steps in the Design Flow
64.4 Hierarchical Design
64.5 Design Representation and Abstraction Levels
64.6 System Specification
64.7 Specification Simulation and Verification64.8 Architectural Design
64.9 Logic Synthesis
64.10 Physical Design
64.11 I/O Architecture and Pad Design
64.12 Tests After Manufacturing
64.13 High-Performance ASIC Design
64.14 Low Power Issues
64.15 Reuse of Semiconductor Blocks
64.16 Conclusion
65 Logic Synthesis for Field Programmable Gate Array (FPGA) TechnologyJohn Lockwood65.1 Introduction
65.2 FPGA Structures
65.3 Logic Synthesis
65.4 Look-up Table (LUT) Synthesis
65.5 Chortle
65.6 Two-Step Approaches
65.7 Conclusion
SECTION IX Test and Testability
66 Testability Concepts and DFT Nick Kanopoulos66.1 Introduction: Basic Concepts
66.2 Design for Testability
67 ATPG and BIST Dimitri Kagaris67.1 Automatic Test Pattern Generation
67.2 Built-In Self-Test
68 CAD Tools for BIST/DFT and Delay Faults Spyros Tragoudas68.1 Introduction68.2 CAD for Stuck-at Faults
68.3 CAD for Path Delays
http://chp63.pdf/http://chp63.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp65.pdf/http://chp65.pdf/http://chp65.pdf/http://chp65.pdf/http://chp65.pdf/http://chp65.pdf/http://chp65.pdf/http://chp65.pdf/http://chp65.pdf/http://s9.pdf/http://chp66.pdf/http://chp66.pdf/http://chp66.pdf/http://chp66.pdf/http://chp67.pdf/http://chp67.pdf/http://chp67.pdf/http://chp67.pdf/http://chp68.pdf/http://chp68.pdf/http://chp68.pdf/http://chp68.pdf/http://chp68.pdf/http://chp68.pdf/http://chp68.pdf/http://chp68.pdf/http://chp68.pdf/http://chp67.pdf/http://chp67.pdf/http://chp67.pdf/http://chp66.pdf/http://chp66.pdf/http://chp66.pdf/http://s9.pdf/http://chp65.pdf/http://chp65.pdf/http://chp65.pdf/http://chp65.pdf/http://chp65.pdf/http://chp65.pdf/http://chp65.pdf/http://chp65.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp64.pdf/http://chp63.pdf/http://chp63.pdf/8/10/2019 statii radio fm
24/27
2000 by CRC Press LLC
SECTION X Compound Semiconductor Digital IntegratedCircuit Technology
69 Materials Stephen I. Long69.1 Introduction
69.2 Compound Semiconductor Materials
69.3 Why III-V Semiconductors?
69.4 Heterojunctions
70 Compound Semiconductor Devices for Digital CircuitsDonald B. Estreich70.1 Introduction
70.2 Unifying Principle for Active Devices: Charge Control Principle
70.3 Comparing Unipolar and Bipolar Transistors
70.4 Typical Device Structures
71 Logic Design Principles and Examples Stephen I. Long71.1 Introduction
71.2 Static Logic Design
71.3 Transient Analysis and Design for Very-High-Speed Logic
72 Logic Design Examples Charles E. Chang, Meera Venkataraman,andStephen I. Long72.1 Design of MESFET and HEMT Logic Circuits
72.2 HBT Logic Design Examples
SECTION XI Design Automation
73 Internet Based Micro-Electronic Design Automation (IMEDA) FrameworkMoon Jung Chungand Heechul Kim73.1 Introduction
73.2 Functional Requirements of Framework73.3 IMEDA System
73.4 Formal Representation of Design Process
73.5 Execution Environment of the Framework
73.6 Implementation
73.7 Conclusion
74 System-Level Design Alice C. Parker, Yosef Tirat-Gefen,and Suhrid A. Wadekar74.1 Introduction
74.2 System Specification
74.3 System Partitioning74.4 Scheduling and Allocating Tasks to Processing Modules
74.5 Allocating and Scheduling Storage Modules
http://s10.pdf/http://s10.pdf/http://chp69.pdf/http://chp69.pdf/http://chp69.pdf/http://chp69.pdf/http://chp69.pdf/http://chp69.pdf/http://chp70.pdf/http://chp70.pdf/http://chp70.pdf/http://chp70.pdf/http://chp70.pdf/http://chp70.pdf/http://chp71.pdf/http://chp71.pdf/http://chp71.pdf/http://chp71.pdf/http://chp71.pdf/http://chp72.pdf/http://chp72.pdf/http://chp72.pdf/http://chp72.pdf/http://s11.pdf/http://chp73.pdf/http://chp73.pdf/http://chp73.pdf/http://chp73.pdf/http://chp73.pdf/http://chp73.pdf/http://chp73.pdf/http://chp73.pdf/http://chp73.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://s11.pdf/http://chp73.pdf/http://chp73.pdf/http://chp73.pdf/http://chp73.pdf/http://chp73.pdf/http://chp73.pdf/http://chp73.pdf/http://chp73.pdf/http://chp72.pdf/http://chp72.pdf/http://chp72.pdf/http://chp71.pdf/http://chp71.pdf/http://chp71.pdf/http://chp71.pdf/http://chp70.pdf/http://chp70.pdf/http://chp70.pdf/http://chp70.pdf/http://chp70.pdf/http://chp69.pdf/http://chp69.pdf/http://chp69.pdf/http://chp69.pdf/http://chp69.pdf/http://s10.pdf/8/10/2019 statii radio fm
25/27
2000 by CRC Press LLC
74.6 Selecting Implementation and Packaging Styles for System Modules
74.7 The Interconnection Strategy
74.8 Word Length Determination
74.9 Predicting System Characteristics
74.10 A Survey of Research in System Design
75 Synthesis at the Register Transfer Level and the Behavioral LevelJ. Bhasker75.1 Introduction
75.2 The Two HDLs
75.3 The Three Different Domains of Synthesis75.4 RTL Synthesis
75.5 Modeling a Three-State Gate
75.6 An Example
75.7 Behavioral Synthesis
75.8 Conclusion
76 Performance Modeling and Analysis in VHDL James H. Aylorand Robert H. Klenke76.1 Introduction
76.2 The ADEPT Design Environment
76.3 A Simple Example of an ADEPT Performance Model76.4 Mixed-Level Modeling
76.5 Conclusions
77 Embedded Computing Systems and Hardware/Software Co-DesignWayne Wolf77.1 Introduction
77.2 Uses of Microprocessors
77.3 Embedded System Architectures
77.4 Hardware/Software Co-Design
78 Design Automation Technology Roadmap Donald Cottrell78.1 Introduction
78.2 Design Automation An Historical Perspective
78.3 The Future
78.4 Summary
SECTION XII Algorithms and Architects
79 Algorithms and Architectures for Multimedia and BeamformingCommunications Flavio Lorenzelliand Kung Yao79.1 Introduction
79.2 Multimedia Support for General Purpose Computers
79.3 Beamforming Array Processing and Architecture
http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://chp75.pdf/http://chp75.pdf/http://chp75.pdf/http://chp75.pdf/http://chp75.pdf/http://chp75.pdf/http://chp75.pdf/http://chp75.pdf/http://chp75.pdf/http://chp75.pdf/http://chp76.pdf/http://chp76.pdf/http://chp76.pdf/http://chp76.pdf/http://chp76.pdf/http://chp76.pdf/http://chp76.pdf/http://chp77.pdf/http://chp77.pdf/http://chp77.pdf/http://chp77.pdf/http://chp77.pdf/http://chp77.pdf/http://chp78.pdf/http://chp78.pdf/http://chp78.pdf/http://chp78.pdf/http://chp78.pdf/http://chp78.pdf/http://s12.pdf/http://chp79.pdf/http://chp79.pdf/http://chp79.pdf/http://chp79.pdf/http://chp79.pdf/http://chp79.pdf/http://chp79.pdf/http://chp79.pdf/http://chp79.pdf/http://chp79.pdf/http://chp79.pdf/http://chp79.pdf/http://chp79.pdf/http://chp79.pdf/http://s12.pdf/http://chp78.pdf/http://chp78.pdf/http://chp78.pdf/http://chp78.pdf/http://chp78.pdf/http://chp77.pdf/http://chp77.pdf/http://chp77.pdf/http://chp77.pdf/http://chp77.pdf/http://chp76.pdf/http://chp76.pdf/http://chp76.pdf/http://chp76.pdf/http://chp76.pdf/http://chp76.pdf/http://chp75.pdf/http://chp75.pdf/http://chp75.pdf/http://chp75.pdf/http://chp75.pdf/http://chp75.pdf/http://chp75.pdf/http://chp75.pdf/http://chp75.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/http://chp74.pdf/8/10/2019 statii radio fm
26/27
2000 by CRC Press LLC
SECTION XIII Design Languages
80 Design Languages David L. Barton80.1 Introduction
80.2 Objects and Data Types
80.3 Standard Logic Types
80.4 Concurrent Statements
80.5 Sequential Statements
80.6 Simultaneous Statements
80.7 Modular Designs80.8 Simulation
80.9 Test Benches
81 Hardware Description in Verilog: An Introductory TutorialZainalabedin Navabi81.1 Elements of Verilog
81.2 Basic Component Descriptions
81.3 A Complete Design
81.4 Controller Description
81.5 Gate and Switch Level Description
81.6 Test Bench Descriptions
81.7 Summary
http://s13.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp81.pdf/http://chp81.pdf/http://chp81.pdf/http://chp81.pdf/http://chp81.pdf/http://chp81.pdf/http://chp81.pdf/http://chp81.pdf/http://chp81.pdf/http://chp81.pdf/http://chp81.pdf/http://chp81.pdf/http://chp81.pdf/http://chp81.pdf/http://chp81.pdf/http://chp81.pdf/http://chp81.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://chp80.pdf/http://s13.pdf/8/10/2019 statii radio fm
27/27