IEEE TAaM Von" on Nu.deo. Scienee, VotN4S-23, No.3, June 1976

STEADY STATE GAMMA TESTING OF A 4KNMOS DYNAMIC RAM

D. W. Coleman and B. M. TemkinGeneral Dynamics Electronics Division

Post Office Box 2566Orlando, Florida 32802

Samples of the Texas Instruments TMS4060JL,4096 bit dynamic random-access memory (4K RAM) were

tested in the ionizing environment of a Ce source.Irradiated in an active condition, the devices were

observed to fail at 1 x 10 rads (Si). Twenty-four hoursafter irradiation, 4 of the 5 devices tested were againfunctional. The devices were not powered and were atroom temperature during the 24 hour anneal period.

The RAM's were tested in support of digitalmultiplexing and rate buffering equipment being designedfor the NIMBUS-G satellite by General Dynamics,Electronics Division. The 4K RAM was selected for usein a data rate buffer due to size, weight and poweradvantages over bipolar or magnetic devices. A majorconcern in using the NMOS device in the satelliteapplication was the ionizing radiation which the RAMmust tolerate in earth orbit. The total ionizing doseabsorbed by the RAM in earth orbit will be derived fromthe interaction of the satellite with the Van Allen radi-ation belts and from the solar flare activity. Samplesof the RAM were tested in the ionizing environment of a

Ce source to determine their total ionizing radiationdose failure threshold. This data was then used todetermine the amount of shielding nece7ssary to limitthe dose absorbed by the device to an acceptable level.

The five devices tested were commercial deviceswith no special fabrication or processing. They weredesignated TMS4060JLand date coded 7521. The NMOSsilicon gate RAM's use a single transistor cell structurewith an MOS capacitor for the memory element. NMOSwas chosen over PMOS by the manufacturer due to itsadvantages of faster speed and lower threshold voltage.The lower threshold voltage simplifies the design of theTTL interface. Compared to a three-transistor memorycell, a one-transistor cell has the advantage of asmallernumber of circuit elements, which makes pos-sible a smaller cell size. The one-transistor cell alsohas a higher process yield than a three-transistor cellof the same size because the topographical structureof a one transistorcell is less susceptible to process

defects. However, it has the disadvantage of yield-ing logic signals of only 200 millivolts at the outputof the memory cell, if it is to meet the specified speed,voltage and power goals.

Todetectthe low signal level, the sense amp-lifier shown in figure 1 was used. The 4096 memorybits are arranged in a 64 row by 64 column matrix withone sense amplifier associated with one column and64 rows.

Abrief discussion of the memory operation is asfollows: Assume data has been loaded into the memory.

Manuscript received by NPSS Dec. 15, 1975.

DATA INPUTBUFFER

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Figure 1. Sense Amplifier (Courtesy of Texas Instruments)

Prior to addressing the row or column, the dummy capac-itors (C4 and C4' of figure 1) are precharged to a volt-age midway between the " 1 " and " 0" state with Q4 andQ4' turned off by an internal clock. If one of the rows

X1 through X32 is selected, transistor Q4' in the dummy

cell is also turned on. The reference charge applied tothe sense amplifier by the dummy cell will enable maxi-mum discrimination between the "S0I" or "1" stored inthe cell enabled (say Q5, C5). The flip-flop formed byQ3 and Q3' will assume the state dictated by the imbal-ance of charge on its inputs, recharging C5 to itspre-addressed state and outputting the data to the out-put buffer.

The test patterns used to check the operation ofthe devices were alternating 1-0, alternating 0-1, andall 0 input. These patterns were written and read at1 bit/as with the chip enable input operating at a 50%duty cycle. The test pattern was written into sequen-tial address locations in groups of 256 bits. Chipenablewas turned off for a 1, 680 microseconds intervalwhich was followed by a refresh cycle. Data was thenwritten into sequential addresses in the write-off-refresh cycle until all 4096 locations were filled. Whenall memorylocationswerefull, the test setread sequen-tial memory locations in groups of 256 bits, with "off"and "refresh" cycles the same as in the write mode.The test set wrote data only once, and then repeatedlyread the data until it was reset. During and immedi-ately after irradiation, the bias supplies were at thenominal vendor-recommended voltages, but the inputsignals were at the minimum specified voltages, withminimum pulse widths and spacing.

The radiation exposures were made using a

Ce source, which deposited 1.0 x 10 rads (Si)/min.

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The output of the sample under testwas mon-itored duringirradiation using the test conditions and test set pre-viously explained.

Five devices were tested. Two of these werebiased continuously during exposure and three werebiased for approximately 30 percent of the exposure timeto simulate system usage. Both of the devices under

continuous bias were still functional after 1 x 10 rads;

one failed after 2 x 10 rads and the other after 4.3 x

10 rads. Two of thedevices biased 30 percent of the

exposure time failed after 1 x 10 rads (one of them inlocation 3328 only); the third device failed in approxi-

mately 20 locations after 2 x 10 rads.

Approximately 24hours after thegamma expos-ure, four of the five devices had recovered, and theyagain operated properly at the nominal recommendedconditions. However, at the minimum specifiedpowersupply and data voltages, only one would operate reli-ably. After two days a second device operated at theminimum conditions and after five days a third devicewould operate at the minimum conditions.

The typical failure observed for a given addresswas the appearances of a high state output regardless ofthe data input. The normal transition to the low stateprior to the appearance of valid data still occurred. Afterthe final exposure, in an attempt to force the devices tofunction, VDDwas varied from 8 to 13.5v, Vcc from 1 to

6v and VBB from 1 to lOv, maintaining VDD + VBB <19v.

Decreasing refresh cycle time to less than 0.5 ms had noobservable effect on the operation of the test devices.It was noted that lowering the substate bias voltageand/or the data input low voltage enhanced the opera-tion of some of the devices.

Three possible failure mechanisms are postu-lated. They are: a loss of charge in the storage capac-itors, a change in the ratio of the stray capacitance tothe storage capacitance, and a shift in threshold voltage.Dynamic RAM's require a refresh period to replace thecharge on the storage capacitor lost due to leakage. Theloss of charge due to radiation seems unlikely as a fail-ure mechanism since decreasing the refresh time intervalhad no effect on the failed devices. A change in theratio of the stray to storage capacitance is considered

a potential failure mechanism since the difference be-tween a "1" and "0" voltage seen by the sense amplifieris given in reference 1 as:

VA= (VDOVAO)/(l + CA/CS)where Cs and CA are the storage and amplifier stray

capacitance, and V and VAO are the voltages across

capacitors Cs and CA respectively before the cell is

selected. Capacitance CA is parasitic and includes all

the stray capacitance which is significant since Cs is

on the order of one tenth picofarad. However, a largechange in the ratio of the two capacitances is notexpected since the two are formed by similar mechan-isms and materials.

Based on the N-channel CMOS data in reference2, a decrease in threshold voltage of two hundred milli-

volts would be expected for a dose of 10 rads. Thischange should not be sufficient to cause problems in thedigital gates in the RAM since the design probably allowsthis amount of change for noise margins. However, if theoutput of the precharge voltage generator shifted bytwenty millivolts, due to the threshold voltage shift, thediscrimination of the sense amplifier would be degraded.The change in precharge voltage due to a shift in thres-hold voltage is difficult to predict, without knowing thedetails of the precharge voltage generator circuit. How-ever, this postulation is favored over the other two by theauthors.

Typical failure levels for commercial CMOS

logic devices are in the order of 10 rads (Si) 2,3,4,5.

The failure of the NMOS RAM at 10 rads (Si) is believedto berelated to the low logic levels associated with thesingle cell design. Three samples from another vendoralso failed in the same range of radiation dose as didthe Texas Instruments samples. The other manufactureralso used the NMOS process with the single transistorcell. Since samples from both manufacturers failed at

the 10 rads level, the probability that each set of sam-ples is from an extremely sensitive lot is reduced.

Based on the anneal characteristics of the RAMafter radiation exposure, this device is consideredapproved for this application if the absorbed radiation

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dose rate is shielded to 10 rads Si)/year. Further

Ce 3 testing will be conducted on devices from theproduction lot intended for satellite usage to verify thatthe failure level and the anneal characteristics have notdegraded.

References

1. C. Kuo, N. Kitagawa, E. Ward, P. Drayer "SenseAmplifier Design is Key to 1-transistor Cell in 4096-bit RAM", Electronics, P116-121, Sept. 13, 1973.

2. R.A. Burghard and C.W. Gwyn, "Radiation FailureModes in CMOS Integrated Circuits, "Nuclear

David W. Coleman received hisB.S. degree from the Univer-sity of South riorida in 1966and his M.S. in Physics fromRollins College in 1971. From1968 to 1974 he was employedby Martin Marietta, Orlando.where he was involved in com-ponent nuclear test and harden-ing. He is presently employedby General Dynamics. Orlando,

where he is responsible for nuclear hardening.

Science, Vol. NS-20, No. 6, P300-306, Dec. 1973.

3. D.H. Habing, and B.D. Shafer, "Room TemperatureAnnealing of Ionization Induced Damage in CMOSCircuits," Nuclear Science, Vol. NS-20, No. 6,P307-314, Dec. 1973.

4. H.A. Eisen, A.S. Epstein, R.A. Polimadei, "Test-ing and Characterization of Radiation HardenedC-MOS Devices", Harry Diamond LaboratoriesReport HDL-PR-75-3, August 1975.

5. E. E. King, G. P. Nelson, H. L. Hughes, "TheEffects of Ionizing Radiation on Various CMOSIntegrated Circuit Structures", Nuclear Science,Vol. NS-19, No. 6, P264-270, Dec. 1972.

Bruce Temkin is EngineeringManager for the Space SyptemsDepartment at General Dynamics,Orlando. He received a B.S.E.E.from Carnegie-Mellon Institutein 1962 and an M.S.E.E. fromNewark College of Engineeringin 1969. He has 10 years ex-perience in Spaceborne Tel-emetry, Command, and DigitalManagement equipment.

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