Stephen Lau

IEEE P1149.7, a complementary superset of the

IEEE 1149.1 standard

Squeezing the power out of a Debug and Test Interface

(DTI)

Stephen Lau - 12/03/07

TI Public Data2

Agenda What is IEEE P1149.7? What are the benefits? How is it added to my system? How does it work? Summary

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TI Public Data3

What is IEEE P1149.7? What is IEEE 1149.1 (JTAG)?

Connection for manufacturing test (BSDL) Connection for debugging software

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TI Public Data4

Standards Focus1149.1 vs. P1149.7

Test

Apps

Compliance: Preserving boundary scan for System

on a Chip (SoC)

Capability: Features for debug

Boundary Scan: Finding card level

connectivity issues

1149.1 P1149.7

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TI Public Data5

What is IEEE P1149.7? What is IEEE 1149.1 (JTAG)?

Connection for manufacturing test (BSDL) Connection for debugging software

What is IEEE P1149.7? A new IEEE standard currently in process P1149.7 is not a replacement for 1149.1 P1149.7 uses 1149.1 as its foundation P1149.7 provides 1149.1 extensions P1149.7 provides 2-pin operating modes

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P1149.7 History and Status MIPI Origins

Objective – define a backwards compatible minimum pin debug interface Strategy – requirements gathering, technical debate Tactics – solicit competing proposals, choose a winner Result – P1149.7 was handily selected as winning proposal vs. SWD

Collaboration with Nexus consortium Objective – Compare common needs, explore common solution Strategy - Joint meetings, compare requirements Tactics - Specifications reviewed, incorporate feedback Result – Agreement to pursue IEEE standard because of large field of use

IEEE PAR approved Test, Debug, and backwards IEEE 1149.1 compatibility considerations Specification reviewed and revision underway now Presumed Result – IEEE 1149.7 standard in early 2008

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What are the benefits?

Operate with fewer pins Fewer pins required for debug/test

Add instrumentation using the same pins Application level debug

TAP power management Reduce power consumption

Provide framework for diverse debug technologies Improve compatibility

Preserve gateway to debug of SI errors/defects Maintain capabilties

SI IP Re-use proven technology

Software IP Re-use proven technology

Debug and Test Tools Re-use proven technology

Pin protocols other than those supporting scan Support for existing technology

Mix and match legacy/new IP Backward compatible

Equal treatment for all industry IP Support for existing technologyInn

ovati

on

/

Cu

sto

miz

ati

on

Pre

serv

e

Investm

en

tD

o m

ore

wit

h less

Do more with less

Innovation / Customization

Preserve Investment

Feature Benefit

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TI Public Data8

Extending JTAG

SW Driver

Emulator

TCLK

TMS

TDI

TDO

TCLK

TMS

TDI

TDO

TC

LK

TM

S

TD

I

TD

O

CoreA

EMU0

EMU1

EM

U1

EM

U0

TC

LK

TM

S

TD

I

TD

O

CoreB

EM

U1

EM

U0

EMU0

EMU1

JTAG Pins Required=6

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TI Public Data9

Extending JTAG

SW Driver

Emulator

TCLK

TMS

TDI

TDO

TCLK

TMS

TDI

TDO

TC

LK

TM

S

TD

I

TD

O

CoreA

•IEEE1149.1 example: Data path is from TDI through cores and out TDO.

EMU0

EMU1

EM

U1

EM

U0

TC

LK

TM

S

TD

I

TD

O

CoreB

EM

U1

EM

U0

EMU0

EMU1

Read Mem

0xcoffee

JTAG Pins Required=6

Communication

(4)

Instrumentation (2)

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TI Public Data10

Extending JTAG

SW Driver

Emulator

TCLK

TMS

TDI

TDO

TCLK

TMS

TDI

TDO

TC

LK

TM

S

TD

I

TD

O

CoreA

TCLK

TMS

TDI

TDO

TCLK

TMS

TDI

TDO

•Use adapters to prototype with existing IEEE1149.1 HW and SW.•IEEE1149.7 starts in 1149.1 mode for compatibility. •Switch the Adapter to IEEE1149.7 mode by sending a command.

EMU0

EMU1

EMU0

EMU1

EM

U1

EM

U0

TC

LK

TM

S

TD

I

TD

O

CoreB

EM

U1

EM

U0

EMU0

EMU1

EMU0

EMU1

Mode=JTAGMode=advanced

TMSTMSCSwitch to 1149.7

•TMS is now TMSC.•TDI and TDO are now optional.

JTAG Pins Required=6JTAG Pins Required=4

Optional signal

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TI Public Data11

Extending 1149.1

SW Driver

Emulator

TCLK

TMS

TDI

TDO

TC

LK

TM

S

TD

I

TD

O

CoreA

TCLK

TMS

TDI

TDO

TCLK

TMS

TDI

TDO

EMU0

EMU1

EMU0

EMU1

EM

U1

EM

U0

TC

LK

TM

S

TD

I

TD

O

CoreB

EM

U1

EM

U0

EMU0

EMU1

Mode=Advanced

TMSTMSC

•EMU0 and EMU1 are typically used for to gather large amounts communication with a target application

•Using Background Data eXchange (BDX) and Custom Data eXchange (CDX), target information can be transferred.

•For maximum compatibility, CDX can be used to carry manufacturer defined protocols.

0xcoffee

0xcoffee

Pins Required=4Pins Required=2

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TI Public Data12

Extending 1149.1

SW Driver

Emulator

TCLK

TMSC

TDI

TDO

TC

LK

TM

S

TD

I

TD

O

CoreA

TCLK

TMS

TDI

TDO

EMU0

EMU1

EM

U1

EM

U0

TC

LK

TM

S

TD

I

TD

O

CoreB

EM

U1

EM

U0

EMU0

EMU1

Mode=Advanced

TMSTMSC

Pins Required=2

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TI Public Data13

IEEE P1149.7 Connection Topologies

TCK

TMS

TCK

TMS

TDI

TDO

TDI

TDO

TCKTMSTDITDO

4-pin Star Scan Topology

DTCInterface TDI

TDO

TCKTMS

TCK

TMS

TCK

TMS

TDI TDO

TDITDO

TCKTMS

TDO

TDI

TDI

TDO

TCKTMS

4-pin Series Scan Topology

DTCInterface

TCK

TMS

TCK

TMS

TCKTMS

2-pin Star Scan Topology

DTCInterface

TCKTMS

When all chips have Class 4 or Class 5 TAPs

the 4-pin topologies may be operated as a

2-pin topology

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TI Public Data14

Key Control Concepts

Extend functionality of BYPASS and IDCODE instructions (“overload” these instructions)

Keep new command structure invisible to existing 1149.1 TAPs

Create commands without using TDI or TDO Use commands to create registers without changing IR/DR

scan paths

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TI Public Data15

Overloading the Bypass Instruction(using Zero-bit DR-Scans (ZBS))

• IR register set to BYPASS or IDCODE instruction by:

• IR-Scan or

• Test-Logic-Reset

• ZBS = CaptureExitUpdate

• The number of consecutive ZBSs are counted to create a control level that specifies the overloaded function

• This is performed by standard IEEE 1149.1 TAP controller state sequences

Method:

BYPASSIR Register

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TI Public Data16

Zero-Bit Scans Create Control Levels

• Count the number of Zero-Bit-Scans (ZBS) to change the definition of BYPASS instruction.

• Lock control level when the Shift-DR state is reached.

Key:

1….

2….

3….

Lock Control Level at 3.

BYPASSIR Register

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TI Public Data17

Creating a Control Level

Example: Steps to create a control level 31. IR-Scan with BYPASS instr.

2. ZBS

3. ZBS

4. ZBS

Example: Steps to create a control level 51. IR-Scan with BYPASS instr.

2. ZBS

3. ZBS

4. ZBS

5. ZBS

6. ZBS

BYPASS instruction

Increment control level from 0 to 1

Increment control level from 1 to 2

Increment control level from 2 to 3

BYPASS instruction

Increment control level from 0 to 1

Increment control level from 1 to 2

Increment control level from 2 to 3

Increment control level from 3 to 4

Increment control level from 4 to 5

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TI Public Data18

SW directed mode switches between JTAG modes and advanced modes. Software drivers always use IEEE state sequences.

Framework for multiple debug and other technologies

IEEE1149.7 - Debug and Test Tech. Binder“All industry debug and test IP co-exists behind a standard Interface”

1149.7

Debug/TestFramework

Applications TAPs

Boundary Scan

JTAG

Bulk Data TransferInstrumentation Sources

Custom Data TransferBDM (Freescale)/ SWD (ARM)/other

BDX

CDX

Test Test and Private Interface Modes

Power Power down test logic when not used

Narrow (2)

or

Wide (4)

Standard interface

benefits tools

suppliers and users

IEEE 1149.1 signaling used at start-up

SW directed mode switches between JTAG modes and advanced modes

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TI Public Data19

Deployment Profiles

Flash, CPLDs, FPGAs

Minimal

SOC or Micro-Controller

ModerateSophisticated

SOC

Most

Deployment Profile

Test Test and private interface modes

Specialtyfunctions

Power Chip power and reset controllermanaging interface power

Every microwattcounts

Shift_DR state may be used to overlay any custom protocol

CDX Extensibility(non-JTAG functions)

Pause and Idle states provideinstrumentation channel

BDX Pin and BW Utilization

JTAG Optimized serialization of TMS, TDI, Ready, and TDO Multiple formats

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TI Public Data20

1149.7 “Classes” IEEE 1149.1 Extensions

Class T0 – Assure IEEE Compliance for chips with multiple TAPs Class T1 – Add control functions (e.g. functional reset, power) Class T2 – Add performance features for series Class T3 – Add Star configuration

Advanced Two-Pin Operation

Class T4 – Add two pin operation Class T5 – Add instruction/custom pin use to two pin operation

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TI Public Data21

IEEE 1149.7 Summary

Do More with Less: Lower pin count

Remaining backwards compatible with Si IP and Tools

Gain additional debug capability

Stephen Lau

Backup

Stephen Lau - 12/03/07

TI Public Data23

IEEE 1149.7 Classes• Ensure compliance with 1149.1 to enhance compatibility with industry test infrastructure

• 4 Power Down modes friendly to: Board Test, Chip Test, and Application Debug

• Chip Level Bypass

• Built-in Chip Select Mechanism

• 2 pins provide scan, Test-Logic-Reset (TLR), and instrumentation (serialized transactions)• Download specific modes (Target Input only)• 2x Clock rate and optimized transactions

• Concurrent Debug and Instrumentation using same pins• Instrumentation of data passed during Run-Test-Idle, Pause-DR, and Pause-IR states• Custom technologies can use the test access port pins in Shift-DR state. (ex: SWD, BDM, etc. )

• After Test-Logic-Reset (TLR) multi-TAP devices:• Conform to mandatory 1149.1 instruction behavior• 1-bit DR-Scan for bypass instruction

• Addresses stacked die and multi-chip module needs

• Power: Test logic power-down, etc.

• Performance: •Shorten multi-chip scan chains with 1-bit IR bypass

•Glue-less star configuration

• Pins: Less pins and more functions•Faster downloads to target

•Equivalent performance with fewer pins

• Instrumentation (BDX)

• Customization (CDX)

Class T0

Class T1

Class T3

Class T4

Class T5

Class T2

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TI Public Data24

Chip1149.7logic

ExistingSi IP

Narrow (2-pins) or

Wide (4-pins)

P1149.7 – Adds capability to 1149.1“Minimizing Changes/Maintaining Performance”

IEEE 1149.7 added No changes to existing Si IP

Emulator1149.7logic

Existingcontroller

IEEE 1149.7 added May be added to existing controller

20 MHz 20 MHz40 MHz

• The same or better performance than IEEE1149.1 may be achieved in some cases• With advanced protocol

• Falling–edge to falling edge timing allows doubling TCK rate• The amount of information transferred is minimized to boost performance• Two or less bits are transferred/TAP controller state in some cases•If a device supports SSCAN modes, performance can improve more.

= the same TCK/TAP state rate as IEEE 1149.1 2 bits/TAP state

2*TCK rate

1.7 bits/TAP state= 1.17X the TCK/TAP state rate as IEEE 1149.1

1 bits/TAP state= 2X the TCK/TAP state rate as IEEE 1149.1

1.5 bits/TAP state= 1.3X the TCK/TAP state rate as IEEE 1149.1

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TI Public Data25

Series Bypass Uses TAP selection and bypass bit to:

improve series conneted devices scan performance using 1-bit chip bypass for very long scan chains

Create a “firewall” to protect system operation when DTC is connected or disconnected from the TS

38-bit IR 24-bit IR 16-bit IR 16-bit IR 6-bit IR

1-bitbypass

1-bitbypass

6-bit IR

Chip Level Bypass Chip Level Bypass

I want to access this

one!

Total Chain=100

Total Chain=8

TAP1 TAP2 TAP1 TAP2 TAP1

TAP1

TAP1 and TAP2 frozen

in IDLE state.

TAP1 and TAP2 frozen

in IDLE state.

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TI Public Data26

Situation at Power-Up At power up, you can have the bypass as the default (JScan1 scan format)

Protects TAPs from spurious signal Prevents core corruption during “hot” connections Command sequence makes TAPs visible. Command sequence is transparent to

IEEE1149.1 devices allowing a mix of IEEE1149.1 and IEEE1149.7 devices.

1-bitbypass

1-bitbypass

6-bit IR

TAP1

TAP1 and TAP2 frozen in TLR state.

TAP1 and TAP2 frozen in TLR state.

38-bit IR 24-bit IR 16-bit IR 16-bit IR 6-bit IR

TAP1 TAP2 TAP1 TAP2 TAP1

1149.7 Device 1149.7 Device 1149.1 Device

1149.7 Device 1149.7 Device 1149.1 Device

Configuration at Power UP

Configuration after

“firewall” lowered.