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Semiconductor Research Corporation Strategic Research for a Dynamic Industry SRC Annual Report 1998
Transcript
Page 1: StrategicResearchfor a DynamicIndustry · enhancements due to copper interconnect systems will lessen, new lithography technologies will be needed, new ... SRC’s long, productive

S e m i c o n d u c t o r R e s e a r c h C o r p o r a t i o n

Strategic Research for aDynamic Industry

S R C A n n u a l R e p o r t 1 9 9 8

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MembersAdvanced Micro Devices, Inc.Digital Equipment CorporationEastman Kodak CompanyHarris CorporationHewlett-Packard CompanyIBM CorporationIntel CorporationLSI Logic CorporationLucent TechnologiesMotorola IncorporatedNational Semiconductor CorporationNorthrop Grumman CorporationTexas Instruments Incorporated

Science Area MembersCadence Design SystemsEaton CorporationEtec Systems, Inc.Mentor Graphics CorporationNovellus Systems, Inc.Shipley CompanySynopsysUltratech Stepper

Associate MemberThe MITRE Corporation

Affiliate MembersCVC, Inc.FLIPCHIP Technologies, L.L.C.Mission Research CorporationNeo Linear, Inc.Numerical Technologies, Inc.OMNIVIEW, Inc.PDF Solutions, Inc.Physical ElectronicsSAL CorporationSILVACO Data SystemsTessera, Inc.Verity Instruments

Government ParticipantsU.S.Army Research OfficeDARPANational Institute of Standards

and TechnologyNational Science Foundation

Strategic PartnersSEMATECHSemiconductor Industry Association

A recap of 1998 would beincomplete without mention ofthe retirement of James F.Freedman.

The following is an excerptfrom Larry Sumney’s remarks atthe retirement event honoringJim Freedman ... “One of Jim’smost valued contributions tothe SRC is his leadership forTECHCON. He served as GeneralChairman for TECHCON ’88 inDallas, TECHCON ’90 in SanJose, TECHCON ’93 in Atlanta,TECHCON ’96 in Phoenix andTECHCON ’98 in Las Vegas. Theearly TECHCONs included facultypresentations and studentposters; TECHCON ’98 wasentirely student presented andincluded 228 papers andposters. Jim was recognized byhis colleagues after TECHCON’96 this way, ‘If I had to summa-rize the best of Jim over all ofthe TECHCONs, it is that he hasalways had the ability to leadwhen needed, delegate owner-ship and responsibility wheneverpossible, and then defend andsupport his staff in all battlesgreat and small.’”

TECHCON is very likely Jim'slegacy to SRC; it provides aforum for looking very closely,on a regular basis, at theresearch and the way resultsare delivered to decide thatSRC does make a positive dif-ference.

This annual report is dedicated to James F. Freedman

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Table of Contents

VisionSemiconductor Research Corporation (SRC) will provide competitive advantage to its members

as the world’s premier research management consortium in delivering relevant research results andrelevantly educated technical talent.

MissionSRC’s mission is to cost-effectively exceed members’ expectations by delivering:

• Managed, innovative, semiconductor technology research responsive to members’ needs and guided by the NTRS, focusing on universities

• Relevantly educated university graduates

• Timely transfer of research results

• Strengthened university semiconductor technology capability through partnerships with members

• Collaboration to enhance commercialization and leveraged research

The annual report of the Semiconductor Research Corporation is published each year to summarizethe directions and results of the SRC research program, present the formal financial report and provideinformation on activities and events of the SRC community for the previous calendar year.

A copy of this report and additional information about SRC are accessible on the World WideWeb at http://www.src.org.

Message from the President & CEO . . . . . . . . . .2

About SRC . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Research Contributions . . . . . . . . . . . . . . . . . . .5

SRC Restructures . . . . . . . . . . . . . . . . . . . . . .10

Value Management Programs . . . . . . . . . . . . .11

Student Relations . . . . . . . . . . . . . . . . . . . . . .12

Aristotle Award . . . . . . . . . . . . . . . . . . . . . . .13

Technical Excellence Award . . . . . . . . . . . . . . .14

Industrial Liaison Program . . . . . . . . . . . . . . . .15

SRC Web Site . . . . . . . . . . . . . . . . . . . . . . . . .16

MARCO’s Focus Center Research Program . . . . .17

Intellectual Property Report . . . . . . . . . . . . . . .18

Financial Report . . . . . . . . . . . . . . . . . . . . . . .19

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Semiconductor Research Corporation

Message from the President & CEO

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Each day, SRC focuses on the future of our dynamic industry. During the pastyear, SRC’s member companies, university researchers and government partners, andour dedicated staff, have positioned themselves to begin the 21st century in anincreasingly complex environment.

To align with the industry’s continuing evolution, SRC has analyzed and reviewed itscore program research structure and combined its seven previous science areas into four:

1. Computer-Aided Design and Test Sciences (CADTS)2. Integrated Circuits and Systems Sciences (ICSS)3. Materials and Process Sciences (MPS)4. Nanostructure and Integration Sciences (NIS)

In addition, SRC has created a special Cross-disciplinary Semiconductor Research (CSR) program that encouragesinitiatives for high-risk research addressing long-term needs of the industry.

What is Next for Technology?The industry will progress toward 100 nm technology nodes with little interruption in cadence. 193 nm

lithography tools will probably suffice to enable this progress, with increasing efforts to add product valuethrough integration of analog/RF signals with digital signals on a single chip. Industry growth will be spurred byexpanding applications and very high-performance/functionality products.

At, or slightly beyond the 100 nm node, the quality of MOSFET transistors will decline, the performanceenhancements due to copper interconnect systems will lessen, new lithography technologies will be needed, newmetrology technologies will be required, packaging problems will become more challenging and the tensionbetween the need to design at high levels of abstraction for productivity enhancements and the need to utilizemore sophisticated (and complex) deep submicron physical device models will be heightened.

In order to address these issues, we are working with SRC members and our university partners to:• Discover new integrable gate dielectrics and new shallow junction technologies to provide high quality

MOSFETs below 100 nm• Invent new low-K interlevel dielectrics to extend the benefits of copper interconnect technologies• Develop new chip architectures that minimize the need for global connections to extend the price-

performance gains for IC technology at the rate provided by industry for three decades• Support the challenge of defining technologies for future generations of patterning systems• Advance the state of metrology for critical dimensions, doping distributions, etc., needed for below

100 nm production• Create new generations of interconnect-aware IC CAD tools and test strategies• Explore novel self-assembly methods that could offer lower complexity processes for IC fabrication• Begin to blend IC and molecular technologies to develop self-configuring architectures that lower

fabrication costs.

This scenario of possibilities is exciting, and can result from SRC’s continued focus on the future. Our commit-ment will pay off, for our industry, and in solutions to human problems and applications we have yet to imagine.

Sincerely,

Larry W. SumneyPresident & CEO

Larry W. Sumney

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Semiconductor Research Corporation

SRC’s ValueThe members of SRC consortium have identified

four products which they consider as critical to pro-viding value to them. Theseproducts are:

Research ResultsSRC sponsors universityresearch that is responsive tothe critical challenges identi-fied in the National Technology

Roadmap for Semiconductors (NTRS). Technologysolutions are key to maintaining the pace of evolu-tion of the technology roadmap necessary for con-tinued health and profitability of the semiconductorindustry.

Relevantly Educated TalentGraduate students engaged in carrying out SRC-sponsored research represent the highest quality ofstudents. SRC research programs prepare them tobe the talented scientists and engineers our mem-bers need to ensure success.

University InfrastructureThrough the sponsorship of universities, SRC hashelped to establish an infrastructure of talentedfaculty which provides resources for the industry to utilize for solving their specific, individual problems.

NetworkingThe consortium provides a forum for the industry,university and government experts and managers at a variety of levels to interact with peers. Theseinteractions provide numerous opportunities forbenchmarking.

The SRC team must continuously focus on alldimensions of the value. We must help create thevalue through the products described above, deliverit in the most effective way, facilitate our membersto extract it in a most cost-effective manner andenhance it on an ongoing basis. The semiconductorindustry is one of the most rapidly changing indus-tries. These changing business conditions changeour member companies’ needs continuously. Weare committed to providing the most value to our

3

SRC was established in 1982 as a research consortium to manage long-term, pre-competitive research in semiconductor technology at U.S.universities and, in doing so, develop the relevantly educated tal-ent to meet the needs of the industry. This consortium hasconsistently produced and delivered research results andrelevantly educated students over the past 17 years.Obviously, the research and the students are stronglyinterdependent. SRC directs a set of research pro-grams, over 300 projects, carried out at over fiftyleading universities now throughout North America.These programs are funded by the member compa-nies comprising of the full value chain of the semi-conductor industry including the infrastructure com-panies (materials, equipment and tools for use by ICcompanies) as well as the IC product.

SRC’s long, productive existence is a testimonial tothe vision and dedicated commitment of thousands ofindividuals in the entire community of the consortium andhas proven to be an excellent and enduring commitment forcooperative research.

About SRC

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4 Semiconductor Research Corporation

members by anticipating, adapting and respondingto their changing needs. In order to keep the con-sortium strong and dynamic, we work with the rep-resentatives of our member companies on the Boardof Directors and various advisory boards to continu-ously revitalize our products, programs, processesand systems. Some examples of the dynamic natureof our business and the value that the community ofour consortium have brought about in 1998 are pre-sented in various sections of this report.

Some of the major initiatives and events during1998 which demonstrate the value, the vitality and thedynamic nature of our consortium include:• Initiation of research in Front End Processes

(FEP) for technology nodes <100nm by sponsoring an FEP Center in collaboration with our strategic partner, SEMATECH.

• Launching of the two Focus Centers dedicated to very long-term (7-8 yrs) research in the areas of Design and Test and in Interconnect Sciences (Page 17).

• A highly successful and valuable TECHCON, our biannual Technical Conference to showcase the best of both our research dollars and students.

• Restructuring of our Science Areas, based on member input and anticipating their future needs (Page 10).

• Some of our highly coveted awards that recognizethe value provided by various constituents of theSRC community, such as the Aristotle Award (Page 13), the Technical Excellence Award (Page 14), and the Industrial Liaison Award (Page 15).

Stronger Partnership with SEMATECH In addition to the focus on the intrinsic value fromSRC, we have also endeavored to maximize thevalue for our members from the entire chain of R&Dperformed in the two sister consortia, SRC (bothFCRP managed by MARCO and the core programsof SRC) and SEMATECH. Working with theExecutive Technical Advisory Boards and the seniormanagement of these two consortia, we have devel-oped and implemented a model and processes, andcoordinated schedules to link Strategic Plans of

About SRC

these organizations. This allows a more robustresearch portfolio, which incorporates inputs fromSEMATECH (whose primary mission is R&D in manu-facturing infrastructure). The linkage also allows,where appropriate, well-planned technology flowfrom SRC research results to “TechnologyHardening” by SEMATECH.

In 1998, SEMATECH and SRC increased bytwofold over 1997 the number of programs withhigh interconsortia relevance. Higher relevancemeans an increased likelihood that SRC-sponsoreduniversity research will be taken up by SEMATECHand commercialized through a supplier partner,resulting in equipment or processes that can beinserted into member company fabs.

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Current

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Future

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Larry Sumney(SRC), with MarkMelliar-Smith(SEMATECH) atTECHCON ’98.

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Semiconductor Research Corporation 5

Research Contributions

SRC’s research is accomplished through the efforts of world-class university professors and their graduate students sup-ported by industrial liaisons from the member companies and SRC’s science area directors. In 1998, research results werevery well aligned with the “difficult challenges” as identified in the National Technology Roadmap for Semiconductors.Details of the 1998 research results can be found on the SRC Web site. Below are some of the significant highlights.

Automatic Test Pattern Generation - Testabilityhas been identified as a major issue on increasinglycomplex designs. The Nemesis 2.2.3 ATPG softwarefrom Professors Tracy Larrabee and Joel Fergusonat the University of California at Santa Cruz nowhas the ability to generate tests for several modelsof resistive bridging faults. Circuits may include bothcombinational and sequential elements, as well astristates. The companion software SPROING 2.0performs diagnosis for single stuck-at, transition, orbridging faults with only a stuck-at fault dictionary.

High-Level Power Estimation - Power manage-ment is increasingly important as complexitiesincrease. It is imperative for portable applicationsas well as to relieve thermal package concernsaffecting long-term reliability. Professor Farid Najmand his students at the University of Illinois atUrbana-Champaign have developed macroscopicdesign methods aimed at power estimation. Prior todesign, the top-down method predicts required areaand power of circuit blocks using a high-level func-tional description, delay specification, gate library,and I/O switching activity; the bottom-up methodmacromodels large circuit blocks based on inputswitching activity.

Interconnect Synthesis - Professor LawrencePileggi and his students at CMU are working todevelop metrics, methodologies and algorithms toenable accurate, reliable design – both electrical andgeometric – of integrated circuit and system inter-connect. Progress in 1998 includes (1) developmentof a new accurate RC-delay model (H-gamma) forinterconnect synthesis to replace the long-used, butinaccurate (for deep submicron regime) Elmore RC-delay model, and (2) development of a new accu-rate, efficient approach for extracting frequency-dependent inductance for interconnect.

Design SciencesProcessor Verification - An increasingly difficult

challenge of microprocessor design is assuring correctoperation before product manufacture and shipment.Three investigators working in formal verificationmade advances in proving processor correctness,and helped raise correctness demonstration to a higherlevel. Professor J. Strother Moore and his studentsat UT-Austin developed a formal description of amulti-issue, speculative execution machine and tech-niques for verifying the difficult exception handlingmechanisms. Professor Randy Bryant and studentsat Carnegie Mellon University (CMU) developedabstraction techniques making possible the efficientverification of pipelined processors. Professor EdClarke and students at CMU applied new modelchecking techniques to out-of-order instructionverification. Hardware/Software Codesign - The hard-ware/software codesign tool and methodologyPOLIS from Professor Alberto Sangiovanni-Vincentelliat the University of California at Berkeley formed thebasis for the Felix codesign tool commercialized bySRC member Cadence Design Systems. A technologytransfer course in June 1998 presented the conceptsand operation of codesign to an industry audienceof semiconductor designers and customers anddesign automation vendors.

Verification Interacting with Synthesis - TheVerification Interacting with Synthesis system (VIS1.3, was released by the University of California atBerkeley, the University of Colorado, and theUniversity of Texas at Austin in September. This isthe third release of what has become the de factostandard platform for testing formal verificationideas. The new release, among many other things,adds combinational and sequential synthesis withinthe VIS framework, forward model checking, andfinite state machine restructuring for power reduc-tion. Professor Robert Brayton reports an average oftwo downloads daily from the Berkeley Web site.

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6 Semiconductor Research Corporation

Process Integration and Device Science3-D Silicon-on-Insulator (SOI) Technologies

Using Epitaxial Lateral Overgrowth (ELO) -Integrated Circuits of giga-scale integration andbeyond may require that devices be fabricated inmultiple levels, i.e., 3-D integration. Stacking devicesin 3-D has potential for increasing the density ofmemories and microprocessors, but could also allowfaster parallel processing with computational buildingblocks. Led by Professor Gerold Neudeck at PurdueUniversity, silicon on insulator (SOI) technologies havebeen developed using selective epitaxial growth(SEG), epitaxial layer overgrowth (ELO) and Chemical-Mechanical Polishing (CMP) to create device sizeislands. To achieve 3-D integration, multiple layers ofSOI (MLSOI) islands were formed by repeating theprocess for a single layer. MOSFETs can be placed inboth layers of islands. Deep submicron, FD-SOI p-MOSFETs have been fabricated in both layers todemonstrate the device quality of the material in eachlayer. (Devices have not yet been fabricated in bothlayers on the same chip.) In addition, This techniqueprovides a 3-D geometry with very smooth interfacesfor possible future quantum devices and nanostruc-tures. Material quality is a critical issue in SOI tech-nology. The material fabricated with this SEG/ELOtechnology is high quality. Islands as small as 150 nmx 150 nm x 40 nm thick and as large as 5 mm x 150µm x 0.1µm thick have been fabricated.

Factory SciencesFeasibility study of a contamination-defect-

fault relationship and mapping tool -Traditionalyield-ramping has relied on physical failure analysisto diagnose problems with a manufacturing process.However, physical failure analysis is an expensive,labor-intensive and sometimes unfruitful venture.A faster technique has been developed by ProfessorW. Maly and his students at CMU which uses electricaltest information to perform cost-effective defectdiagnosis. The purpose of this study was to exam-ine the feasibility for using this approach to reliablymap electrical circuit faults uniquely to the defectcausing the fault. A contamination-defect-fault(CDF) relationship is modeled in CODEF, which,given a prescribed process and circuit layout topology,maps a contamination particle into a process defectresulting in a defective circuit. The SPICE circuit ofthis defective IC segment is then extracted andcatalogued. A comparison of a measured circuitfault with a catalogue of simulated faults, each cor-related with a known defect, then maps a measuredcircuit fault uniquely to a known defect. In thisstudy CODEF was used to characterize faults of aSRAM as a test vehicle for Intel’s 0.25-µm CMOSprocess. Fault paretos were generated fromsimulation data and verified against results fromIntel’s yield analysis group with focus on process start-up problems during definition of poly lines. The keygoal of the study was the identification of both thepredominant fault and the most problematic pro-cessing step during the process phase. Followingsubstantial CODEF simulations (250,000 simulationswith particles evenly distributed among 80 process-ing steps), a unique fault type list for each of the80 processing steps was extracted by circuit netlistcomparison tool, Gemini-II. The resulting 80 fault-type lists were combined by a final netlist compari-son to one large fault-type list. Stacked bar graphsand fault paretos of all processing steps were gener-ated and compared to process startup data. Themost problematic processing steps as well as themost frequent SRAM faults were identified success-fully and scripts were written to visualize the layoutlocation of particles causing the specific faults.

Research Contributions

Photo courtesy of IBM Corporation

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Lithography Defect Simulation - Professor W.Maly and his students at CMU have also collaboratedwith AMD to apply CMU’s 2-D topographical simu-lation tool, METROPOLE, to the simulation of defectsin i-line lithography. In this case, METROPOLE wasused to map defect types to faulty photoresist pro-files, which formed the basis of a dictionary. This cor-relation was then used to provide insight into defectmechanisms that cause major distortions in photore-sist profiles. The nature of the distorted patterns wasused in yield improvement efforts by comparing simu-lation results with the observed photoresist profiles onwafers. Using this methodology, defect sources wereidentified and defect densities were dramatically low-ered, in one some by a factor of 10X.

Interconnect SciencesFabrication of Ultra-thin C-Si Polymer Films

for Use as Adhesion and Diffusion Barriers inCu/Low-K Integration - The introduction of Cu inmetallization architectures requires a barrier both toprevent diffusion of Cu into the device material andalso to improve Cu adhesion to the dielectric sub-strate. In order to meet the requirement of 0.1micron geometries, such films should be capable ofconsistent processing and performance at thicknesses < 100 Å. Professor Jeff Kelber and his students atthe University of North Texas have fabricated C-Sifilms on Cu and Ta substrates by UV or electron-induced cross-linking of vinyl silane monomers. Films< 100 Å thick have inhibited Cu diffusion to tempera-tures in excess of 800 K (527 C). Auger studies of Cudeposited onto such films suggest adequate adhesiondue to a strength of Cu-substrate chemical interac-tion comparable to that between Cu and Ta with one

monolayer of oxygen. The films show excellent ther-mal stability on Cu and Ta, and do not delaminateunder thermal cycling. Films formed on Ta do notdecompose at temperatures below 1000 K. Filmscontaining only C, Si and H react slowly until O hasbeen stoichiometrically inserted in existing Si-Cbonds. This property may afford a mechanism forpreparing ultrathin silicon oxycarbide and silicon nitro-carbide films with useful chemical and electronicproperties. The chemical structures and properties ofthe films formed to date suggest an excellent poten-tial as “capping” layers to inhibit Cu diffusion intoxerogels and other porous dielectrics with dielectricconstants < 2.0.

Lithography SciencesAdvanced Resist Research - Professor

Grant Willson and his students at UT-Austincontinue to push the extensibility of opticalpatterning by designing and demonstratingthe feasibility of optically printing arrays of 80nm line/120 nm space pairs with a novel singlelayer resist and 193 nm phase mask technolo-gy. During 4Q98, they also optically printedisolated arrays of 80 nm features using 193nm radiation, novel top surface imaging mate-rials, and a binary mask. Their results suggestthat optical patterning might be extensiblethrough the end of the current NTRS.

Maskless Patterning - Professor Calvin Quateand his students at Stanford have patterned rows ofdeep sub micron features by scanning a linear arrayof 50 addressable probe tips. Also, Professor Dai atStanford recently demonstrated a moderately lowtemperature CVD process for growing dense, pat-terned, anisotropic brush-like arrays of nanotubes.This emerging control over the synthesis of nanotubesrepresents a potential breakthrough opportunity withbroad applicability beyond patterning.

Semiconductor Research Corporation 7

Specific notching defects in photoresist lines such asshown in (a) and (b) above can now be identified andunderstood by simulations and then reduced usingfocused yield improvement efforts.

(a) (b)

Photographs provided by Professor Hongjie Dai, Stanford University

Photographs provided by Advanced Micro Devices, Inc.

Patterned Arrays of Nanotubes

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8 Semiconductor Research Corporation

Resist Synthesis and Modeling - Professor JeanFrechet’s team at UC-Berkeley, in collaboration withProfessor Quate’s group at Stanford, has designednovel resist systems and demonstrated the feasibilityof patterning with monolayers of beam sensitivedendrimers. These dendrimers can be engineered todifferent effective diameters, ~5-8 nm, and can packin regular arrays on the surface of wafers. Theprobe beam induced decomposition of a specificdendrimer promises to image nanometer scaleopenings to the substrate.

Materials and Bulk Process SciencesModeling of Ion Implantation - Professor Al

Tasch at UT-Austin completed the development andvalidation of the ultra-low energy model in UT-MAR-LOWE by making major modifications to the classi-cal binary collision approximation (BCA) theory suchthat it is applicable at ultra low energies. This newmodel has been experimentally verified for B and Asimplants at energies down to 1 and 2 KeV, respec-tively and model predictions are in good agreementwith SIMS data, achieving excellent fits to a varietyof SIMS profiles from KeV to MeV energies, andfrom B to In masses. This will be important in creat-ing ultra-shallow source/drain junctions for CMOStransistors at nodes below 100nm.

Research on high K gate dielectrics forMOSFETs at Minnesota - As the MOS transistorcontinues to scale, better gate dielectrics are neededto obtain required transistor drive characteristicswhile maintaining sufficient voltage breakdownsand low device leakage, a critical factor for lowpower designs. Professor Steve Campbell hasdemonstrated high K films with an equivalent oxidethickness (EOT) of about 1 nm. This research has

attained a significant milestone in the search for asuitable sub- 1 nm high K gate dielectric. This workis important to the re-engineering of the CMOStransistor for nodes below 100 nm.

Packaging SciencesMoire Study of Structural Integrity of High-

Density Flip-Chip Packages - Plastic area-arraypackages with under-filled flip-chip configurationhave become an enabling technology for high-per-formance and low-cost giga-scale packaging inte-

gration. The development of area-arraypackages incorporates new sets of materi-als, processes and interconnect structuresthat are not always optimized and compat-ible. These issues can give rise to seriousmanufacturing and reliability problems asthe package types enter production.Structural integrity is of particular concerndue to thermal deformation caused by themismatch in thermal and mechanical prop-erties of the packaging materials and thesilicon. The development of phase-shiftMoire interferometry led by Professor PaulHo at UT-Austin has provided a high-reso-lution capability for direct measurement ofthe stress-strain distribution in flip-chip

packages. Using a phase shift technique, the inter-ferometer has demonstrated a resolution of 26 nmfor structures as small as 25 microns. This is a 16ximprovement over standard Moire interferometry,extending the technique for studying chip-to-pack-aging interconnects for future generations. Theresults were used for direct assessment of the struc-tural integrity and experimental verification for com-puter modeling, which, in turn, provided feedbackfor design optimization and processing improve-ment. In collaboration with member companies, thistechnology is being applied for packaging develop-ment of Cu/low k interconnects.

Environmental Safety and HealthResist Research - Professor Chris Ober and his

students at Cornell University have designed newfamilies of resist materials that can be patternedwith an environmentally benign, closed loop, super-critical CO2 development process. This process isanalogous to that used for decaffinating millions ofpounds of coffee annually and would create little orno developer waste. During 1998, this team demon-strated the feasibility of patterning arrays of 200 nmline/space pairs.

Each sphere is a globularpolymetric macromoleculewith a diameter of 1-10 nm

Photochemical reactionscause either (a) the decom-position of the macro-molocule ...

... or (b) exclusion of themacromolecule from theself-assembled monolayer

Addressing Individual Molecules

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Semiconductor Research Corporation

MetrologyUltra-low Voltage Electron Beam Imaging -

The detection and identification of circuit defects assmall as a few nanometers becomes critically impor-tant as feature sizes shrink to those dimensions.Professor David Joy’s research team at the Universityof Tennessee-Knoxville has developed new approach-es to metrology using ultra-low voltage electronbeam spectroscopy [1-100 eV] and has demonstratedthe feasibility of resolving gross composition defectson the nanometer scale and at high speed. The ultra-low energy beam eliminates damage and contamina-tion concerns. The initial demonstration using anAuger spectrometer with a 10 nm probe size demon-strated a count rate about 105 higher than expectedfor X-ray analysis. Spectra can be recorded in a veryshort time with good signal to noise ratio.

Development of High Resolution (10 ns/100nm) Thermometry for Devices, Interconnects, andPackages - As feature sizes shrink and circuits oper-ate at higher frequencies, the ability to measuretemperature with high spatial and temporal resolu-tion becomes more important. Highly localized tem-perature excursions are having a greater and greaterinfluence on the performance and reliability ofdevices (e.g., SOI MOSFETs), interconnects (e.g., ESDevents in thin metal lines), and packages (e.g., at flipchip, CSP, and BGA interfaces). In addition, novelmethods with high resolution are required to char-acterize the thermal properties of the new thin filmsbeing introduced at all levels of circuit manufactur-ing. Professor Kenneth Goodson and his students

at Stanford have developed a unique thermometrycapability that provides the spatial and temporal res-olution required to study and characterize all ofthese phenomena. The system employs opticalreflectance in both the far-field and near-fieldregimes as the thermal probe. The far-field regime isused to look at structures with dimensions as smallas 500 nm and the near field for structures withdimensions as small as 100 nm. The time resolution is10 ns or less. Work is now under way that uses thisunique tool for better understanding and improvedmodeling of the thermal properties of SOI devices,ESD phenomena, packaging interfaces and thin films.

Semiconductor Modeling and SimulationThe fourth year of the SRC’s CRADA on

Semiconductor Modeling and Simulation involving10 SRC member companies, 10 universities, LosAlamos National Laboratory and Sandia NationalLaboratory was extremely productive. The CRADAthrusts are: Bulk Processes, Gridding Technologies,Materials Reliability and Topography. One of theCRADA projects is focused on the development andvalidation of a physically-based reliability estimationtool for VLSI interconnect systems. This projectinvolves collaboration between the NationalLaboratory scientists, led by Dr. Galen Straub ofLANL, Professor Carl Thompson of MIT, andProfessor Harold Frost of Dartmouth College. Theteam is working to extend 2-D interconnect predic-tive reliability tools developed at the universities tohandle 3-D structures with appropriate representa-tion of interconnect sidewall effects. In 1998, excel-lent progress was made on interconnect metal graingrowth for use in electromigration reliability compu-tations. The sophisticated grid technology, LaGrit,developed by the National Laboratories, was usedfor 3-D models of dynamic grain structure motionand shape evolution under excitation.

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Supercritical Co2 Development of Photoresists

Image with 191 nm Source

Polycrystalline Film Evolution with Annealing

Grain Growth to Stagnation• Driving Forces for Grain Growth

– Grain boundary energy reduction– Surface, interface and strain energy minimization

Photograph provided by Dr. David Cartwright, Los Alamos National Laboratory

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SRC Restructures in 1999 to Optimize Member ValueThe structure of the industry SRC series is changing as we approach the 21st century; for example, more equipment sup-

pliers are also becoming process providers, CAD companies increasingly offer design services, the number of fabless IC compa-nies is growing and SRC members are directing efforts to their core DSP, Telecommunications and Microprocessor businesses.

By moving to fewer science areas (seven areasare reduced to four in the new structure) thechange favorably positions SRC to:• attract new members from the equipment supplier

and fabless IC industries. New members mayparticipate as Science Area members with duesscaled to their actual areas of interest.Equipment and materials suppliers will find valueas Material and Process Sciences members; CADcompanies as Computer-Aided Design and TestSciences members. Science Area members haveaccess to the entire SRC portfolio.

• encourage effective and efficient memberinvolvement in a broad-based cross-disciplinaryplanning effort. Strategic Planning occurs at theScience Area level. Each member company mayassign representatives to the four Science AreaCoordinating Committees, who oversee strategicand planning efforts. Although they may assigna representative to any or all of the eight relatedThrust Technical Advisory Boards, members whochoose to limit their representatives to specificthrust areas can still engage in the full spectrumof planning activities through their CoordinatingCommittee representatives.

The four new science areas are:Computer-Aided Design and Test Sciences (CADTS)

The challenges of supporting the design of abillion transistor chips and systems will requireunprecedented advances in design tools at manylevels and in test methodologies. CADTS researchspans physical design, synthesis, verification and testfor digital and mixed-signal systems. CADTS seeks todevelop innovative approaches to increased designproductivity in response to the needs of membersand also contributes to new product concepts forthe CAD industry.

Integrated Circuits and Systems Sciences (ICSS)

This new science area is designed to address thegrowing design needs of members and to attract newmembers from the design services industry and fromthe fabless integrated circuit industry. ICSS will focuson new circuit and system design methodologies andconcepts to serve the members for whom integrateddesign solutions are critical to competitiveness.

Materials and Process Sciences (MPS)

In order to meet the performance requirements forfuture generation integrated circuits, the semiconductorindustry must re-engineer the MOSFET, it must employpatterning systems providing sub 100 nm feature sizes,and it must address the limitations imposed by knownmetal and insulator interconnect systems. MPS isdesigned to provide a synergistic approach to the res-olution of challenges by comprehending materials andprocess research in device, interconnect, patterning,and environmental safety and health technologies.

Nanostructure and Integration Sciences (NIS)

The idea of technology integration is central tothis new science area at the chip, package and factorylevels. NIS seeks new devices realized by integratedprocesses to satisfy transistor needs in the 2010time frame. NIS also conducts research on advancedpackage technologies that are central to the realiza-tion of integrated systems, and it takes an integratedview of the operation of the factory as a systemwhose performance is to be optimized.

Synergistic to the four science areas, a specialCross-disciplinary Semiconductor Research (CSR)program encourages initiatives for high-risk researchthat may lead to breakthrough or disruptive tech-nologies addressing the long-term needs of theindustry. CSR provides one year exploratory fundingfor cross-disciplinary teams to develop proposals forsupport from one or more of the SRC science areas.It is one way SRC attempts to tap innovation andpromote revolutionary approaches to addressing thenext generation of IC challenges.

SRC Restructures

10 Semiconductor Research Corporation

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Semiconductor Research Corporation

Value Management Programs

11

Value Management ProgramsIn 1998, the scope of the SRC Technology

Transfer Group was formally extended to addressthe entire value chain – including the creation, deliv-ery, extraction and advocacy of value stemmingfrom the SRC research agenda and results.Accordingly, the Technology Transfer TechnicalAdvisory Board (TTTAB) was renamed the ValueChain Technical Advisory Board (VCTAB) and theirresponsibilities were expanded and documented.

A Focus on Information QualityDuring this transitional year, much of the opera-

tional activity needed to support the identification,storing and distribution of research information wasformally placed under the Value Managementumbrella. The Value Management team, in conjunc-tion with SRC staff, assures the quality of this infor-mation so that it can be extracted monthly to themember-secure area of the SRC Web site.

Team-Driven AchievementsKey accomplishments were guided by two

VCTAB subteams established in 1998: Effectivenessand TECHCON Marketing. The Effectiveness teamtargeted the implementation of industry and uni-versity recommendations made at the 1997 SummerStudy. Site review pre-reading materials describingkey research accomplishments, subsequent year’splans, and technology transfer highlights were deliv-ered to Technical Advisory Board members attendingthe review. At the request of industry, research pro-posals were posted to the SRC Web site for AdvisoryBoard access. Additionally, TAB members reviewingresearch proposals are now provided a summary ofthe technical recommendations made to investiga-tors at the annual site review – the purpose is toprovide a framework for evaluating the proposal.

Under the guidance of the Marketing sub-team, a distributed electronic approach to publicityfor TECHCON’98, allowed SRC to eliminate over$20,000 in production and mailing costs. Theapproach allowed delivery of member-customiz-

able, concise, targeted information aboutthe conference in formats suitable for e-mail and posting to the SRC and memberinternal Web sites.

Three panel sessions at TECHCON ’98, werecoordinated by the Value Management Team.Dinesh Mehta of SRC moderated a session entitledSIA/SRC/SEMATECH/MARCO: Addressing the NTRSGrand Challenges, which was designed to encour-age creative approaches to addressing the critical‘red’ areas of the NTRS. A session on StrategicWorkforce Issues was moderated by Professor MarkLaw of the University of Florida. A third session on10 Ways to Simplify Working with SRC was moder-ated by Gail Massari of SRC.

Ken Ports, VCTAB Chair from Harris Semiconductorchallenges the VCTAB to address improvedprocesses that assure maximum member value –from planning through technology diffusion.

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Student Relations

1998 saw the growth of established student programs and much effort spent on starting two new initiatives: a pilotprogram of SRC Undergraduate Research Scholarships and creation of a Human Resource Needs Roadmap. Going forward,the careful integration of established programs and new initiatives will ensure a broader scope for SRC Student Relations.

1998 Accomplishments

• 779 students were supported under SRC con-tract research providing an outstanding sourceof technology transfer through internships andpermanent hire.

• Of 139 graduating students, 75 were hired bySRC member organizations/universities, repre-senting 54% of the graduating population. Avalue model for student hires was developed bythe Student Relations TAB to assist members indefining the value derived through student hires.

• 55 Fellowships were supported under theGraduate Fellowship Program. Of the 10 Fellowscompleting the GFP in 1998, 6 joined membercompanies or university faculties.

• 14 company-named fellowships were in placeduring 1998 as follows: AMD, 3; Harris, 1; IBM,2; Motorola, 4; National, 2; Texas Instruments, 2.

• 9 Master’s Scholarships were supported, fourcontinuing from 1997 and 5 beginning in thefall of 1998.

• Access to and information about SRC studentswas enhanced in 1998 by increasing the num-ber of student resumes available on the Website, enhancing search capability and providing aweb-based spreadsheet of students looking forinternships.

• 236 SRC students presented their research at TECHCON ’98.

• 20 SRC companies participated in JobsFair at TECHCON ’98.

• The GFP Annual Conference Banquet was heldat TECHCON ’98 and the Fellows Award for“Outstanding Research Presentation” was pre-sented to Dennis Sylvester, University of Californiaat Berkeley.

New Directions

• A program of Undergraduate ResearchScholarships was successfully piloted during1998 with 9 summer scholarships and 2academic year scholarships placed throughSRC-funded faculty. A small number of schol-arships will be awarded for the summer of1999 as funds allow.

• SRC accepted responsibility for the Engineers/University segment of a Human ResourceNeeds Roadmap at the request of the SIA andwith support and direction from the SRC Boardof Directors. The Roadmap document, largelycompleted in 1998, includes a needs assessmentand gap analysis for technical human resourcefor the semiconductor industry into the 21stcentury. This document will guide much of thework of Student Relations in 1999.

12 Semiconductor Research Corporation

SRC Fellows at TECH-CON ’98. New SRCFellow, Stefan Riegefrom MIT, explains hisresearch to JeanKelsey who will com-plete her doctoralstudy at SUNY/Albanyas an SRC Fellow in1999 and join IBMCorporation.

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Aristotle Award Presented at GFP Conference

Two Aristotle Awards were presented in 1998 recognizing excellence in teaching through the research process. Theawards were presented at the Graduate Fellowship Program Annual Conference at TECHCON ’98 in Las Vegas, NV, toProfessors Franco Cerrina and Joseph Greene.

Professor Cerrina directs the Center for X-ray Lithography at the University of Wisconsin-Madison. His formerstudents speak of his ability as a scientist and researcher that has made him a leader in his field and the affectthat has had on their own development as graduate students. Through Professor Cerrina’s leadership, dedica-tion and hard work, the Center for X-ray Lithography at the University of Wisconsin hasbeen molded into one of the world’s leading research centers in the area of advanced lith-ography, producing graduate students with skills and background that allow immediatecontribution to the semiconductor industry.

Professor Greene is well known for providing an atmosphere in which outstanding stu-dents can produce outstanding accomplishments. He teaches his students to be good citi-zens in the scientific community by encouraging their early participation in professionalsocieties. His students attribute the success of Professor Greene’s research in great mea-sure to the team spirit of the group. Students are expected to work together for the ben-efit of the group, and they are expected to understand all aspects of the research well enough to challengeeach other’s ideas. In his tenure at the University of Illinois, Professor Greene has graduated 34 doctoral andnine master’s students; four SRC Fellows are among his current and past students.

GFP FellowsAndrew AboUniversity of California at Berkeley

Peter AbramowitzUniversity of Texas at Austin

Michael Beattie, Texas Instruments/SRC Fellow

Carnegie Mellon University

Michael BoothCornell University

Christopher BorstRensselaer Polytechnic Institute

Arthur Bradley*Auburn University

Scott Bukofsky*Yale University

Danny ChenCornell University

Jir-Shyr Chen, IBM/SRC FellowCornell University

Paul Dentinger*University of Wisconsin

Jonathan DoanStanford University

Joel Fenner, Robert M. Burger Fellow

North Carolina State University

Timothy Fisher*Cornell University

Brian Floyd, Harris/SRC FellowUniversity of Florida

David Fryer, Texas Instruments/SRC Fellow

University of Wisconsin

Glenn Glass, Motorola/SRC FellowUniversity of Illinois

Heidi GundlachUniversity at Albany, State University

of New York

Jennifer Havard, AMD/SRC Fellow*Cornell University

Noel HoilienUniversity of Minnesota

Gregg HoyerUniversity of Washington

Anna Ison, Motorola/SRC FellowUniversity of California at Berkeley

Maura JenkinsStanford University

Simon Karecki, Motorola/SRC FellowMassachusetts Institute of Technology

Norman KayUniversity of Arizona

Jean KelseyUniversity at Albany, State University

of New York

Michael KrasnickiCarnegie Mellon University

Jae-Wook LeeUniversity of California at Berkeley

Steven W. Levine*Cornell University

Aaron LilakUniversity of Florida

Derek MartinUniversity of Florida

George McMurrayUniversity of California at Berkeley

Katherine Mueller*University of Texas at Austin

James O‚KeeffeStanford University

Michael Orshansky, AMD/SRC FellowUniversity of California/Berkeley

Shipra Panda, NSC/SRC FellowCarnegie Mellon University

Michael Perkins, NIST/SRC FellowStanford University

Laura Purette, Motorola/SRC FellowMassachusetts Institute of Technology

Sriram RajamaniUniversity of California at Berkeley

Benjamin Rathsack, NSC/SRC FellowUniversity of Texas at Austin

Stefan RiegeMassachusetts Institute of Technology

Lance Robertson, IBM/SRC FellowUniversity of Florida

Eric Shero*University of Arizona

Brad ShutzbergCornell University

Jeffrey SnodgrassStanford University

Robert Sumners, AMD/SRC FellowUniversity of Texas at Austin

Dennis Sylvester University of California at Berkeley

Bassam TabbaraUniversity of California at Berkeley

Nerissa TaylorUniversity of Illinois at Urbana-Champaign

Robert ThackerUniversity of Utah

Shawn ThomasUniversity of California at Los Angeles

Peter VanDerVoorn*Cornell University

Andy WeiMassachusetts Institute of Technology

Chad WeintraubNorth Carolina State University

Heidi WitschiUniversity of Wisconsin

Xin Yi ZhangStanford University

Master’s ScholarsPaul AmpadauUniversity of Washington

Adreanne KellyLehigh University

Ronald KinderUniversity of Illinois

Francisco MachucaStanford University

Toussaint MyricksUniversity of Washington

Adrain RobinsonRensselaer Institute of Technology

Tamara TubbsGeorgia Institute of Technology

Jaimal WilliamsonGeorgia Institute of Technology

Enrique ValescoStanford University

*Graduated in 1998

Semiconductor Research Corporation 13

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Recognizing Research That Accelerates Innovation

Since its inception 1991, the SRC Technical Excellence Award has recognized 48 researchers and 14 major researchefforts whose technological contributions have significantly enhanced the productivity of the U.S. semiconductor industry.Each year a research team is chosen based on the team’s creativity and innovation, scientific merit of their research, value toindustry of the results and effectiveness of the team at technology transfer.

Technical Excellence Award

The 1997 Technical Excellence Award was pre-sented to Professor William Oldham, Dr. RichardSchenker and Mr. Fan Piao for their outstandingresearch at the University of Californiaat Berkeley on “Ultraviolet Damage toFused Silica.” Their work involvedinnovative research on new methodsof measuring optical materials com-paction and the effects of damage onlithographic performance for the 193nm regime. Prior to this work, dataon damage to fused silica at 193 nmwas either unavailable or poorlyorganized. Therefore, it was nearlyimpossible to assess the difficulty of193 nm material technology imple-mentation or its likelihood of success.Given the impending need for smallerlithographic resolution, this created aresearch dilemma for both users oflithographic exposure equipment andmanufacturers.

The information supplied by theUCB team provided key informationon the state of 193 nm technologyand facilitated cooperative interactionwith the suppliers of semiconductor equipment.Due to the extensive and high quality publicationsproduced by the research team, the results weresimple to implement and easily comprehended. Theresearch team was completely open in disclosing bothsuccesses and problems encountered throughout theprogram. It is estimated that the pace of technologyimplementation has been accelerated by 3-5 yearsbased on the team’s efforts which have made a majorimpact in our understanding of DUV optical materials.

(L-R) Dr. Richard Schenker, Professor WilliamOldham and Mr. Fan Piao display their com-memorative awards as recipients of SRC’sTechnical Excellence Award at TECHCON ’98.

14 Semiconductor Research Corporation

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The SRC Industrial Liaison Program was launched in 1983 (as the MentorProgram) to provide a formal framework for human interactions that stimulate cre-ativity and solve technical challenges. SRC Industrial Liaisons are over 500 scientists,engineers, and managers from SRC member companies who are interested in support-ing specific research tasks and actively managing and planning for the desired programresults. They provide three critical functions as part of the SRC-University-Industryteam: Research Facilitation; Technology Transfer; Student Mentoring.

Semiconductor Research Corporation 15

The SRC community recognizes the significant contributionsof Industrial Liaisons with an annual award. Six winners for the1998 Award were chosen from among the university and indus-try nominations.

Robert Aitken of Hewlett Packard worked with Professor TracyLarrabee and student, David Lavo (now of Hewlett Packard), at theUniversity of California, Santa Cruz. Professor Larrabee said “I thinkof this relationship as the very best that SRC mentorship has to offerto both the academic research program and the industrial partner.”

Laurie Beu of Motorola worked with Professor Rafael Reif of MIT.Ms. Beu was outstanding in her commitment to ensure that ProfessorReif’s work in plasma etching stays at the forefront of the industry.Ms. Beu promoted the project to other companies, opening the doorto collaborations with gas vendors and equipment manufacturers.

Martin Giles of Intel worked with Professor Mark Law at theUniversity of Florida. According to Professor Law, there is a constanttension between asking universities for fundamentally new knowl-edge while requesting a constant stream of short-term deliverablesthat are useful to industry. Dr. Giles’ approach illustrates that indus-trial mentors can help SRC reach both goals.

Effiong Ibok of Advanced Micro Devices worked with ProfessorsWortman and Hauser at North Carolina State University. Dr. Ibok pro-vided test chips and process technology information, maintained reg-ular discussions with Professors Hauser and Wortman, and arrangedtraining and instructional programs for AMD engineering staff on theuse of NCSU’s electrical characterization method.

Sungho Jin of Lucent Technologies is recognized for his work withLeon Keer’s research on interface reliability studies at NorthwesternUniversity. He encouraged ingenuity, innovation and the use of everyavailable resource to achieve research goals. Dr. Jin also providedvaluable feedback on the significance of the research in meetingindustrial needs.

Alexander Liddle of Lucent Technologies worked with ProfessorRoxann Englestad at the University of Wisconsin, Madison. Three stu-dents wrote of him, “It has been inspiring to meet a scientist withsuch technical expertise that also has a sense of humor, integrity andhonest consideration for the people with whom he works.”

Industrial Liaison Program

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Delivering Value in Information: SRC Web site - The Next Generation SRC Web site has been dramatically expand-ed in 1998 to better support the SRC community. It was redesigned to improve the integration of information about SRCand its programs into the daily workflow of personnel that can contribute to and gain value from it.

The ChallengeThe challenge faced by SRC's Web architects

was two-fold: to substantially improve value deliveryand to integrate and manage extensible informationand technology strategies targeted to meet theincreasingly more sophisticated and complex set ofuser requirements. It was equally clear that this wasfar more than the application of information tech-nologies.

An Expanded ArchitectureTo accommodate the ever-growing volume,

complexity and usage of information, the site archi-tecture had to be scalable and extensible allowingrapid response to new and changing requirements.This was tackled by addressing both the informationsystem technologies employed and the informationmanagement processes in place at SRC that collectand manage data. Efforts focused on businessprocesses, data models, implementation methodsand quality initiatives to ensure timely and accurateinformation capture, management and delivery.

New and Improved Site DesignFrom a user's perspective, the most obvious site

improvement is a completely redesigned look andfeel. With over 12,000 pages of content, it wasimperative that a more robust methodology befound for easily navigating the site. The first majorstep toward this goal was an innovative expandingand collapsing menu structure that remainsonscreen and readily accessible throughout the site.

FeaturesAs site content grew, it became increasingly

more important to make users aware of timely newcontent without forcing them to scroll or scanthrough a long list of links or search functions.Using a newspaper paradigm, SRC adopted a“Features” column on the home page that presentsthe latest headlines of SRC and each one is just aclick away from the home page.

New and Improved SearchOf course, with any large Web site, there is

always a need for a robust search capability. SRCgreatly enhanced the site search engine in threeareas. First, the Search function is now alwaysprominently displayed in the top banner of the SRCsite regardless of location. Second, an advancedSearch capability was implemented that provides afar more robust set of capabilities within subsets ofthe site. Finally, Search now integrates all site con-tent including the full content of all documents inPortable Document Format (PDF).

Secure ContentGeneral information about SRC is available to the

public without requiring a login, but the vast majorityof content on the Web site is available to personnel atmember companies or current researchers via privi-leged user accounts that require login. Until a userlogs in, this content appears “locked” and attempts toaccess it simply yield a login information screen.

User ProfilingUnlike newsletters or email, a Web site requires

that a user initiate a request for information at theWeb site. In this busy world, it would be advanta-geous to know when something of specific interest toyou became available. Starting in 1998, SRC deployedthe first phase of its user profiling capability.

Not Just About DeliveryWhile the success of the World Wide Web is

founded on rapid access to information, the Web canalso provide a ready means to collect information fromusers while maintaining a high degree of integrity andreliability in the information received. Numerous“forms” now exist on the SRC site that enable rapidcollection of data and member participation.

What the Future HoldsSRC will continue to update its Web site consis-

tent with the growth and capability of the Web andthe needs of the SRC community.

SRC Web Site – The Next Generation

16 Semiconductor Research Corporation

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Semiconductor Research Corporation 17

The Microelectronics Advanced Research Corporation (MARCO) is a wholly owned but separately managed sub-sidiary of SRC. MARCO is a not-for-profit research management organization that can manage research projects for indi-vidual customers or consortia. At the present time MARCO is managing the Focus Center Research Program (FCRP) fora consortia including semiconductor device manufacturers, and their equipment and material suppliers. The Department ofDefense is a co-participant in this program, with their management being provided by DARPA. Two Focus Centers werelaunched in 1998, with four additional Focus Centers anticipated to be started in the near future.

and organizational leadership for each Focus Centeris provided by a University Director at a lead univer-sity. Each Focus Center has a number of affiliated

universities, each with one or more asso-ciated researchers.

At the present time the FCRP man-ages two Focus Centers – one in Designand Test with lead university theUniversity of California at Berkeley, andone in Interconnect with lead universitythe Georgia Institute of Technology.The Design and Test Focus Center presentlyhas nine affiliated universities, the

Interconnect Focus Center presently has six affiliateduniversities.

The first two Focus Centers will be funded for atwo-year period, and then evaluated for progresstowards the Focus Center goals. Since two years isa short time to expect significant progress in gener-ating new concepts and radical alternatives to cur-rent methodology, the initial evaluation duringthese two years will be primarily on the process,rather than on results. The two year evaluationwill encompass progress in areas such as: generating a widely accepted long range vision for the FocusCenter; communication and synergistic perfor-mance among researchers in the Center; the avail-ability of a nurturing environment for new conceptsand radical alternatives; and the acceptance andsupport of the sponsoring companies for the FocusCenter concept.

Research funded by the FCRP is longer range(typically more than eight years out) than that fund-ed by SRC. Although both SRC and MARCO fundwork that addresses the challenges ofthe National Technology Roadmap forSemiconductors (NTRS), FCRP efforts areexpected to be multi-university withstrong emphasis on cross-fertilization ofideas during the basic research stage.The results of the FCRP are intended tobe new concepts and radical alternativesto existing methodologies that addressthe challenges of the end of the NTRSand beyond.

Basic research advances made as part of FCRPprograms may spawn proposals to SRC for researchthat addresses NTRS needs five years out andbeyond. Such research, as it in turn yields resultspertinent to solving industrial development chal-lenges, may be identified by the SRC TechnicalAdvisory Boards and industrial constituencies aspossible targets for transfer to SEMATECH or third-parties for commercialization.

The organization of the FCRP is made up offunding agencies, program management, lead uni-versities, and affiliated universities. The fundingagents are the semiconductor device manufactur-ers, represented by the Semiconductor IndustryAssociation (SIA), their material and equipmentsuppliers represented by SEMI/SEMATECH, and theDepartment of Defense represented by DARPA.MARCO and DARPA manage the FCRP under thedirection of a Governing Council made up of repre-sentatives from the funding agencies. The technical

MARCO’s Focus Center Research Program

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18 Semiconductor Research Corporation

Another value of SRC membership is protectionof technology and intellectual property assets thatare developed as a result of SRC support. SRC has aworldwide, nontransferable, royalty-free, non-exclu-sive license right to inventions and works of author-ship (e.g., software) resulting from SRC-fundedresearch. SRC sub-licenses such inventions andworks of authorship, as appropriate, to SRCMembers.

U.S. Patents which issued in 1998 includedadditions to existing technology portfolios in theareas of electromignition, design techniques forcircuit reliability, alternative device structures,metrology tools, materials and processes.

Overall, SRC added six newly issued U.S.Patents to its intellectual property portfolio, bringingthe SRC’s total number of issued U.S. Patents to156. The table on this page lists SRC U.S. Patentsissued in 1998.

Preserving Options for the Future

1998 U.S. Patents IssuedTitle Inventor Issued Patent No. University

Passivated Copper Conductor Layers William A. Lanford, 6/16/98 5,766,379 SUNY/Albanyfor Microelectronic Applications and Wei Wang, Peijun DingMethod of Manufacturing Same

Delta Doped and Counter Doped Chenming Hu, 7/14/98 5,780,899 UC/BerkeleyDynamic Treshold Voltage MOSFET Hsing-Jen Wannfor Ultra-Low Voltage Operation

Methods,Apparatus and Computer Sung-Mo Steve Kang, 8/18/98 5,796,638 UIUCProgram Products for Synthesizing Charvaka Duvvury, Carlos Integrated Circuits with Electrostatic Hernando Diaz, Sridhar Discharge Capability and Correcting RamaswarnyGround Rules Faults Therein

Methods,Apparatus and Computer Jun Ye, R. Fabian 8/25/98 5,798,947 StanfordProgram Products for Self-Calibrating Wedgewood Pease,Two-Dimensional Metrology Stages Michael T.Takac

Systems, Methods and Computer Mohamed S. Moosa, 10/13/98 5,822,218 ClemsonProgram Products for Prediction of Kelvin F. PooleDefect-Related Failures in IntegratedCircuits

Methods of Forming Polycrystalline James S. Foresi, 11/24/98 5,841,931 MITSemiconductor Waveguides for Anu M.Agarwal,Optoelectronic Integrated Circuit, Marcie R. Black,and Devices Formed Thereby Debra M. Koker,

Lionel C. Kimerling

Intellectual Property Report

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Semiconductor Research Corporation 19

To the Board of Directors of Semiconductor Research Corporation

In our opinion, the accompanying combined statements of financial position

and the related combined statements of activities and of cash flows present

fairly, in all material respects, the financial position of Semiconductor Research

Corporation (SRC) and its subsidiary at December 31, 1998 and 1997, and the

changes in their net assets and their cash flows for the years then ended, in

conformity with generally accepted accounting principles. These financial

statements are the responsibility of SRC’s management; our responsibility is to

express an opinion on these financial statements based on our audits. We con-

ducted our audits of these statements in accordance with generally accepted

auditing standards which require that we plan and perform the audit to obtain

reasonable assurance about whether the financial statements are free of mate-

rial misstatement. An audit includes examining, on a test basis, evidence sup-

porting the amounts and disclosures in the financial statements, assessing the

accounting principles used and significant estimates made by management,

and evaluating the overall financial statement presentation. We believe that

our audits provide a reasonable basis for the opinion expressed above.

PricewaterhouseCoopers LLP

Raleigh, North Carolina

March 11, 1999

Financial ReportReport of Independent

Accountants

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20 Semiconductor Research Corporation

Combined Statements of Financial Position December 31, 1998 and 1997

1998 1997

AssetsCurrent assets:

Cash and cash equivalents $ 9,591 $ 9,456Marketable securities 6,740 6,222Membership fees receivable 2,612 780Focus Center Research Program receivables - 1,194Other current assets 184 597Due from SRC Education Alliance 1 5

Total current assets 19,128 18,254

Computer and office equipment 1,100 899Furniture and fixtures 458 446

1,558 1,345Less - accumulated depreciation (1,227) (982)

331 363

Other noncurrent assets 611 534

Total assets $ 20,070 $ 19,151

Liabilities and Net AssetsCurrent liabilities:

Research contracts payable $ 12,390 $ 13,965Accounts payable and accrued expenses 724 698Deferred revenue 910 5Focus Center Research Program billings in excess of expenses - 62

Total current liabilities 14,024 14,730

Unrestricted net assets – undesignated 3,218 3,180Unrestricted net assets – designated for Research 2,828 1,241

Customization Program

Total unrestricted net assets 6,046 4,421

Total liabilities and net assets $ 20,070 $ 19,151

The accompanying notes are an integral part of these financial statements.

Financial Report

(all dollars in thousands)

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Semiconductor Research Corporation 21

Combined Statements of ActivitiesYears Ended December 31, 1998 and 1997

1998 1997Changes in unrestricted net assets:Revenue and gains:

Member fees – undesignated $ 30,956 $ 30,975Member fees – designated for Research

Customization Program 2,898 1,322Associate member fees 2,111 480Affiliate member fees 49 38Science area member fees 1,095 859Grant revenue 64 238Investment return 969 840

Total unrestricted revenues and gains 38,142 34,752

Expenses:Contract research and grants 28,058 27,659Graduate Fellowship Program 1,231 771Management and general 5,543 4,979Nonrecurring costs 43 -

Total expenses 34,875 33,409

Focus Center Research Program:Participant fees 527 1,333Contract expenses (1,332) -Management and general (837) (1,333)

Total Focus Center Research Program (1,642) -

Increase in unrestricted net assets 1,625 1,343

Net assets at beginning of year 4,421 3,078

Net assets at end of year $ 6,046 $ 4,421

The accompanying notes are an integral part of these financial statements.

(all dollars in thousands)

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22 Semiconductor Research Corporation

Combined Statements of Cash FlowsYears Ended December 31, 1998 and 1997

1998 1997Operating activities:

Change in net assets $ 1,625 $ 1,343Adjustments to reconcile change in net assets to net cash

provided (used) by operating activities:Depreciation 317 310(Gain) loss on disposal of fixed assets (3) 4Realized and change in unrealized gain (155) (103)

on marketable securities (Increase) decrease in membership fees receivable (1,832) 160Decrease (increase) in Focus Center 1,194 (928)

Research Program receivablesDecrease in receivable from SRCEA 4 -Decrease (increase) in other current assets 413 (293)Decrease in research contracts payable (1,575) (1,915)Increase in accounts payable and accrued expenses 26 212Increase (decrease) in deferred revenue 905 (1,579)(Decrease) increase in billings in excess of expenses (62) 62Increase in other noncurrent assets (77) (73)

Net cash provided (used) by operating activities 780 (2,800)

Investing activities:Purchases of fixed assets (292) (91)Proceeds from sale of fixed assets 10 3Purchases of marketable securities (3,675) (7,268)Proceeds from sale of marketable securities 3,312 6,959

Net cash used by investing activities (645) (397)

Net increase (decrease) in cash and cash equivalents 135 (3,197)

Cash and cash equivalents, beginning of year 9,456 12,653

Cash and cash equivalents, end of year $ 9,591 $ 9,456

Financial Report

The accompanying notes are an integral part of these financial statements.

(all dollars in thousands)

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Semiconductor Research Corporation 23

Notes to Combined Financial StatementsYears ended December 31, 1998 and 1997

1. Description of Organization and Summary of Significant Accounting Policies

Background and Basis of Combination – SemiconductorResearch Corporation (SRC) is a not-for-profit organization formed in1982 to conduct research in the fields of engineering and physical sci-ence related to semiconductor development and manufacture. Activityhas centered on initiation and administration of contract research withvarious institutions and universities. SRC has expended approximately$385 million since inception through December 31, 1998 relating to fel-lowships, contract research and grant expenses and industry supportactivities. SRC's charter requires that member corporations, which arecorporations involved in the manufacture, purchase, use or sale of semi-conductors or semiconductor related equipment, software and materi-als, be assessed membership fees based on a percentage of their semi-conductor sales, use or manufacture. These fees are subject to certainlimitations.

SRC has created other classes of membership which allow organiza-tions and companies otherwise not eligible for membership to joinSRC. Associate and affiliate members must undertake research anddevelopment of semiconductor devices within the United States orCanada; they have similar privileges of membership except they do nothave direct representation on the Board of Directors.

The combined financial statements include the accounts ofMicroelectronics Advanced Research Corporation (MARCO). MARCOis a not-for-profit Delaware corporation formed in 1997 to manage aU.S. university based pre-competitive Focus Center Research Program(FCRP) in semiconductor technology. MARCO has been combinedwith SRC in the accompanying financial statements because SRC main-tains control of a majority voting interest in MARCO. All significanttransactions and balances have been eliminated in combination.

Use of Estimates – The preparation of financial statements in con-formity with generally accepted accounting principles requires manage-ment to make estimates and assumptions that affect the reportedamounts of assets, liabilities, revenue and expenses and related disclo-sures. Actual results could differ from those estimates.

Cash and Cash Equivalents – Cash equivalents consist of vari-ous short-term investments which have original maturities of threemonths or less.

Marketable Securities – Marketable securities are carried at esti-mated market values based on quoted prices. Changes in the estimat-ed market value of securities are reflected as unrealized gains or loss-es in the accompanying combined statements of activities.

Computer and Office Equipment, Furniture and Fixtures –Computer and office equipment and furniture and fixtures are recordedat cost, and depreciation is calculated using the straight-line method overestimated useful lives of three to five years. For assets purchased afterJanuary 1, 1995, depreciation is calculated using a useful life of three years.

Member Fees – Revenue from full, science area, and associate mem-bers is recognized upon invoicing. Revenues from affiliate members isrecognized upon receipt as participation in the program is voluntary.

Deferred Revenue – Membership fees received in advance of theterm of the membership agreement are recorded as deferred revenue.

Grant Revenue – Revenue from unrestricted grants is recognizedupon SRC’s request for funds from the Federal agency. The requestfor reimbursement occurs subsequent to the funding of the grant orfellowship.

Contract Research and Grant Expense – Contract researchexpense is recognized ratably over the term of the contract unlessqualified costs billed by the recipient are greater than the ratableamounts; in this case the actual amount billed is recognized. Becausebillings from the recipients are typically delayed, in order to preparetimely financial statements this practice of recognizing contractexpense ratably over the term of the contract is considered toapproximate actual costs.

Included within contract research and grant expense in the accom-panying statement of activities are industry support expenses totalingapproximately $1,275 and $1,444, respectively, for the years endedDecember 31, 1998 and 1997. These expenses relate to special pro-jects undertaken by SRC and are recognized as incurred.

Unrestricted grants awarded to others are expensed at the timethe grant is awarded.

Research Customization Program – SRC has designated cer-tain assets to the Research Customization Program which com-menced in January 1997. This program allows members whose feesare $1,000 or greater to direct up to 10% of their fees to select uni-versity projects which are of particular interest to those members.

Nonrecurring Costs – Nonrecurring costs consist of expenseswhich management considers to be one-time in nature and unrelatedto SRC's normal research activities. Nonrecurring costs for the yearended December 31, 1998 include certain severance payments andlegal fees related to intellectual property issues.

MARCO – Revenue from FCRP participants is recognized uponreceipt. The contracts between MARCO and FCRP participants stipu-late that any net assets which have been accumulated by MARCO fromFCRP activities shall be returned to FCRP participants upon terminationof the FCRP. As such, any FCRP fees billed in excess of expenses arerecorded as a liability in the accompanying combined statements offinancial position.

Contract research expense is recognized ratably over the term of thecontract unless qualified costs billed by the recipient are greater thanthe ratable amounts; in this case the actual amount billed is recognized.

Income Taxes – SRC is exempt from federal income taxes underSection 501(c)(6) of the Internal Revenue Code. MARCO has notrequested tax exempt status under the Internal Revenue Code due tothe nature of its activities.

2. Marketable SecuritiesThe cost and estimated market values of marketable securities at

December 31, 1998 and 1997 are as follows.

1998 1997Estimated Estimated

Cost Mkt.Value Cost Mkt.Value

$ 4,965 $ 5,085 $ 6,160 $ 6,2221,654 1,655 – –

$ 6,619 $ 6,740 $ 6,160 $ 6,222

(all dollars in thousands)

U.S. Government obligations

Federal agency obligations

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Notes to Combined Financial Statements

24 Semiconductor Research Corporation

Years ended December 31, 1998 and 1997

The components of investment return in the accompanying statementsactivities are as follows:

1998 1997Interest income $ 858 $ 767Net realized gains 85 13Net unrealized gains 58 90Investment fees (32) (30)

$ 969 $ 840

3. Operating LeasesIn December 1995, SRC entered into a non-cancelable lease for

office space; the lease expires in September 2005 and has minimumrental payments as follows:

1999 $ 5172000 5142001 1872002 462003 and thereafter 139

1,403

Less: sublease payments 565

$ 838

Rent expense, net of sublease income, was approximately $346and $379 for 1998 and 1997, respectively.

4. Benefit PlansSRC and its subsidiary have a defined contribution retirement plan

covering all employees. Expense under this plan was approximately$351 and $290 for 1998 and 1997, respectively. SRC also has adeferred compensation plan covering all employees. Expense underthis plan was approximately $321 and $123 for 1998 and 1997,respectively.

5. CommitmentsSRC has research contracts and grant commitments outstanding of

approximately $8,830 at December 31, 1998. These commitments rep-resent active research contracts and grants entered into throughDecember 31, 1998 less expenses incurred by SRC on the related con-tracts. During the period January 1, 1999 through March 11, 1999,SRC committed to additional contracts and grants aggregating approxi-mately $8,439. SRC may, at its option, terminate any contracts andcommitments upon sixty days written notice. Termination, however,would not occur without due reason, justification and negotiation ofcontract close-out costs as well as bridging costs for SRC funded grad-uate students, as appropriate.

SRC membership agreement stipulates that full members committo financial support of SRC on a rolling three year period based on anannual fee schedule. The fee schedule stipulates that the maximumone-year decline in a member's fee shall not exceed 30%. As ofDecember 31, 1998, the minimum three year membership fee com-mitment to SRC, assuming all members' fees declined at the maximumrate of 30% per year, would be approximately $51,898.

6. Income TaxesSRC is exempt from federal income taxes under Section 501(c)(6)

of the Internal Revenue Code.As noted earlier, MARCO was incorporated in Delaware as a not-

for-profit corporation. However, due to the nature of its activities, ithas not requested tax exempt status under the Internal Revenue

Code. Income taxes are computed using the asset and liabilityapproach that requires the recognition of deferred tax assets and lia-bilities for the expected future tax consequences of events that havebeen recognized in MARCO’s financial information or tax returns. Inestimating future tax consequences, the Company generally considersall expected future events other than enactment of changes in tax lawor rates. If it is "more likely than not" that some portion or all of adeferred tax asset will not be realized, a valuation allowance isrecorded.

There is no current tax provision or benefit in any period asMARCO has generated net operating losses for income tax purposesfor which there is not carryback potential. There is no deferredincome tax provision or benefit recorded in any period as MARCO isin a net deferred tax asset position for which a full valuationallowance has been recorded due to uncertainty of realization.

At December 31, 1998 and 1997, MARCO had net operating losscarryforwards of approximately $390 and $0, respectively, expiringbeginning in 2018.

7. Related Parties

Semiconductor Industry Association (SIA) – The SIA cur-rently performs billing functions related to the FCRP. In 1997, the SIAalso performed collection functions. As such, as of December 31,1997, approximately $1,194 had been collected by the SIA from par-ticipants in the FCRP which had not been remitted to MARCO.Thisamount has been included within FCRP receivables in the accompany-ing statements of financial position.

SRC Education Alliance (SRCEA) – At December 31, 1998and 1997, $1 and $5, respectively, was due to SRC for reimbursementof costs paid by SRC on behalf of SRCEA.

SEMATECH – In 1987, SEMATECH was formed as a not-for-profitresearch organization to improve the available technology associatedwith the manufacture of semiconductors in the United States. In1988, SEMATECH and SRC entered into an agreement under whichthey will work collaboratively to identify areas of semiconductor man-ufacturing technology which could benefit from research performedby various institutions within the United States. SRC solicits propos-als for and manages these research contracts which are ultimatelyfunded by SEMATECH. In 1998 and 1997, SRC recognized revenuesof approximately $2,011 and $396, respectively, from SEMATECH asreimbursement for monies used by SRC to fund research contractsidentified under SRC's annual agreement and amendments theretowith SEMATECH.

Industrial Rebates – In 1996, SRC began utilizing personnel frommember companies to assist in program related activities. SRC paysfor these services in the form of membership fee rebates. Totalrebates for the years ended December 31, 1998 and December 31,1997 were approximately $347 and $450, respectively, and are includ-ed within contract research and grants expense in the accompanyingstatement of activities.

(all dollars in thousands)

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1998 SRC Board of Directors

George BodwayHewlett-Packard CompanyChairman

Bruce C. BurkeyEastman Kodak Company(1/98 -3/98)

Sunlin ChouIntel Corporation

Walter ClassEaton Corporation

Michael FitzpatrickNorthrop Grumman Corporation

Thomas GannonDigital Equipment Corporation(1/98 -6/98)

Sherry GillespieMotorola, Incorporated

Richard S. HillNovellus Systems, Inc.

Dyer A. MatlockHarris Corporation(1/98 -10/98)

David N. NicholsEastmen Kodak Company(3/98 - 12/98)

Yoshio NishiTexas Instruments Incorporated (12/98)

Gobi R. PadmanabhanNational Semiconductor Corporation

Mark PintoLucent Technologies

Michael PolcariIBM Corporation

Llanda RichardsonDigital Equipment Corporation(6/98 - 9/98)

Richard SchinellaLSI Logic Corporation

Ashwin ShahTexas Instruments Incorporated (1/98 -12/98)

Larry SumneySemiconductor Research Corporation

Donald WollesenAdvanced Micro Devices, Inc.

Clark McFaddenDewey BallantineCounsel

C. Mark Melliar-SmithSEMATECH ex officio

Larry SumneyPresident & CEO

Ralph K. Cavin IIIVice President, ResearchOperations

Dinesh MehtaVice President, AdministrativeOperations and Strategic Initiatives

Peter Verhofstadt*Executive Vice President, & Chief Scientist

E.D. “Sonny” Maynard*Executive Vice President, Government Affairs

1998 Office of the Chief Executive

* Co-Executive Director, MARCO

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Semiconductor Research Corporation

http://www.src.org

North CarolinaBrighton Hall, Suite 120, 1101 Slater Road

Durham, North Carolina 27703(919) 941-9400

Post Office Box 12053Research Triangle Park, North Carolina 27709-2053

California181 Metro Drive, Suite 455San Jose, California 95110

(408) 453-9460


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