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HBE-SoC-Entry II HBE-SoC-Entry II
HBE-SoC-Entry IIHBE-SoC-Entry II
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AgendaAgendaObjectivesCreating Project and ARM Stripe.H/W Design and VerificationBuild Software CodeDownload to the Target Board
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ObjectivesObjectivesCan understand and create ARM StripeBe aware of AHB Bus InterconnectionCan verify ARM-Based H/W systemHow to develop Embedded SoftwareConfigure Target Excalibur DeviceDo Debug Embedded SoftwareManage Development Tools
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RequirementsRequirementsAltera Quartus II IDE v3.0(or later)Mentor Graphics ModelSim v5.7(or later)ARM Development Suite v1.1(or later)ARM-Based Excalibur Entry II PlatformOptional− GNUpro GCC C Compiler for ARM − Multi-ICE for ARM Debugging− Other EDA Synthesis or Simulator
Create ProjectCreate Project
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Start Quartus IIStart Quartus IILaunch Quartus II (Desktop Icon)
Navigation Window
Process Window
Messege Window
Workspace
Menu Bar
Tool Bar
Status Bar
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Create New ProjectCreate New ProjectFile > New Project Wizard … Click
Click
Click
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Specify Project NameSpecify Project NameFolder : DemoName : DemoTop-Level : Demo Specify user own folder
1
Click
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Add Other FilesAdd Other FilesBypass this step by click “Next” 2
Click
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EDA SettingsEDA SettingsBypass this step by click “Next”We will use later
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Click
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Device SelectDevice SelectExcaliburEPXA4F672C3
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Click
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Summary and FinishSummary and Finish
Project folderProject nameTop-level entity name
Target Device
Click
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DoneDone
Project name is displayed
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MegaWizard Plug-In Manager :Create ARM StripeMegaWizard Plug-In Manager :Create ARM Stripe
Tools > MegaWizard .. Click
Click
Click
Click
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ARM-Based ExcaliburARM-Based ExcaliburMegafunction : ARM-Based ExcaliburOutput file : VHDLOutput file : stripe.vhd Click Click
File name
Click
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System SettingSystem SettingDevice Selection− Excalibur_ARM− EPXA4
Reset Operation− Boot from Flash
Byte Order− Little Endian
Reserve Pins− EBI Automatically
Enabled− Enable UART Pins− Disable Trace Pins
Click
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Stripe-to-PLD InterfaceStripe-to-PLD InterfaceBridges− Stripe-to-PLD
Interrupts− None
Trace/Debug− Disable Trace
Extensions
Click
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ClocksClocksClk_ref− 25 MHz
AHB1/AHB2− Enable PLL1− AHB1: 133 MHz− AHB2: 62.5 MHz
SDRAM Controller− Enable PLL2− 133MHz
Serial Programming− Enable But Not Used
Click
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Memory MapMemory MapRegisters− Default: 0x7FFFC000; 16K
SRAM0 : OFFSRAM1 : OFFDPRAM0 : OFFDPRAM1: OFFSDRAM0 :− 0x00000000; 64M; 32bit
SDRAM1 : OFFEBI0− 0x40000000; 16M
EBI1, EBI2, EBI3: OFFPLD0− 80000000; 2G
PLD1, PLD2, PLD3: OFF Click
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EBI0 SettingsEBI0 SettingsSynchronousWait Cycles: 8CS Polarity: Active LowData Width: 16 BitsBus Clock Divide: 1
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SDRAM SettingsSDRAM Settings
Click
Click
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Output File SummaryOutput File SummaryDisplay file to create
Click
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Browse project folderBrowse project folderThere are some files generated by Quartus II
Generated files by Quartus II MegaWizard
H/W Design OverviewH/W Design Overview
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Top-Level DesignTop-Level Design
Stripe.bsfStripe.vhd
Single_transaction_slave.bsfSingle_transaction_slave.vhd
Regfile.bsfRegfile.vhd
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File DescriptionFile DescriptionStripe.vhd− ARM Stripe Entity through MegaWizard
Single_transaction_slave.vhd− Single transaction AHB slave
Regfile.vhd− Back-end logic latch interface with Physical H/W
H/W DesignH/W Design
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Begin New H/W DesignBegin New H/W DesignFile > New … ClickBlock Diagram/schematic File select -> OK click
Click
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Save file as DemoSave file as DemoSave Blank Block file as Top-Level Entity Demo
Click
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Add two Design fileAdd two Design fileMenu Assignment > Settings .. ClickAdd Hw_design\rtl\single_transaction_slave.vhd to the projectAdd Hw_design\rtl\regfile.vhd to project
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Generate Block SymbolGenerate Block SymbolMove Navigation Window > Files TabTwo Design files are existClick one file and Click Mouse right-buttonSelect “Create Symbol File..” in the Pop-up MenuCreate the other file’s symbol tooTwo Symbols are made in project folder
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InstantiationInstantiationMenu Edit > Insert Symbol … Click or Double-Click on the Blank Block/Schematic Empty spaceCan see Symbol Window
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InstantiationInstantiationLoad Two Design Symbol file to the Top-level Block/schematic Design file Also Load Stripe Design Symbol file generated by MegaWizard to the Top-level Block/schematic Design fileLoad ARM Stripe SymbolArrange Symbols properly
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Load CompleteLoad Complete
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Port Map/Specify Input/OutputPort Map/Specify Input/OutputLoad Symbol window on Menu Edit > Symbol ..Add Input/Output/BidirSymbol
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Connecting SymbolsConnecting SymbolsConnect ARM Stripe Reserved Pin to Pin SymbolSpecify Pin Name
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Connecting Master PortConnecting Master PortDraw Net for ARM Stripe Master Port with Draw ToolSpecify Signal Name with Double-Click the Net
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Connecting AHB SlaveConnecting AHB SlaveDraw Net for AHB Slave to Connecting with ARM Stripe Master PortSpecify Signal Name with Double-Click on the Net
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Connecting Back-end LogicConnecting Back-end LogicDraw Net for Register file to Connecting with AHB Slave InterfaceSpecify Signal Name with Double-Click on the Net
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Clock/Reset/EtcClock/Reset/EtcAdd Clock Input PinAdd Reset Input PinAdd LED Output Pin SymbolDraw Net and Name it
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Design CompletionDesign Completion
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Check DesignCheck DesignMenu Processing > Start > Start Analysis & Synthesis ClickWill check syntax and errors
SimulationSimulation
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RequirementsRequirementsModelSim v5.7(or later)Exc_bus_translate.exeDesign filesInput.datMastercommand.dataltera_mf.vhdaltera_mf_components.vhdALT_EXC_STRIPE.VHDALT_EXC_STRIPE_ARCH_BFM.VHD
<Quartus_Install folder>\eda\sim_lib
<Quartus_Install folder>\eda\sim_lib\excalibur\lpm
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Create Top-level EntityCreate Top-level EntityBefore verification, Should create Top-design in Qaurtus IIMenu File > Create/Update > Create HDL File … ClickCreate Top-level Entity “Demo.vhd” Click OKModelSim Can’t Read Altera Quartus demo.bdf
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Run ModelSimRun ModelSimRun ModelSim ProgramCreate ProjectFile > New > Project ClickProject Name− Demo
Project Location− Modelsim_project
Default Library Name− work
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Add Files to simulateAdd Files to simulateAdd files to ModelSim after project settingTop-level DesignSub-module DesignAltera Bus Model LibsARM Stripe
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Build ErrorBuild ErrorAfter input All files and then Build AllMenu Compile > Build AllBut Maybe Error is occurred
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Successfully BuildSuccessfully BuildSelect altera_mf.vhd and Right-Mouse Button ClickSelect Type vlib altera_mf <enter>Type vmap altera_mf work <enter>Build All again
Click
Click
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Bus Command Language FileBus Command Language FileINPUT.DAT
idle(4);
write (0x80000004, 32, 1, 0xA);write (0x80000008, 32, 1, 3);write (0x8000000c, 32, 1, 5);
write (0x80000004, 32, 1, 0xC);write (0x80000008, 32, 1, 4);read (0x8000000c, 32, 1);
write (0x80000004, 32, 1, 0x9502);write (0x80000008, 32, 1, 5);write (0x8000000c, 32, 1, 7);read (0x80000004, 32, 1);read (0x80000008, 32, 1);
/*INCR Burst test*/write (0x80000004, 32, 3, 9 ,6, 5);read (0x80000010, 32, 1);
/*Error Checking test*/write (0x80000010, 32, 1, 10);read (0x80000010, 32, 1);read (0x80000010, 16, 1); read (0x80000018, 32, 1);
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Exc_bus_translate.extExc_bus_translate.extExc_bus_translate.exe <input> <output>Converts Bus transaction into Bus controlEx> Exc_bus_translate input.dat <enter>
exc_bus_translate.exe
input.dat
mastercommands.dat
Convert
Bus Transaction File
Bus Control File
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Mastercommand.datMastercommand.dat///////////////////////////////////////////////////////////////////////////////////////////////// Altera upCore Bus Transaction Simulator Master Port Command File//// mastercommands.dat//// This file is interpretted by apex20ke_atoms.v to simulate the issueing of read/write // instructions to the PLD by the microprocessor via the AHB3 master interface//// NB Only data, transaction and repeat fields are tested during the // data beats of burst transactions/////////////////////////////////////////////////////////////////////////////////////////////////// FORMAT// / __________________________________| reserved (0000)/// ///| | ++++++++++++++++++++++++++++++++++ valid transaction 1=USE BUS 0=SILENT//| |+ _______________________________//| |+ / _________________________| address //| |+/ ///| |+| | +++++++++++++++++++++++++ write 1=WRITE 0=READ//| |+| |+ _______________________ //| |+| |+ / _______________| write data / expected read data//| |+| |+/ ///| |+| |+| | ++++++++++++++++ reserved (0) (1=>lock)//| |+| |+| |+//| |+| |+| |+ /-------------- reserved (0) (1=>check read data)//| |+| |+| |+///| |+| |+| |+| ************** transaction 0=IDLE, 1=BUSY, 2=NONSEQ, 3=SEQ//| |+| |+| |+|*//| |+| |+| |+|* /------------ reserved (0)
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Simulation – Load designSimulation – Load designMenu Simulate … > Simulate .. ClickSelect “Demo” in DesignClick OKModel Prompt changes to Simulation Mode VSIM>
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Simulation – Input StimulusSimulation – Input StimulusType below in the ModelSim Command WindowView wave <enter>Add wave * <enter>Delete some useless signals if waveform is displayed.− Clk_ref, sdram*, ebi*, uart* etc.
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Simulation - WaveformSimulation - Waveform
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Simulation – Input vectorSimulation – Input vectorType below in the ModelSim Command Window− Force pld 0 0, 1 10ns –repeat 20ns− Force reset_slave 1 0, 0 100ns− Run 1050ns
And then observe the waveform windowDoes it work well? Yes or No.
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Simulation - DoneSimulation - Done
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Output.datOutput.datMASTER: trans=[ 2] addr=[80000004] WRITE data=[0000000A] expected=[0000000A] WORD OKAY MASTER: trans=[ 3] addr=[80000008] WRITE data=[00000003] expected=[00000003] WORD OKAY MASTER: trans=[ 4] addr=[8000000C] WRITE data=[00000005] expected=[00000005] WORD OKAY MASTER: trans=[ 5] addr=[80000004] WRITE data=[0000000C] expected=[0000000C] WORD OKAY MASTER: trans=[ 6] addr=[80000008] WRITE data=[00000004] expected=[00000004] WORD OKAY MASTER: trans=[ 7] addr=[8000000C] READ data=[00000004] expected=[00000000] WORD OKAY MASTER: trans=[ 8] addr=[80000004] WRITE data=[00009502] expected=[00009502] WORD OKAY MASTER: trans=[ 9] addr=[80000008] WRITE data=[00000005] expected=[00000005] WORD OKAY MASTER: trans=[ 10] addr=[8000000C] WRITE data=[00000007] expected=[00000007] WORD OKAY MASTER: trans=[ 11] addr=[80000004] READ data=[00000007] expected=[00000000] WORD OKAY MASTER: trans=[ 12] addr=[80000008] READ data=[00000007] expected=[00000000] WORD OKAY MASTER: trans=[ 13] addr=[80000004] WRITE data=[00000009] expected=[00000009] WORD OKAY MASTER: trans=[ 14] addr=[80000008] WRITE data=[00000006] expected=[00000006] WORD OKAY MASTER: trans=[ 15] addr=[8000000C] WRITE data=[00000005] expected=[00000005] WORD OKAY MASTER: trans=[ 16] addr=[80000010] READ data=[00000009] expected=[00000000] WORD OKAY MASTER: trans=[ 17] addr=[80000010] WRITE data=[0000000A] expected=[0000000A] WORD OKAY MASTER: trans=[ 18] addr=[80000010] READ data=[0000000A] expected=[00000000] WORD OKAY MASTER: trans=[ 19] addr=[80000010] READ data=[0000000A] expected=[00000000] HALF WORD ERROR
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Timing SimulationTiming Simulation
Apex20ke_atoms.vhd : Altera LibApex20ke_components.vhd : Altera LibDemo.vho : Top-level Designdemo_modelsim.xrf : EDA Tool Settingdemo_vhd.sdo : EDA Tool Setting
Quartus II > EDA Tools > Simulation > ModelSim(VHDL)<Project folder>\simulation\modelsim
<Quartus_Install folder>\eda\sim_lib
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Timing SimulationTiming Simulation
Place and RoutePlace and Route
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Pin FittingPin FittingReturn to Quartus IIAssignments > Assignment Editor ClickAdd PLD SignalAdd Reset_slave SignalAdd USER_LED[15:0] Signal
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Pin AssignmentsPin AssignmentsClick
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Complete H/W DesignComplete H/W DesignTool > Processing > Start Compilation Click
Embedded SoftwareEmbedded Software
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Design Flow : Boot from FlashDesign Flow : Boot from Flash
Parse .sbd File& Convert
User’s HardwareDesign Entry
Quartus II Software
User’s SoftwareDesign Entry
Compile, Link
.rtl File .h File
.hex File
.sbd File
.sbi File
ExcaliburMegaWizard Plug-In
Link & Convert Object File to .hex
Boot Loader
.hex File
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Software filesSoftware filesArmc_startup.sRetarget.cIrq.cUartcomm.cIrq.cMain.c
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Add filesAdd filesIn Quartus II, Add software file to projectMenu Project > Add/Remove files in …Click
Click
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Software Build SettingSoftware Build SettingMenu Assignment > Wizard or Settings Click
Click
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Software Build SettingSoftware Build SettingEmbedded processor− ARM922T
Software Toolset− ADS Standard Tools
Click
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Software Build SettingSoftware Build SettingByte order− Little endian
Output file format− Hexadecimal (.hex)
File name− Demo.hex
Click
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Software Build SettingSoftware Build SettingSelect “Create a file that allows the device to be configured from flash memory”Type “Demo.sbi”And the click “Next”
Click
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Software Build SettingSoftware Build SettingOnly C/C++ header path− Type “.,../common “
And click “Next” for the Next step
Click
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Software Build SettingSoftware Build SettingAssembler setting page− Type only “.”− Indicate current project
folder
Click
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Software Build SettingSoftware Build SettingLinker settings− Entry address : 0x0− Read-only : 0x0− R/W address : 0x2000
Additional Link option− -first armc_startup.o(init)
And Then Click “Next”
Click
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Software Build SettingSoftware Build SettingLate page of SettingsJust click “Finish”
Click
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Compile Software CodeCompile Software CodeProcessing Menu Start Software Build− Demo_flash.hex
Application Application CodeCode
PLD ImagePLD Image
Flash Flash Programming Programming
FileFile
Demo.hexDemo.sbi
Demo_flash.hex
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ARM Development SuiteARM Development SuiteANSI C Compilers: armcc & tccISO/Embedded C++ Compilers: armcpp & tcppARM/Thumb Assembler: armasmLinker: armlinkDebugger: AXDFormat Converter: fromelfLibrarian: armarC & C++ Libraries
DownloadDownload
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Exc_flash_programmerExc_flash_programmerRun Dos Command WindowTo download image file − Type “Exc_flash_programmer –p –v –g
demo_flash.hex” <enter>
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DownloadDownload
Batch file
Flash utility
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SummarySummaryCreate project and H/W designVerify H/W design with BFMPlacement and RouteEmbedded SoftwareDownload
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