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STT-MRAM as a non-volatile memory (NVM) technology offeringSTT-MRAM is production ready and currently sampling to customers
Advantages of STT-MRAM
- Non-volatile & low power
- Fast write speeds (tpulse < 10 ns)
- Endurance > 109 cycles
IEDM 2019 IEDM 2019 IEDM 2020
STT-MRAM state-of-the-art☺
High performance
compute
BEOL
compatibility Scalablity
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Embedded electronics – Driven by memory, limited by power
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Market forecasts predict extensive application range for STT-MRAM
Courtesy Yole development
Courtesy: IBM
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Why is STT-MRAM the most promising emerging NVM?
▪ Many potential benefits – fast R/W times (1 – 10 ns), low power operation, large endurance* (~1015 cycles)..
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Esw = 0.12 pJ @ 1ppm
G. Jan et al., VLSI 2018 J. J. Kan et al., IEDM 2016S. Sakhare et al., IEDM 2018
H. Noguchi et al., ISSCC 2016
Endurance at RT Area savings over SRAM
Low power, high
speed operation High endurance Dense structure, small footprint
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STT-MRAM technology development driven by application domain
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Requirements
- Low power (Jsw < 5 MA/cm2)
- High speed (toper < 10 ns)
- WER > 1e-6
- 10 years retention (-40 C to +85 C)
High performance computingExamples: LLC, SoC
Requirements
- High density (pitch = 50 nm)
- Low power (Jsw < 1 MA/cm2)
- Relaxed speed (toper ~ 50 ns)
- WER ~ 1e-6
- 10 years retention (-40 C to +125 C)
Low power computing Examples: eFLASH replacement, Edge IoT
Fundamentals of Magnetoresistive RAM (MRAM)
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MRAM – Fundamentals
▪ Memory – 2 distinct states; decided by relative orientation of ferromagnetic layers
▪ Read - current sensing through magnetic tunnel junction (MTJ); TMR effects modulates readout signal
▪ Write – multiple write schemes dependent on MRAM flavour (current-driven or E field-driven)
▪ Mechanism – Generator of spin torques, followed by angular momentum transfer for magnetization reversal
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What is an MRAM device?
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i e-
Free layerFerromagnet can freely rotate
Pinned layerFerromagnet cannot rotate
Insulating barrier
Magnetic tunnel junction
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Write operation
▪ Write – tunneling electrons (s) transfer spin angular momentum to bound electrons (d,f)
▪ Magnetization experiences torque from transverse component only
▪ Magnetization reversal dynamics described by Landau-Lifshitz-Gilbert-Slonczweski (LLGS) equation
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Spin Transfer Torque (STT) enables magnetization reversal
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precession damping Spin torque
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Evolution of MTJ design
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Perpendicular magnetic anisotropy (PMA)
Magnetic anisotropy – preferred orientation of material magnetization
𝐾𝑒𝑓𝑓 = 𝐾𝑐𝑟𝑦𝑠𝑡𝑎𝑙 + 𝐾𝑠ℎ𝑎𝑝𝑒 + 𝐾𝑖𝑛𝑡/𝑡 + 𝐾𝑠𝑡𝑟𝑒𝑠𝑠
Energy cost of overcoming
demagnetization PMA systems – energy efficient and scalable!
A.V. Khvalkovskiy et al., Jour. Appl. Phys. D 46, 074001 (2013)
# Description
Ms Saturation magnetization (FL)
Hk Magnetic anisotropy field (FL)
Damping constant
Spin polarization
t Thickness
Jc0 Critical switching current density
Technology parameters of switching FL
Cost of writing information
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Integration process for high performance, high density STT-MRAM
▪ Annealing of film stack required for optimal crystallization and TMR
▪ End-of-line (EOL) anneals are challenging to stability of full MTJ stack
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1x integration scheme enables costs benefits and higher cell densities
EO
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ield
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me
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Process flow
(c)Cross-section(b)
M4
M3
MTJ
TEM of integrated MTJ bit-cellFront-end up
to target metal
Bottom electrode
MTJ module
MTJ deposition
Patterning + anneal
Top contact module
Passivation
EOL field
(a)
Pro
cess f
low
Pro
cess Flow
Baseline 400 C BP stackRA = 4.5 W.m2, TMR = 160%
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Challenges to market adoption - Defects
▪ MTJ defect study an active area of research → not a simple resistor!
▪ Device-aware test approach needed for failure mitigation & process optimization
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Defect zoology in the MRAM process flow
Front-end up
to target metal
Bottom electrode
MTJ module
MTJ deposition
Patterning + anneal
Top contact module
Passivation
EOL field
(a)
Pro
cess f
low
Pro
cess Flow
L. Wu et al., TETC 2019
STT-MRAM as eSRAM replacement- Challenges & mitigation strategies
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WER target (for LLCs) 1e-9 cycles
Challenge 1 – Achieving BEOL compatibility
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BEOL thermal budget leads to magnetic layer degradation and yield reduction
TMR (%)
Cou
nt
Tail bits
Tail bits cause WER widening
➢ Increased write power
➢ Increased reliability issues
Tail bits in dense arrays
TMR distribution in 1 MB STT-MRAM array
Jc
(a.u
.)
Electrical CD (nm)
tPW = 5 ns
BEOL challenge (400 C, >90 min)
Penalty in data retention ( Hk)
Increased
write
latency
High bias WER increase
G. Jan et al., VLSI 2018
▪ Largely solved by annealing MTJ prior to patterning step to enable optimal bcc (100) crystallization
▪ Incorporation of increased B % in magnetic layers enables delayed crystallization; ensures higher thermal budget!
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Challenge 2 – Backhopping in reference layer (RL)
▪ Unintended reversal of RL under influence of STT
leads to data corruption.
▪ Patterning-induced Hk loss in RL leads to reduced
Eb (constant FL, RL switching).
▪ Mitigation: Increase RL PMA, and pinning with SAF
(HL layer)
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Backhopping leading to WER increase
W. Kim et al., IEEE Trans. Magn. (2016)
WE
R
tPW = 5 ns tPW = 10 ns tPW = 50 ns
Jpulse (MA/cm2) Jpulse (MA/cm2) Jpulse (MA/cm2)
WE
R
tPW = 5 ns tPW = 10 ns tPW = 50 ns
Jpulse (MA/cm2) Jpulse (MA/cm2) Jpulse (MA/cm2)
WE
R
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Challenge 3 – Write power reduction and scalability
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Data retention
() 10 yrs
Stack engineering (Ku, Ms,...)
Patterning challenges
Need for a new FL design beyond conventional CoFeB/MgO interfaces
~ (60 – 90) in operating T rangeChallenge. Linear -Ic relation results in higher write power
Solder reflow challenge
- addressed by Hk engineering,
- though Ic increases also
Random fluctuations of magnetization
Not a memory anymore!
Materials innovation
Challenge. Materials engineering limited by TMR–-Ic tradeoff
Hk → Hc → Eb → Increased power consumption!
Single domain onset (Dsd) pushed to smaller sizes...
Property degradation
Challenge. Increase in
PID with reduced CD.
Switching efficiency
drops.
Fundamental limit!
CD reduction →
Ic reduction
=𝐸𝑏𝑘𝐵𝑇
=𝐾𝑢𝑉
𝑘𝐵𝑇=𝑀𝑠𝐻𝑘𝑉
2𝑘𝐵𝑇
Data retention
Glossary
Eb – energy barrier (in kT)
Ms – saturation magnetization (in A/m)
Hk – magnetic anisotropy field (in T)
PID – patterning-induced damage
Hc
(mT
)
Size (nm)
Switching current
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Challenge 4 – Addressing process variability
Key challenge for market adoption – Can we address MTJ damage control in dense arrays?
Process-induced damage broadens distributions; pose manufacturability concerns
J. G. Alzate et al., IEDM 2019
S. Rao et al., ICM 2018
2.5x
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Observed trends of variability Modelling Experimental confirmation
40% improvement!
CD = 60 nm
SIDDHARTH RAO SIDDHARTH RAO
Patterning of MTJ nanopillar devices
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MRAM device
300mm wafer
Main etch (ME)
Over-etch (OE)
A primer
▪ MTJ patterning – Ion-beam etch (IBE) using a 2-step etching mechanism
▪ Over-etch step is necessary to clean re-deposited metallic sidewalls to avoid device shorts.
▪ Post-etch treatment (ie: oxygen treatment) necessary to render sidewalls electrically inactive
Expected damage profile
Damage region with gradual
variation in device parameters
SIDDHARTH RAO
GRADIENT
𝑅𝐴2 𝑒𝑥𝑡𝑒𝑛𝑑𝑠 𝑓𝑟𝑜𝑚 𝑅𝐴1 (𝑎𝑡 𝐶𝐷𝑚𝑖𝑛) 𝑡𝑜 ∞ (𝑎𝑡 𝐶𝐷1)
At the absolute centre,
RAdevice = RAminimal
Pri
stin
e Z
one
(R1)
Dam
aged r
egi
on
(R2)
A process-aware damage model
Ideal scenario of damage
Process-agnostic modelRealistic scenario of damage
Process-aware model
𝑅𝐴2 = (𝑅𝐴1 × 𝐴2 × 𝑅𝐴1+2)
( 𝐴1+2 × 𝑅𝐴1 − (𝐴1 × 𝑅𝐴1+2))
𝐴𝑡, 𝐴1+2 × 𝑅𝐴1 = 𝐴1 × 𝑅𝐴1+2 −−→ 𝑅𝐴2 = ∞
RA Trends in damaged region
SIDDHARTH RAO SIDDHARTH RAO
Using PID quantification for process optimization
▪ 5 samples with varying main etch (ME) and over etch (OE) energies were compared.
▪ A gentler sidewall clean results in a more shallow penetration of the etch ions.
▪ Steeper TMR drop profile with decreasing OE energy also suggests lesser damage.
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A)
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Experimental results validate model!!
S. Rao et al., ICM 2018
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Electrical validation on 1 Mbit STT-MRAM arrayOptimized process achieves 99.5% yield, 20% Ewrite reduction and 30% Vwrite reduction
At 200 MHz
R/W performance improvement
Tighter Vwrite distributions
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No tail signature
with optimized etch!
Improved reliability
Optimized etch achieves targeted endurance specs
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S. Rao et al., IMW 2021
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Summary
▪ STT-MRAM technology – an ‘ideal’ NVM embedded memory solution
▪ Offers low leakage, low power, low write latency and is a scalable solution
▪ WER < 1 ppm and endurance > 1012 cycles demonstrated on prototype vehicles
▪ Currently available in market as eFLASH replacement for embedded applications
▪ For HPC such as LLC (eSRAM replacement), some challenges remain
▪ BEOL compatibility (400 C anneals) has been demonstrated in several recent reports
▪ Write power consumption remains higher than SRAM → breakthrough required in materials
▪ Write efficiency hampered by scaling; attributed to increasing patterning-induced damage
▪ Post-patterning treatments can enable improved device performance
▪ Need for more modelling insight into processes → ML-driven can be an interesting approach
▪ All major foundries now sampling STT-MRAM for HPC and LP applications!
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STT-MRAM is a mature technology, but some challenges for widespread adoption remain
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