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STT-RAM Generator
- Anurag Nigam
Motivation
Challenges in SRAM High Leakage
Solution Non-volatile
memory
Leakage current
Memory Technology Comparison
STT-RAM bit cell overview
MTJ
WL
SL
BL
Oxide layer
Free Ferro magnetic layerRPRAP
Hard Ferro magnetic layer
MTJ
1 MTJ 1 access transistor
Bit-cell Design IMTJ = f (Vin, parameters) Behavioral current source Need to solve differential equation How to solve differential
equation ??
Capacitor current equation
I = C dV/dt
I C
V
dtCIV /
Bit-cell design
Editing CDF parameter to create behavioral source
componentName = isourceI = f(V)
Bit-cell design
Schematic Write “1” Operation
WL BL=0V
SL=1V
Switching
Memory Interface
Write Driver
Timing Block
Sensing Block
Memory Array
WLen
SAen
CLK
Data In
Data Out
R/W
ADDR
R/W
CL
WLS
Data In
CLK
R’/W
ADDR
Data Out
STT-RAM Macro
Write Driver
Write “1” BL =0 SL=1 Write “0” BL=1 SL=0
TBUF
TBUF
BL
SL
Sense amplifier design
Test bit-cell
R-V characteristic of MTJ
Two states (RAP and RP) Resistance is a function of voltage
-1.5 -1 -0.5 0 0.5 1 1.50
2000
4000
6000
80007000
5000
3000
1000
Applied Voltage (V)
R (
)
RAP
RP
Schematic automation Leaf-cell schematic creation
Bitcells – Manual (using current/voltage sources)
Decoders – Skill Sense amp. Timing block, Write driver
– Manual Memory array creation
1Kb array - Skill
Schematic automation Decoderprocedure(Create7to128DecoderSchematic(libname,cellna
me)) Write Driverprocedure(CreateWriteDrSchematic(libname,cellname,C)) Memory Arrayprocedure(CreateSTTRAMSchematic(libname,cellname,R,C
))
1Kb STT-RAM array
Timing block
128 x 8 array
Write Driver
Sense amplifier
Read and Write operation
clkData<0> Out<0>
Write “1” Read “1”
Write “0” Read ”0”
Deliverables STT-RAM bit-cell SPICE model Skill script to generate complete
functional STT-RAM Class-specific work
Importing bit-cell model in ADE Skill script development
Thanks for your time !