2004/12/23 1

Techniques for and DSP Software Implementation of IEEE 802.16a TDD OFDMA Downlink Pilot-Symbol-Aided Channel Estimation

Student: Chen, Ching

Advisor: Prof. D. W. Lin

Time: 2005/6/1

2004/12/23 2

Outline

Review of frequency and time domain interpolation approaches Frequency: Linear and 2nd-order interpolation Time: 2-D interpolation

Simulation results DSP code acceleration Conclusion & future work Reference

2004/12/23 3

LS Estimator LS estimation objective

Channel matrix considering pilot carriers only:

The Transform can reformulated :

LS estimator

2||ˆ|| XHY LS

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Interpolation in Frequency domain Linear Interpolation The need for interpolation Mathematical expression:

Example

2004/12/23 5

Interpolation in Frequency domain Second-Order Interpolation Mathematical expression:

Example

2004/12/23 6

Interpolation in Time domain 2-D InterpolationWe have pilots

to do interpolation.

568324)8142(4)( tsFixLocPilosPilotsCoincidenttsVarLocPilo NNN

2004/12/23 7

Interpolation in Time domain 2-D Interpolation Using previous symbol information

with 2 kinds of formulas :

(1) Formula 1:

(2) Formular 2:

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ppppformulaDsets

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pppformulaDsets

2004/12/23 8

Channel Model

ATTC (Advanced Television Technology Center) and the Grande Alliance DTV Laboratory’s ensemble E model:

6-tap multi-path channel:

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Simulation on Static Channel Comparison between 1st and 2nd formulas by using linear interpolation

MSE SER

2004/12/23 10

Simulation on Static Channel Comparison between 1st and 2nd formulas by using 2nd-order interpolation

MSE SER

2004/12/23 11

Simulation on Static Channel Comparison between linear and 2nd-order interpolation by using 1st formula.

MSE SER

2004/12/23 12

Simulation on Static Channel Comparison between linear and 2nd-order interpolation by using 2nd formula.

MSE SER

2004/12/23 13

Simulation on Rayleigh Fading Channel fdT=0.01, V=27km/h Comparison between linear and 2nd-order interpolation by using 2nd formula.

MSE SER

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Simulation on Rayleigh Fading Channel fdT=0.02, V=54km/h Comparison between linear and 2nd-order interpolation by using 2nd formula.

MSE SER

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Summation

1st formula works better than 2nd one when suffering static channel condition.

Linear interpolation performs almost the same with 2nd-order one on static channel but better on rayleigh fading channel .

Besides, it is of low complexity.

2004/12/23 16

DSP Acceleration

Data type modification. Using intrinsic functions. Coding style optimization.

2004/12/23 17

Different Data Types Simulation ResultsFloating-point v.s. Fixed-point 32 bits

Function

Name

Floating-point

Code size

(Bytes)

Floating-point

ExecutetionCycles

Fixed-point

32bits

Code size

(Bytes)

Fixed-point

32bits

Executetion Cycles

Improve-ment

Complex_Multiplier 284 899,603 484 88,513 90.16%

Complex_Divier 404 1,900,051 440 688,850 63.75%

Linear_Interpolation 548 579,794 632 441,423 23.87%

64QAM 580 92,169 456 104,458 -13.33%

De-64QAM 2472 1,305,239 1088 225,016 82.76%

2004/12/23 18

Different Data Types Simulation ResultsFixed-point 32 bits v.s. Fixed-point 16 bits

Function

Name

Fixed-point

32bits

Code size

(Bytes)

Fixed-point

32bitsExecutetion Cycles

Fixed-point

16bits

Code size

(Bytes)

Fixed-point

16bits

Executetion Cycles

Improve-ment

Complex_Multiplier 484 88,513 324 71,493 19.23%

Complex_Divier 440 688,850 280 283,122 58.89%

Linear_Interpolation 632 441,423 356 139,365 68.43%

64QAM 456 104,458 440 104,458 0%

De-64QAM 1088 225,016 1076 224,055 0.4%

2004/12/23 19

Different Coding Style Simulation Results

Function

Name

Fixed-point

16bits

Code size

(Bytes)

Before

Fixed-point

16bitsExecutetion Cycles

Before

Fixed-point

16bits

Code size

(Bytes)

After

Fixed-point

16bits

Executetion Cycles

After

Improve-ment

Complex_Multiplier 324 71,493 488 7,686 89.25%

Complex_Divier 280 283,122 348 201,427 28.86%

Linear_Interpolation 356 139,365 308 132,442 4.97%

64QAM 440 104,458 404 104,458 0%

De-64QAM 1076 224,055 1052 218,894 2.3%

2004/12/23 20

Using Intrinsic Functions

For TI C6000 DSP Special functions which have best optimized assembly code on

the TI DSP architecture

(1)_amemd8_const: Allows aligned loads of 8 bytes to memory.

2004/12/23 21

Using Intrinsic Functions

(2)_dotp2 & _dotpn2: Works for complex multiplier.

(3)_add2: 32 bits adder .

2004/12/23 22

Simulation Results by Using Intrinsic Functions

Function

Name

Fixed-point

16bits

Code size

(Bytes)

Before

Fixed-point

16bitsExecutetion Cycles

Before

Fixed-point

16bits

Code size

(Bytes)

After

Fixed-point

16bits

Executetion Cycles

After

Improve-ment

Complex_Multiplier 488 7,686 268 3,426 55.42%

Complex_Divier 348 201,427 428 193,764 3.8%

Linear_Interpolation 308 132,442 308 132,442 0%

64QAM 404 104,458 404 104,458 0%

De-64QAM 1052 218,894 1052 218,894 0%

2004/12/23 23

Different Coding Style Simulation Results(Interpolation, De-QAM)

Function

Name

Fixed-point

16bits

Code size

(Bytes)

Before

Fixed-point

16bitsExecutetion Cycles

Before

Fixed-point

16bits

Code size

(Bytes)

After

Fixed-point

16bits

Executetion Cycles

After

Improve-ment

Complex_Multiplier 268 3426 272 3421 0%

Complex_Divier 428 193,764 428 162,960 15.89%

Linear_Interpolation 308 132,442 332 74,066 44.08%

64QAM 404 104,458 396 101,308 3.02%

De-64QAM 1052 218,894 1068 148,169 32.31%

2004/12/23 24

Performance Comparison between Floating-point and Fixed-point version

MSE SER

2004/12/23 25

Future Work

More optimization of DSP code.

2004/12/23 26

Reference Chen, Ying Ying , “Study and Techniques of IEE

E 802.16a TDD OFDMA Downlink Channel Estimation,” June 2004

Texas Instrument, TMS320C6000 Optimizing Compiler User Guild, literature no. SPRU187K, Oct. 2002.

Texas Instrument, TMS320C6000 Programmer’s guide, literature no. SPRU198F, Feb. 2001.