STX Technical Manual & Desigm Guide - France-elec · 5.6.1 IRQ Resources ... Table 3-7 PCI...

STX Technical Manual &

Baseboard Design Guide

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Disclaimers The information in this document has been carefully checked and is believed to be accurate. AXIOMTEK Co., Ltd. assumes no responsibility for any infringements of patents or other rights of third parties which may result from its use. AXIOMTEK assumes no responsibility for any inaccuracies that may be contained in this document. AXIOMTEK makes no commitment to update or to keep current the information contained in this manual.

No part of this document may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of AXIOMTEK Co., Ltd.

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Please visit our web site for newest version of this Hardware Specification and for other information (like Product Info or drivers).

Copyright 2003 by AXIOMTEK Co., Ltd. All rights reserved. March 2003 Printed in Taiwan

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Table of Contents Table of Contents .................................................................................................................. iii List of Figures ........................................................................................................................ v List of Tables .......................................................................................................................... v Introduction ............................................................................................................................ 1

1.1 What is a STX Module? .................................................................................... 1 1.2 STX Baseboard ................................................................................................. 2 1.3 STX Interface..................................................................................................... 2 1.4 Side and View Definitions ................................................................................ 3 1.5 STX SoM Module............................................................................................... 3

1.5.1 Mounting Description .................................................................................................................. 4 1.6 System Block Diagram..................................................................................... 4 1.7 Functional Block Diagram ............................................................................... 5

Signal Descriptions & Pin Definitions .................................................................................. 6 2.1 Interface Signals............................................................................................... 6 2.2 Signal Summary................................................................................................ 6 2.3 Signal Group Location ..................................................................................... 7 2.4 Signal Description ............................................................................................ 7

2.4.1 PCI Bus Interface ......................................................................................................................... 9 2.4.1.1 PCI Function Module .................................................................................................... 12

2.4.2 ISA ............................................................................................................................................... 16 2.4.2.1 ISA Function Module .................................................................................................... 19

2.4.3 IDE ............................................................................................................................................... 21 2.4.3.1 E-IDE Function Module................................................................................................. 23

2.4.4 FDD.............................................................................................................................................. 27 2.4.4.1 FDD Function Module................................................................................................... 28

2.4.5 PPI ............................................................................................................................................... 29 2.4.5.1 PPI Function Module .................................................................................................... 29

2.4.6 SPI 1,2 ......................................................................................................................................... 31 2.4.6.1 SPI 1,2 Function Module .............................................................................................. 32

2.4.7 IrDA.............................................................................................................................................. 34 2.4.8 KB/MS.......................................................................................................................................... 34

2.4.8.1 KB/MS Function Module............................................................................................... 34 2.4.9 USB 1&2 ...................................................................................................................................... 36

2.4.9.1 USB 1&2 Function Module ........................................................................................... 36 2.4.10 USB 3&4 ...................................................................................................................................... 38

2.4.10.1 USB 3&4 Function Module....................................................................................... 38 2.4.11 ETH.............................................................................................................................................. 39

2.4.11.1 ETH Function Module ................................................................................................... 39 2.4.12 AC’97 ........................................................................................................................................... 41

2.4.12.1 AC’97 Function Module............................................................................................ 41 2.4.13 CRT.............................................................................................................................................. 43

2.4.13.1 CRT Function Module .............................................................................................. 43 2.4.14 FPI & TV-Out ............................................................................................................................... 45

2.4.14.1 FPI & TV-Out Function Module................................................................................ 48 2.4.15 FEAT ............................................................................................................................................ 50

2.4.15.1 FEAT Function Module............................................................................................. 50 2.4.16 MISC ............................................................................................................................................ 51 2.4.17 JTAG............................................................................................................................................ 52

2.4.17.1 JTAG Design Notes .................................................................................................. 52

iv

2.4.18 PWR............................................................................................................................................. 52 2.4.20 Reserved..................................................................................................................................... 53

2.5 Pin Definitions................................................................................................. 53 2.5.1 P1/J1 Connector Pinout ............................................................................................................ 53 2.5.2 P2/J2 Connector Pinout ............................................................................................................ 56 2.5.3 FC2 – ZV from STX Module ....................................................................................................... 59 2.5.4 FC1 – IDE2 from STX Module.................................................................................................... 60

Electrical Characteristics .................................................................................................... 56 3.1 Flat Panel Interface......................................................................................... 56 3.2 PCI Bus Interface............................................................................................ 64

3.2.1 Clock Distribution ...................................................................................................................... 64 3.2.2 IDSEL Mapping........................................................................................................................... 64 3.2.3 Interrupt Routing........................................................................................................................ 65 3.2.4 Signaling Voltage Level ............................................................................................................. 65

3.3 Electrical Power Requirements ..................................................................... 65 Mechanical Specifications................................................................................................... 66

4.1 STX Dimensions ............................................................................................. 66 4.2 FPC1 and FPC2 Connectors .......................................................................... 69 4.3 STX Base Board.............................................................................................. 70

Award BIOS Defaults ........................................................................................................... 71 5.1 Standard CMOS Features............................................................................... 71 5.2 Advanced BIOS Features............................................................................... 71 5.3 Advanced Chipset Features........................................................................... 72 5.4 Integrated Peripherals.................................................................................... 72 5.5 Power Management Setup ............................................................................. 73

5.5.1 Wake Up Events ......................................................................................................................... 73 5.6 PnP/PCI Configurations ................................................................................. 73

5.6.1 IRQ Resources ........................................................................................................................... 73 5.6.2 DMA Resources.......................................................................................................................... 74

5.7 Frequency/Voltage Control ............................................................................ 74 Troubleshooting ................................................................................................................... 75 Technical References .......................................................................................................... 83 Abbreviations ....................................................................................................................... 84

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List of Figures Figure 1-1 Bare STX Module ........................................................................................................ 1 Figure 1-2 Boxed STX Module ..................................................................................................... 2 Figure 2-1 Signal Group Location (J1 & J2 Connectors on STX Baseboard Top View)........ 7 Figure 2-2 PCI Slot Sample Design 1 ........................................................................................ 12 Figure 2-3 PCI Slot Sample Design 2 ........................................................................................ 13 Figure 2-4 PCI Slot Sample Design 3 ........................................................................................ 14 Figure 2-5 PCI Slot Sample Design 4 ........................................................................................ 15 Figure 2-6 ISA Function Module Schematic............................................................................. 20 Figure 2-7 IDE1 Function Module Schematic........................................................................... 23 Figure 2-8 IDE2 Function Module Schematic........................................................................... 26 Figure 2-9 FDD Function Module Schematic ........................................................................... 28 Figure 2-10 PPI Function Module Schematic ............................................................................. 30 Figure 2-11 SPI 1,2 Function Module Schematic....................................................................... 33 Figure 2-12 Keyboard and Mouse Function Module Schematic .............................................. 35 Figure 2-13 USB 1&2 Function Module Schematic ................................................................... 37 Figure 2-14 USB 3&4 Function Module Schematic ................................................................... 38 Figure 2-15 ETH Function Module Schematic ........................................................................... 40 Figure 2-16 AC’97 Function Module Schematic ........................................................................ 42 Figure 2-17 CRT Function Module Schematic ........................................................................... 44 Figure 2-18 FPI Function Module Schematic ............................................................................. 48 Figure 2-19 TV-Out Function Module Schematic....................................................................... 49 Figure 4-1 STX Module Dimensions.......................................................................................... 66 Figure 4-2 STX Module Dimensions.......................................................................................... 66 Figure 4-3 STX Module Layout .................................................................................................. 67 Figure 4-4 STX Height Dimensions ........................................................................................... 67 Figure 4-5 J1/J2 Connector Specifications .............................................................................. 68 Figure 4-6 FC1, FC2 Location of STX Baseboard.................................................................... 68 Figure 4-7 FPC41 Top View ........................................................................................................ 69

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List of Tables Table 1-1 STX Baseboard Format Examples............................................................................ 2 Table 2-1 STX Connectors.......................................................................................................... 6 Table 2-2 STX Signal Groups (P1&P2) ...................................................................................... 6 Table 2-3 Signal Direction .......................................................................................................... 7 Table 2-4 Driver Type .................................................................................................................. 8 Table 2-5 Signal Type.................................................................................................................. 8 Table 2-6 PCI Bus Signals ........................................................................................................ 11 Table 2-7 ISA Bus Signals – 8-bit............................................................................................. 18 Table 2-8 ISA Bus Signals – 16-bit extension......................................................................... 19 Table 2-9 E-IDE Interface Signals ............................................................................................ 22 Table 2-10 E-IDE Interface Signals ............................................................................................ 25 Table 2-11 Floppy Disk Drive Interface Signals ....................................................................... 27 Table 2-12 PPI Interface Signals ................................................................................................ 29 Table 2-13 SPI 1 Interface Signals ............................................................................................. 31 Table 2-14 SPI 2 Interface Signals ............................................................................................. 31 Table 2-15 IrDA Interface Signals .............................................................................................. 34 Table 2-16 Keyboard and Mouse Signals ................................................................................. 34 Table 2-17 Universal Serial Bus 1 Interface Signals................................................................ 36 Table 2-18 Universal Serial Bus 3&4 Interface Signals ........................................................... 38 Table 2-19 Ethernet 10/100Mbit Interface Signals.................................................................... 39 Table 2-20 Audio Codec ‘97 Interface Signals ......................................................................... 41 Table 2-21 CRT Interface Signals .............................................................................................. 43 Table 2-22 Flat Panel Interface Signals..................................................................................... 46 Table 2-23 FC2 Connector Pinout.............................................................................................. 47 Table 2-24 Feature Signals......................................................................................................... 50 Table 2-25 Miscellaneous Signals ............................................................................................. 51 Table 2-26 Power and Ground Pins........................................................................................... 52 Table 2-27 STX P1 / J1 Connector Pin out ................................................................................ 56 Table 2-28 STX P2/J2 Connector Pin out .................................................................................. 59 Table 2-29 FC2 Connector Pin out............................................................................................. 59 Table 2-30 FC1 Connector Pin out............................................................................................. 60 Table 3-1 Flat Panel Pixel Data Mapping................................................................................. 56 Table 3-2 DSTN and TFT Flat Panel Pixel Data Mapping....................................................... 57 Table 3-3 TFT Flat Panel Pixel Data Mapping......................................................................... 59 Table 3-4 Flat Panel Interface Pins of Color DSTN and Color TFT LCD .............................. 63 Table 3-5 Sampling Edge in 24-bitMode (FP_BSEL=1) ......................................................... 63 Table 3-6 Sampling Edge in 12-bitMode (FP_BSEL=0) ......................................................... 64 Table 3-7 PCI Interrupt Routing ............................................................................................... 65 Table 3-8 STX88600 Electrical Power Requirements............................................................. 65 Table 3-9 STX88601 Electrical Power Requirements............................................................. 66 Table 4-1 STX Module Type I. Heights..................................................................................... 69 Table B-1 Abbreviations Used.................................................................................................. 84

STX Module Technical Manual & Baseboard Design GuideVersion 0.99, March 2003

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document and/or product at any time and without notice.

C h a p t e r 1 Introduction

1.1 What is a STX Module? A general-purpose processing module, a STX module contains the complete functionality of common industrial PC on a very small space. STX module always provides all the functionality through its STX Interface regardless of the various memory configurations or computational power it possesses. STX’s major difference to other SoMs is that STX follows the PC/104 module standard. Therefore, the current enclosure design does not need to be changed once they choose to use STX as a new solution.

In case that STX Baseboard is to contain some components below the STX Module, it might be necessary to make sure that there is sufficient empty space below the STX Module. There are two STX Module types defined: For detailed description of dimensions and used plugs see Chapter 4. Mechanical Specification on.

For various purposes, the STX Hardware Specification defines two types of modules: � Bare STX Module

� Boxed STX Module

Bare STX Module is only a PCB with assembled components and no cooling mechanism implemented. The Bare STX Module is targeted for high integrated embedded and industrial applications where variability is the primary goal. It is presumed that the system designer will provide necessary heat removal according to application requirements.

Figure 1-1 Bare STX Module




Boxed STX Module has the top cover with heatsink. There is no need for additional heat removal as the heat removal capabilities of the Boxed STX Module are satisfied. Boxed STX Module is an ultimate, easy-to-upgrade solution and has to be designed to comply with mechanical specification.

Figure 1-2 Boxed STX Modules

1.2 STX Baseboard STX Baseboard provides receptacles for STX Module, supplies it with power and interfaces it with peripherals and expansion slots. The STX Baseboard can be designed in accordance with different formats – AT, ATX, LPX, NLX, PC-104 or custom format.

Format Description desktop ATX form factor Baseboard with standard desktop connectors

and functionality including ISA/PCI expansion slots PC-104+ all the required connectors and PC-104+ interface for typical

PC-104+ applications bare all the required connectors (CRT, keyboard/mouse, IDE,

floppy, net, audio etc.) for standalone applications minimal defined as bare with PC-104 size

Table 1-1 STX Baseboard Format Examples

1.3 STX Interface The STX Interface is an assembly of two pairs of 200-pin AMP connectors – two plugs on STX Module and two receptacles on STX Baseboard. The STX Interface uses 400 pins total. The plugs used on STX Module are referred to as P1 and P2 while the opposite receptacles used on STX Baseboard are referred to as J1 and J2. For more information see chapter 4. Mechanical Specification.




1.4 Side and View Definitions STX Module Bottom side of the STX Module is defined as the side equipped with the STX

Interface plugs. Top side is the opposite side.

Top view for the STX Module is defined as view at the top side. In opposite, bottom view is defined as view at the bottom side.

STX Baseboard Top side of the STX Baseboard is defined as the side equipped with the STX Interface receptacles. Bottom side is the opposite side.

Top view for the STX Baseboard is defined as view at the top side. In opposite, bottom view is defined as the bottom side.

1.5 STX SoM Module AXIOMTEK’s STX is a STX form factor SoM (System On Module) that comes with low power consumption processors (i.e., VIA Eden and INTEL ULV-PIII), core logic, graphics controller with CRT/LCD/TV-out, multiple I/O, fast Ethernet controller and AC-link interface for external audio Codec output. In addition to these integrated features onboard the STX, the STX standard interface provides 4 PCI Masters and ISA output for expansion design purpose applied on the related Baseboard.

With AXIOMTEK’s STX SoMs, customers can now adapt various I/O combinations for different application purposes while maintaining the same hardware kernel. The SoM architecture of AXIOMTEK basically follows the standard STX definition with Type-II module and configuration No. 2 stacking combination.

In addition to the standard pin-out from STX interfaces, AXIOMTEK’s STX SoM provides additional functions from it such as USB 3/4 from STX interface N/C pins, max. Of up to 36-bit TTL LCD plus STN, TV-out and ZV port support. Other than 24-bit from STX interface, AXIOMTEK defines a 41-pin FPC connector on the edge of SoM located on the back side of STX SoM, and an IDE2 port via 2nd 41-pin FPC connector on the components side of AXIOMTEK’s STX SoM.

Basically, the STX SoM only provides key kernel computing functions as engine; other I/O signal converting and interfacing are done through the Baseboard.

Like AC-link, this is a digital signal for Audio, Modem control; but this signal cannot be used without converted into analog interface. Therefore, we need to have a Baseboard which is equipped with AC’97 Codec to convert these AC-link digital signals to become the real world can accept type as analog.




1.5.1 Mounting Description Mounting orientation of the SoM is similar with the stack mounting of PC/104 modules. However, the stacking between SoM and Baseboard goes through STX connectors with 2 male connectors on SoM and 2 female connectors for the Baseboard. These connectors are 6.6 mm height plugs that allow the use of the components on the STX Baseboard underneath the STX Module. Basically, board-to-board is horizontal, but interface connectors are vertical. At this moment, there is no clear indication/explanation describing multiple stacking from the rear side of the Baseboard.

The current STX-compatible Baseboards are STB86600, STB97100, STB97200, STB97300 and STB97101. More Baseboards will be added soon in AXIOMTEK’s product line.

1.6 System Block Diagram




1.7 Functional Block Diagram

STXVEA STX Module Data bookVersion 1.0, March 2003

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to this document and/or product at any time and without notice.

:

C h a p t e r 2 Signal Descriptions & Pin Definitions

2.1 Interface Signals Connectors Label

STX base board Connector P1 STX base board Connector P2 ZV from STX module FC2 IDE2 from STX module FC1

Table 2-1 STX Connectors

2.2 Signal Summary Signal Group Group Description Pins Count

PCI PCI Bus 60 ISA ISA Bus 88 E-IDE E-IDE Interface 28 FDD Floppy Disk Drive Interface 15 PPI PPI Interface 17 SPI1 Serial Port 1 Interface 8 SPI2 Serial Port 2 Interface 8 IrDA IrDA Interface 2 KB/MS Keyboard and PS/2 Mouse Signals 4 USB 1&2 Universal Serial Bus 1 Interface 3 USB3&4 Universal Serial Bus 3 and 4 Interface 3 ETH Ethernet 10/100Mbit Interface 6 AC’97 Audio Codec ‘97 Interface 5 CRT CRT Interface 9 FPI Flat Panel Interface 36 FEAT Feature Signals 7 MISC Miscellaneous Signals 9 JTAG JTAG/Boundary Scan Signals 5 PWR Power and Ground Pins 81 RSVD Reserved Pins 6 Total 400

Table 2-2 STX Signal Groups (P1&P2)




2.3 Signal Group Location

Figure 2-1 Signal Group Location (J1 & J2 Connectors on STX Baseboard Top View)

2.4 Signal Description This section describes all the signals (sorted in alphabetical order) in each group.

The following notations are used to describe the signal direction:

Symbol Description I Input-only signal O Output-only signal B Bi-directional input / output signal

DC Refers to power or ground pins that are not used for any information transfer.

Table 2-3 Signal Direction




The signal description also includes the output driver type used for the particular signal:

Symbol Description TP Standard totem pole active driver OD Open-drain driver allows multiple devices to share a signal as a

wire-OR. A pull-up resistor is required to sustain the inactive state. TS Output or bi-directional tri-state pin driver STS Sustained tri-state is an active low tri-state signal owned and driven

by one and only one device at a time. The device that drives a STS pin low must drive it high for at least one clock before letting it float. A new device cannot start driving a STS signal any sooner than one clock after the previous owner tri-states it. A pull-up resistor is required to sustain the inactive state until another device drives it.

A Analog output driver

Table 2-4 Driver Type

The following notation is used if pull-up or pull-down resistor is implemented on the STX Module:

Symbol Description U Pull-up resistor is implemented on the STX Module. D Pull-down resistor is implemented on the STX Module.

Table 2-5 Signal Type

Whole signal type is composed from one or more of these symbols divided by a hyphen.

For example, B-STS-U means bi-directional sustained tri-state signal with pull-up resistor implemented on the STX Module.




2.4.1 PCI Bus Interface STX Interface supports up to three PCI devices or slots. The clock distribution for each PCI device is 33MHz, under any CPU so long as the skew requirement is within 500PS.

Signal Pin Type Description ADADADAD0000 J1/43J1/43J1/43J1/43

AD1AD1AD1AD1 J1/45J1/45J1/45J1/45

AD2AD2AD2AD2 J1/48J1/48J1/48J1/48

AD3AD3AD3AD3 J1/51J1/51J1/51J1/51

AD4AD4AD4AD4 J1/49J1/49J1/49J1/49

AD5AD5AD5AD5 J1/50J1/50J1/50J1/50

AD6AD6AD6AD6 J1/55J1/55J1/55J1/55

AD7AD7AD7AD7 J1/56J1/56J1/56J1/56

AD8AD8AD8AD8 J1/57J1/57J1/57J1/57

AD9AD9AD9AD9 J1/60J1/60J1/60J1/60

AD10AD10AD10AD10 J1/61J1/61J1/61J1/61

AD11AD11AD11AD11 J1/62J1/62J1/62J1/62

AD12AD12AD12AD12 J1/67J1/67J1/67J1/67

AD13AD13AD13AD13 J1/68J1/68J1/68J1/68

AD14AD14AD14AD14 J1/66J1/66J1/66J1/66

AD15AD15AD15AD15 J1/69J1/69J1/69J1/69

AD16AD16AD16AD16 J1/96J1/96J1/96J1/96

ADADADAD17171717 J1/97J1/97J1/97J1/97

AD18AD18AD18AD18 J1/98J1/98J1/98J1/98

AD19AD19AD19AD19 J1/103J1/103J1/103J1/103

AD20AD20AD20AD20 J1/104J1/104J1/104J1/104

AD21AD21AD21AD21 J1/102J1/102J1/102J1/102

AD22AD22AD22AD22 J1/105J1/105J1/105J1/105

AD23AD23AD23AD23 J1/108J1/108J1/108J1/108

AD24AD24AD24AD24 J1/114J1/114J1/114J1/114

AD25AD25AD25AD25 J1/117J1/117J1/117J1/117

AD26AD26AD26AD26 J1/120J1/120J1/120J1/120

AD27AD27AD27AD27 J1/123J1/123J1/123J1/123

AD28AD28AD28AD28 J1/121J1/121J1/121J1/121

AD29AD29AD29AD29 J1/122J1/122J1/122J1/122

AD30AD30AD30AD30 J1/129J1/129J1/129J1/129

AD31AD31AD31AD31 J1/127J1/127J1/127J1/127

B-TS Address and Data are multiplexed signals connected to the PCI address/data bus. Address is driven during the address phase with FRAME# assertion, data is driven or received in the following clocks.




C/BE0#C/BE0#C/BE0#C/BE0# J1/54J1/54J1/54J1/54




B-TS Bus Command and Byte Enables define the bus command during the address phase of a transaction, while are used as byte enables during the data phase. The byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. C/BE[0]# applies to byte 0 (LSB) and C/BE[3]# applies to byte 3 (MSB).

CLK3CLK3CLK3CLK3 J1/145J1/145J1/145J1/145




O-TP Clock provides timing for all transactions on PCI and is an input to every PCI device. All other PCI signals, except RST#, INT[D..A]#, are sampled on the rising edge of CLK and all other timing parameters are defined with respect to this edge. Currently the STX supports 33 MHz frequency.

DEVSEL#DEVSEL#DEVSEL#DEVSEL# J1/87J1/87J1/87J1/87 B-STS-U Device Select indicates the driving device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected.

FRAME#FRAME#FRAME#FRAME# J1/90J1/90J1/90J1/90 B-STS-U Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME# is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is disserted, the transaction is in the final data phase or has completed.

GNT0#GNT0#GNT0#GNT0# J1/135J1/135J1/135J1/135




O-TS Grant indicates to the agent that access to the bus has been granted. This is a point to point signal. Every master has its own GNT# which must be ignored while RST# is asserted.

INTA#INTA#INTA#INTA# J1/154J1/154J1/154J1/154

INTB#INTB#INTB#INTB# J1/155J1/155J1/155J1/155

INTC#INTC#INTC#INTC# J1/153J1/153J1/153J1/153

INTD#INTD#INTD#INTD# J1/152J1/152J1/152J1/152

B-OD-U Interrupts are level sensitive, asserted low, using open drain output drivers. A device asserts its INTx# line when requesting attention from its device driver. Once the INTx# signal is asserted, it remains asserted until the device driver clears the pending request. When the request is cleared, the device desserts its INTx# signals.

IRDY#IRDY#IRDY#IRDY# J/89J/89J/89J/89 B-STS-U Initiator Ready indicates the initiating agents (bus masters) ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates that valid data is present on AD[31..00]. During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together.

Continued . . . . .




Signal Pin Type Description LOCK#LOCK#LOCK#LOCK# J1/81J1/81J1/81J1/81 B-STS-U Lock indicates an atomic operation that may require multiple transactions

to complete. When LOCK# is asserted, non-exclusive transactions may proceed to an address that is not currently locked.

PARPARPARPAR J1/75J1/75J1/75J1/75 B-TS Parity is even parity across AD[31..00] and C/BE[3..0]#. Parity generation is required by all PCI agents. PAR is stable and valid one clock after the address phase. For data phases, PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. The master drives PAR for address and write data phases; the target drives PAR for read data phases.

PEPEPEPERR#RR#RR#RR# J1/80J1/80J1/80J1/80 B-STS-U Parity Error reports data parity errors during all PCI transactions except a Special Cycle. The PERR# pin is sustained tri-state and must be driven active by the agent receiving data two clocks following the data when a data parity error is detected.

REQ3#REQ3#REQ3#REQ3# J1/130J1/130J1/130J1/130



REQ0#REQ0#REQ0#REQ0# JJJJ1/1271/1271/1271/127

I-U Request indicates to the arbiter that this agent desires use of the bus. This is a point to point signal. Every master has its own REQ# which must be tri-stated while RST# is asserted.

RST#RST#RST#RST# J1/151J1/151J1/151J1/151 O-TP Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent state. Any time RST# is asserted, all PCI output signals must be driven to their benign state.

SERR#SERR#SERR#SERR# J1/74J1/74J1/74J1/74 B-OD-U System Error reports address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. SERR# is open drain output and is actively driven for a single PCI clock by the agent reporting the error.

STOP#STOP#STOP#STOP# J1/82J1/82J1/82J1/82 B-STS-U Stop indicates the current target is requesting the master to stop the current transaction.

TRDY# TRDY# TRDY# TRDY# J1/88J1/88J1/88J1/88 B-STS-U Target Ready indicates the target agent’s (selected device’s) ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed on any clock both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that valid data is present on AD[31..00]. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together.

Table 2-6 PCI Bus Signals




2.4.1.1 PCI Function Module The standard STX interface can support up to four PCI devices or slots on the Baseboard and only up to three PCI devices with bus master capability. AXIOMTEK module, however, can support four PCI devices with BUS master capability.

Sample Design for Four PCI Slot on STX Baseboard. The trace length of all PCI clocks should be similar. The trace attribute of all clocks and signals must have a minimum of 6 mils width and 12 mils between two adjacent traces.

0

E

VCC5

3VSBVCC12 VCC3VCC5 VCC12VCC5 VCC3

VCC5

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29

A62A61A60A59A58A57A56A55A54A53A52

A49A48A47A46A45A44A43A42A41A40A39A38A37A36A35A34A33A32A31A30

J1/154

IDSEL

TDI

RESERVED

RESERVED

GND

GND

GND

GND

GND

GND

GND

GNDGND

GND

+5V

+5V+5V

+5V

+5V

+5V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+12V

+5V

AD0AD2

AD4AD6

AD9

AD11

AD15

AD13

AD16AD18

AD20AD22

AD26

AD24

AD28

AD30

GNT

PME

REQ64

C/BE0

SDONE

PAR

SBO

STOP

TRDY

FRAME

RST3.3V_AUX

INTAINTC

TRST

TMS

J1/151J1/135

J1/110J1/129J1/121J1/120J1/114

J1/105J1/104J1/98J1/96J1/90

J1/88

J1/82

J1/75J1/69J1/68J1/62J1/60

J1/54

J1/55J1/49J1/48J1/43

B14

B52B53B54B55B56B57B58B59B60B61B62

B10B11B12B13

B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32B33B34B35B36B37B38B39B40B41B42B43B44B45B46B47B48B49

B1B2B3B4B5B6B7B8B9

J1/155

J1/145J1/130J1/127J1/122J1/123J1/117J1/116J1/108J1/102J1/103

J1/97J1/95J1/89J1/87J1/81J1/80J1/74J1/72J1/66J1/67J1/61

J1/57J1/56J1/50J1/51

J1/45

J1/152INTCINTA

PCI1

RESERVED

RESERVED

-12VTCKGNDTDO+5V+5VINTBINTDPRSNT1

PRSNT2GNDGND

GND

GND

GND

GND

GND

GND

GND

GND

CLK

+5V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

AD12AD10

AD31AD29

AD27AD25

AD23

AD21AD19

AD17

AD14

REQ

C/BE3

C/BE2

IRDY

DEVSEL

LOCK

SERR

C/BE1

PERR

GND

+5V

+5V+5V

+3.3V

AD8AD7

AD5AD3

AD1

ACK64

J1/153

AD21

PCI_RSTGNT1

AD30AD28AD26AD24

AD22AD20AD18AD16FRAME

TRDYSTOP

PARAD15AD13AD11AD9

C_BE0

AD6AD4AD2AD0

PME

INTDINTB

CLK0REQ0

AD31AD29AD27AD25C_BE3AD23

AD19AD17C_BE2IRDYDEVSEL

PLOCKPERRSERRC_BE1AD14AD12AD10

AD21

AD8AD7AD5AD3AD1

Figure 2-2 PCI Slot Sample Design 1




B14

INTCINTA

VCC5

3VSBVCC12

VCC3VCC5

PCI2VCC12 VCC5 VCC3

J1/154

VCC5

J1/141J1/128J1/127J1/122J1/123J1/117J1/116J1/108J1/102J1/103

J1/97J1/95J1/89J1/87J1/81J1/80J1/74J1/72J1/66J1/67J1/61

J1/57J1/56J1/50J1/51J1/45

AD21

J1/151J1/138J1/110J1/129J1/121J1/120J1/114

J1/105J1/104J1/98J1/96J1/90J1/88J1/82

J1/75J1/69J1/68J1/62J1/60

J1/54J1/55J1/49J1/48J1/43

J1/153

B52B53B54B55B56B57B58B59B60B61B62

B10B11B12B13B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32B33B34B35B36B37B38B39B40B41B42B43B44B45B46B47B48B49

B1B2B3B4B5B6B7B8B9

CLK1REQ1AD31AD29AD27AD25C_BE3AD23

AD19AD17C_BE2IRDYDEVSELPLOCKPERRSERRC_BE1AD14AD12AD10

AD8AD7AD5AD3AD1

AD21


A62A61A60A59A58A57A56A55A54A53A52


INTDINTB

PCI_RSTGNT1

AD30AD28AD26AD24

AD22AD20AD18AD16FRAMETRDYSTOP

PARAD15AD13AD11AD9

C_BE0

AD6AD4AD2AD0

J1/154J1/152

IDSEL

TDI

RESERVED

RESERVED

GND

GND

GND

GND

GND

GND

GND

GNDGND

GND

+5V

+5V+5V

+5V

+5V

+5V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+12V

+5V

AD0AD2

AD4AD6

AD9

AD11

AD15AD13

AD16AD18

AD20AD22

AD26

AD24

AD28

AD30

GNT

PME

REQ64

C/BE0

SDONE

PAR

SBO

STOP

TRDY

FRAME

RST3.3V_AUX

INTAINTC

TRST

TMS

-12VTCKGNDTDO+5V+5VINTBINTDPRSNT1RESERVEDPRSNT2

RESERVED

GNDGND

GND

GND

GND

GND

GND

GND

GND

GND

GND

CLK

+5V

+5V

+5V+5V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

AD12AD10

AD8AD7

AD5AD3

AD1

AD31AD29AD27AD25

AD23

AD21AD19

AD17

AD14

REQ

C/BE3

C/BE2

IRDY

DEVSEL

LOCK

SERR

C/BE1

ACK64

PERR





INTCINTA

PCI_RSTGNT2PMEAD30AD28AD26AD24

AD22AD20AD18AD16FRAMETRDYSTOP

PARAD15AD13AD11AD9

C_BE0AD6AD4AD2AD0

J1/151J1/151J1/110J1/129J1/121J1/120J1/114

J1/105J1/104J1/98J1/96J1/90J1/88J1/82

J1/75J1/69J1/68J1/62J1/60

J1/54J1/55J1/49J1/48J1/43

VCC5

3VSBVCC12VCC3VCC5

J1/153J1/154

PCI3VCC12 VCC5 VCC3

J1/152J1/155

VCC5

J1/141J1/137J1/127J1/122J1/123J1/117J1/116J1/108J1/102J1/103

J1/97J1/95J1/89J1/87J1/81J1/80J1/74J1/72J1/66J1/67J1/61

J1/57J1/56J1/50J1/51J1/45

INTDINTB

CLK2REQ2AD31AD29AD27AD25C_BE3AD23AD21AD19

J1/122

AD17C_BE2IRDYDEVSELPLOCKPERRSERRC_BE1AD14AD12AD10

AD8AD7AD5AD3AD1

B1B2B3B4B5B6B7B8B9

B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32B33B34B35B36B37B38B39B40B41B42B43B44B45B46B47B48B49

B52B53B54B55B56B57B58B59B60B61B62

-12VTCKGNDTDO+5V+5VINTBINTDPRSNT1RESERVEDPRSNT2

RESERVED

GNDGND

GND

GND

GND

GND

GND

GND

GND

GND

GND

CLK

+5V

+5V

+5V+5V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

AD12AD10

AD8AD7

AD5AD3

AD1

AD31AD29AD23AD25

AD23

AD21AD19

AD17

AD14

REQ

C/BE3

C/BE2IRDY

DEVSEL

LOCKPERRSERR

C/BE1

ACK64

IDSEL

TDI

RESERVED

RESERVED

GND

GND

GND

GND

GND

GND

GND

GNDGND

GND

+5V

+5V+5V

+5V

+5V

+5V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+12V

+5V

AD0AD2

AD4AD6

AD9

AD11

AD15+3.3V

AD16AD18

AD20AD22

AD26

AD24

AD28

AD30

GNT

PME

REQ64

C/BE0

SDONE

PARSBO

STOP

TRDY

FRAME

RST3.3V_AUX

INTAINTC

TRST

TMS


A62A61A60A59A58A57A56A55A54A53A52










2.4.2 ISA STX Interface supports both 8-bit ISA and 16-bit ISA extensions.

Signal Pin Type Description AENAENAENAEN J2/50J2/50J2/50J2/50 O-TP Address Enable is driven by the Permanent Master to indicate that the address

lines are driven by a DMA controller. The assertion of AEN disables response to I/O port addresses when the I/O command strobes are asserted. When AEN is asserted only the device asserting DRQn should respond.

BALEBALEBALEBALE J2/186J2/186J2/186J2/186 O-TP Bus Address Latch Enable is used to latch valid addresses from the current master on the falling edge of BALE.

DACK3#DACK3#DACK3#DACK3# J2/84J2/84J2/84J2/84




O-TP DMA Acknowledges is driven by the Permanent Master to indicate that a DMA operation can begin. They are driven at all times for those DMA channels that are attached.

DRQ0DRQ0DRQ0DRQ0 J2/112J2/112J2/112J2/112




I-D DMA Requests are driven by a DMA bus adapter to indicate a request for a DMA bus operation. DRQ[3..1] request 8-bit DMA operations. All bus DMA adapters will drive these lines with a tri-state driver. The Permanent Master monitors this signal to determine which if any of the DMA devices are requesting the bus.

ENDXFR#ENDXFR#ENDXFR#ENDXFR# J2/32J2/32J2/32J2/32 I-U End of Transfer is asserted by a 16-bit memory mapped device that may cause an early termination of the current transfer. It should be gated with MEMR# or MEMW# and is not valid during DMA transfers. It is called 0WS# on some implementations.

IOCHCHK#IOCHCHK#IOCHCHK#IOCHCHK# J2/4J2/4J2/4J2/4 I-U I/O Channel Check is driven active by an adapter detecting a fatal error during bus operation. This open collector signal is driven low typically causing a nonmaskable interrupt.

IOCHRDYIOCHRDYIOCHRDYIOCHRDY J2/42J2/42J2/42J2/42 B-OD-U I/O Channel Ready is driven inactive by the target of either a memory or I/O operation to extend the current cycle. This open collector signal is driven based on the system address and the appropriate control strobe.

IOR#IOR#IOR#IOR# J2/76J2/76J2/76J2/76 B-TS-U I/O Read is driven to indicate an I/O read operation. I/O mapped devices using this strobe should decode for selection of adapter and address based on SA[15..00] and AEN. Additionally, DMA devices will use IOR# in conjunction with the appropriate DACKn# to decode a DMA transfer from the I/O device.

IOW#IOW#IOW#IOW# J2/68J2/68J2/68J2/68 B-TS-U I/O Write is driven to indicate an I/O write operation. I/O mapped devices using this strobe should decode for selection of adapter and address based on SA[15..00] and AEN. Additionally, DMA devices will use IOW# in conjunction with the appropriate DACKn# to decode a DMA transfer from the I/O device.

Continued . . . . .

Signal Pin Type Description




IRQ9,IRQ9,IRQ9,IRQ9, J2/16J2/16J2/16J2/16

IRQ7IRQ7IRQ7IRQ7 J2/122J2/122J2/122J2/122





I-U Interrupt Requests indicate the presence of an interrupting bus adapter. Because of the use of pull-ups, unused interrupt inputs must be masked.

OSCOSCOSCOSC J2/194J2/194J2/194J2/194 O-TP Oscillator This is a clock signal with a 14.31818 MHz frequency. REFRESH#REFRESH#REFRESH#REFRESH# J2/114J2/114J2/114J2/114 B-TS-U Refresh is driven by the Current Master to indicate a memory refresh operation.RESETDRVRESETDRVRESETDRVRESETDRV J2/8J2/8J2/8J2/8 O-TP Reset Drive indicates that the adapter should be brought to an initial reset

condition. SA0SA0SA0SA0 J2/198J2/198J2/198J2/198

SA1SA1SA1SA1 J2/196J2/196J2/196J2/196

SA2SA2SA2SA2 J2/192J2/192J2/192J2/192

SA3SA3SA3SA3 J2/188J2/188J2/188J2/188

SA4SA4SA4SA4 J2/180J2/180J2/180J2/180

SA5SA5SA5SA5 J2/172J2/172J2/172J2/172

SSSSA6A6A6A6 J2/164J2/164J2/164J2/164

SA7SA7SA7SA7 J2/160J2/160J2/160J2/160

SA8SA8SA8SA8 J2/148J2/148J2/148J2/148

SA9SA9SA9SA9 J2/140J2/140J2/140J2/140

SA10SA10SA10SA10 J2/132J2/132J2/132J2/132

SA11SA11SA11SA11 J2/124J2/124J2/124J2/124

SA12SA12SA12SA12 J2/116J2/116J2/116J2/116

SA13SA13SA13SA13 J2/108J2/108J2/108J2/108

SA14SA14SA14SA14 J2/94J2/94J2/94J2/94

SA15SA15SA15SA15 J2/90J2/90J2/90J2/90

SA16SA16SA16SA16 J2/82J2/82J2/82J2/82

SA17SA17SA17SA17 J2/74J2/74J2/74J2/74

SA18SA18SA18SA18 J2/66J2/66J2/66J2/66

SA19SA19SA19SA19 J2/58J2/58J2/58J2/58

B-TS System Address signals define the selection with the granularity of one byte within the 1 MB section of memory defined by the LA[19..17] address lines. The address lines SA[19..17] that are coincident with LA[19..17] are defined to have the same value as LA[19..17] for all memory cycles. During a refresh initiated transfer only SA[7..0] are valid.

Continued . . . . .




Signal Pin Type Description SD0SD0SD0SD0 J2/J2/J2/J2/34343434 SD1SD1SD1SD1 J2/30J2/30J2/30J2/30 SD2SD2SD2SD2 J2/26J2/26J2/26J2/26 SD3SD3SD3SD3 J2/22J2/22J2/22J2/22 SD4SD4SD4SD4 J2/18J2/18J2/18J2/18 SD5SD5SD5SD5 J2/14J2/14J2/14J2/14 SD6SD6SD6SD6 J2/10J2/10J2/10J2/10 SD7SD7SD7SD7 J2/6J2/6J2/6J2/6

B-TS System Data are defined for the low order byte of a 16-bit bus and the only bus for 8-bit adapters and systems. Memory or I/O transfers on this bus are defined for 8-bit operations with even or odd addresses and for 16-bit operations for odd addresses only. The signals SA0 and SBHE# are used to define the data present on this bus.

SMEMR#SMEMR#SMEMR#SMEMR# J2/60J2/60J2/60J2/60 O-TP Standard Memory Read is driven to indicate a memory read operation in the first 1 MB of system memory. Memory mapped devices using this strobe should decode addresses SA[19..00] only.

SMEMW#SMEMW#SMEMW#SMEMW# J2/52J2/52J2/52J2/52 O-TP Standard Memory Write is driven to indicate a memory write operation in the first 1 MB of system memory. Memory mapped devices using this strobe should decode addresses SA[19..00] only.

SYSCLKSYSCLKSYSCLKSYSCLK J2/122J2/122J2/122J2/122 O-TP System Clock is the reference clock for the ISA bus. This clock signal may vary in frequency from 6 MHz to 8.33 MHz.

TCTCTCTC J2/178J2/178J2/178J2/178 O-TP Terminal Count is asserted during a read or writes command indicating that the DMA controller has reached a terminal count for the current transfer. DACKn# must be presented by the bus adapter to validate the TC signal.

Table 2-7 ISA Bus Signals – 8-bit

The following table shows signals in 16-bit ISA extension.

Signal Pin Type Description DACK7# DACK7# DACK7# DACK7# J2/152J2/152J2/152J2/152



O-TP DMA Acknowledges is driven by the Permanent Master to indicate that a DMA operation can begin. They are driven with a totem pole driver at all times for those DMA channels that are attached.




I-D DMA Requests are driven by a DMA bus adapter to indicate a request for a DMA bus operation. DRQ[7..5] request 16-bit DMA operations while DRQ0 requests 8-bit DMA operations. All bus DMA adapters will drive these lines with a tri-state driver. The Permanent Master monitors this signal to determine which if any of the DMA devices are requesting the bus.

IOCS16#IOCS16#IOCS16#IOCS16# J2/54J2/54J2/54J2/54 I-U 16 bit I/O Chip Select is driven by an I/O mapped adapter indicating that the I/O device located at the address on the bus is 16 bits wide. This signal is driven based only on SA[15..00] when AEN is not asserted.

IRQ15IRQ15IRQ15IRQ15 J2/86J2/86J2/86J2/86 IRQ14IRQ14IRQ14IRQ14 J2/94J2/94J2/94J2/94 IRQ12IRQ12IRQ12IRQ12 J2/78J2/78J2/78J2/78 IRQ11IRQ11IRQ11IRQ11 J2/70J2/70J2/70J2/70 IRQ10IRQ10IRQ10IRQ10 J2/62J2/62J2/62J2/62

I-U Interrupt Requests indicate the presence of an interrupting bus adapter. Because of the use of pull-ups, unused interrupt inputs must be masked.

Continued . . . . .




Signal Pin Type Description LA17LA17LA17LA17 J2/102J2/102J2/102J2/102

LA18LA18LA18LA18 J2/96J2/96J2/96J2/96

LA19LA19LA19LA19 J2/88J2/88J2/88J2/88

LA20LA20LA20LA20 J2/80J2/80J2/80J2/80

LA21LA21LA21LA21 J2/72J2/72J2/72J2/72

LA22LA22LA22LA22 J2/64J2/64J2/64J2/64

LA23LA23LA23LA23 J2/56J2/56J2/56J2/56

B-TS Latched Address signals define the selection of a 128 KB of memory space within the 16 MB address range of the 16-bit data bus. These signals are not defined for I/O access.

MASTER#MASTER#MASTER#MASTER# J2/176J2/176J2/176J2/176 I-U Master is driven by a DMA bus adapter to indicate that the adapter is going to drive the system address, data and control lines.

MEMCS16#MEMCS16#MEMCS16#MEMCS16# J2/46J2/46J2/46J2/46 B-OD-U 16 bit Memory Chip Select is driven by a memory mapped adapter indicating that the memory device located at the address on the bus is 16 bits wide. This signal is driven based on LA[23..17] only.

MEMR#MEMR#MEMR#MEMR# J2/110J2/110J2/110J2/110 B-TS-U Memory Read is driven to indicate a memory read operation. Memory mapped devices using this strobe should decode addresses LA[23..17] and SA[19..00].

MEMW#MEMW#MEMW#MEMW# J2/118J2/118J2/118J2/118 B-TS-U Memory Write is driven to indicate a memory write operation. Memory mapped devices using this strobe should decode addresses LA[23..17] and SA[19..00].

SBHE#SBHE#SBHE#SBHE# J2/48J2/48J2/48J2/48 B-TS System Byte High Enable indicates that a byte is being transferred on the upper byte (SD[15..08]) of the 16-bit bus.

SD8SD8SD8SD8 J2/126J2/126J2/126J2/126

SD9SD9SD9SD9 J2/134J2/134J2/134J2/134

SD10SD10SD10SD10 J2/142J2/142J2/142J2/142

SD11SD11SD11SD11 J2/150J2/150J2/150J2/150

SD12SD12SD12SD12 J2/158J2/158J2/158J2/158

SD13SD13SD13SD13 J2/166J2/166J2/166J2/166

SD14SD14SD14SD14 JJJJ2/1742/1742/1742/174

SD15SD15SD15SD15 J2/182J2/182J2/182J2/182

B-TS System Data are defined for the high order byte of a 16-bit bus. Memory or I/O transfers on this bus are defined when SBHE# is active.

Table 2-8 ISA Bus Signals – 16-bit extension

2.4.2.1 ISA Function Module The standard STX interface supports both 8-bit ISA and 16-bit extensions. STX Interface supports ISA devices on the Baseboard. All pull-ups are integrated on the STX module.




Figure 2-6 ISA Function Module Schematic




2.4.3 IDE STX Interface supports one E-IDE channel for two (master and slave) devices. If the STX Module contains an on-board IDE device, this device should be connected to different E-IDE channel than the one that is connected to STX Interface.

Signal Pin Type Description CS0CS0CS0CS0 J2/53J2/53J2/53J2/53

CS1CS1CS1CS1 J2/55J2/55J2/55J2/55

O-TP Chip Selects are used to select the Command Block or Control Block registers. When DMACK# is asserted, CS[1..0]# shall be negated and transfers shall be 16 bits wide.

DA2DA2DA2DA2 J2/51J2/51J2/51J2/51

DA1DA1DA1DA1 J2/47J2/47J2/47J2/47

DA0DA0DA0DA0 J2/49J2/49J2/49J2/49

O-TP Device Address is the 3-bit binary coded address asserted by the host to access a register or data port in the device.

DD0DD0DD0DD0 J2/31J2/31J2/31J2/31

DD1DD1DD1DD1 J2/27J2/27J2/27J2/27

DD2DD2DD2DD2 J2/23J2/23J2/23J2/23

DD3DD3DD3DD3 J2/19J2/19J2/19J2/19

DD4DD4DD4DD4 JJJJ2/152/152/152/15

DD5DD5DD5DD5 J2/7J2/7J2/7J2/7





DD10DD10DD10DD10 J213J213J213J213

DD11DD11DD11DD11 J2/17J2/17J2/17J2/17

DD12DD12DD12DD12 J2/21J2/21J2/21J2/21

DD13DD13DD13DD13 J2/25J2/25J2/25J2/25

DD14DD14DD14DD14 J2/29J2/29J2/29J2/29

DD15DD15DD15DD15 J2/33J2/33J2/33J2/33

B-TS Device Data is an 8-bit or 16-bit bi-directional data interface between the host and the device. The lower 8 bits are used for 8-bit register transfers. Data transfers are 16 bits wide except for devices that implement 8-bit data transfers only.

DIOR#DIOR#DIOR#DIOR# J2/41J2/41J2/41J2/41 O-TS Device I/O Read is the strobe signal asserted by the host to read device registers or the Data port. In Ultra DMA mode this pin is used for Ultra DMA Ready (HDMARDY#) and Ultra DMA Data Strobe (HSTROBE).

DIOW#DIOW#DIOW#DIOW# J2/39J2/39J2/39J2/39 O-TS Device I/O Write is the strobe signal asserted by the host to write device registers or the Data port. In Ultra DMA mode this pin is used for Stop Ultra DMA burst (STOP).

DMACK#DMACK#DMACK#DMACK# J2/45J2/45J2/45J2/45 O-TP DMA Acknowledge shall be used by the host in response to DMARQ to initiate DMA transfers.

DMARQDMARQDMARQDMARQ J2/37J2/37J2/37J2/37 I-D DMA Request is used for DMA data transfers between host and device and shall be asserted by the device when the device is ready to transfer data to or from the host. The direction of data




transfer is controlled by DIOR# and DIOW#. The device shall wait until the host asserts DMACK# before negating DMARQ, and re-asserting DMARQ if there is more data to transfer.

INTRQINTRQINTRQINTRQ J2/35J2/35J2/35J2/35 I-U Device Interrupt is used by the selected device to interrupt the host system when interrupt pending is set. This signal shall be released when the device is not selected.

IORDYIORDYIORDYIORDY J2/43J2/43J2/43J2/43 I-U I/O Channel Ready is negated to extend the host transfer cycle of any host register access (read or write) when the device is not ready to respond to a data transfer request. In Ultra DMA mode this pin is used for Ultra DMA Ready (DDMARDY#) and Ultra DMA Data Strobe (DSTROBE).

RRRRESET#ESET#ESET#ESET# J2/1J2/1J2/1J2/1 O-TP Hardware Reset is used by the host to reset the device.

Table 2-9 E-IDE Interface Signals




2.4.3.1 E-IDE Function Module

Figure 2-7 IDE1 Function Module Schematic




Signal Pin Type Description CS0CS0CS0CS0 FC1/38FC1/38FC1/38FC1/38

CS1CS1CS1CS1 FC1/39FC1/39FC1/39FC1/39

O-TP Chip Selects are used to select the Command Block or Control Block registers. When DMACK# is asserted, CS[1..0]# shall be negated and transfers shall be 16 bits wide.

DA2DA2DA2DA2 FC1/37FC1/37FC1/37FC1/37



O-TP Device Address is the 3-bit binary coded address asserted by the host to access a register or data port in the device.

DD0DD0DD0DD0 FC1/22FC1/22FC1/22FC1/22












DD12DD12DD12DD12 FC1/FC1/FC1/FC1/16161616




B-TS Device Data is an 8-bit or 16-bit bi-directional data interface between the host and the device. The lower 8 bits are used for 8-bit register transfers. Data transfers are 16 bits wide except for devices that implement 8-bit data transfers only.

DIOR#DIOR#DIOR#DIOR# FC1/28FC1/28FC1/28FC1/28 O-TS Device I/O Read is the strobe signal asserted by the host to read device registers or the Data port. In Ultra DMA mode this pin is used for Ultra DMA Ready (HDMARDY#) and Ultra DMA Data Strobe (HSTROBE).

DIOW#DIOW#DIOW#DIOW# FC1/27FC1/27FC1/27FC1/27 O-TS Device I/O Write is the strobe signal asserted by the host to write device registers or the Data port. In Ultra DMA mode this pin is used for Stop Ultra DMA burst (STOP).

DMACK#DMACK#DMACK#DMACK# FC1/30FC1/30FC1/30FC1/30 O-TP DMA Acknowledge shall be used by the host in response to DMARQ to initiate DMA transfers.

DMARQDMARQDMARQDMARQ FC1/26FC1/26FC1/26FC1/26 I-D DMA Request is used for DMA data transfers between host and device and shall be asserted by the device when the device is ready to transfer data to or from the host. The direction of data transfer is controlled by DIOR# and DIOW#. The device shall wait until the host asserts DMACK# before negating DMARQ, and re-asserting DMARQ if there is more data to transfer.

INTRQINTRQINTRQINTRQ FC1/32FC1/32FC1/32FC1/32 I-U Device Interrupt is used by the selected device to interrupt the host system when interrupt pending is set. This signal shall be released when the device is not selected.




IORDYIORDYIORDYIORDY FC1/29FC1/29FC1/29FC1/29 I-U I/O Channel Ready is negated to extend the host transfer cycle of any host register access (read or write) when the device is not ready to respond to a data transfer request. In Ultra DMA mode this pin is used for Ultra DMA Ready (DDMARDY#) and Ultra DMA Data Strobe (DSTROBE).

RESET#RESET#RESET#RESET# FC1/2FC1/2FC1/2FC1/2 O-TP Hardware Reset is used by the host to reset the device.

Table 2-10 E-IDE Interface Signals




Figure 2-8 IDE2 Function Module Schematic




2.4.4 FDD STX Interface supports one or two standard floppy disk drives.

Signal Pin Type Description DENSELDENSELDENSELDENSEL J2/59J2/59J2/59J2/59 O-TP Density Select indicates whether a high density data rate (500 Kbps

or 1 Mbps) or a low density data rate (250 or 300 Kbps) is selected.DIR#DIR#DIR#DIR# J2/71J2/71J2/71J2/71 O-TP Direction signal determines the direction of the FDD head movement

(active=step in, inactive=step out) during a seek operation. During reads or writes, DIR# is inactive.

DR0#DR0#DR0#DR0# J2/67J2/67J2/67J2/67

DR1#DR1#DR1#DR1# J2/65J2/65J2/65J2/65

O-TP Drive Select 1 and 0 signals are the decoded drive select output signals.

DSKCHG#DSKCHG#DSKCHG#DSKCHG# J2/87J2/87J2/87J2/87 I-U Disk Change indicates whether or not the drive door has been opened.

HDSEL#HDSEL#HDSEL#HDSEL# J2/85J2/85J2/85J2/85 O-TP Head Select determines which side of the FDD is accessed. Active low selects side 1, inactive selects side 0.

INDEX#INDEX#INDEX#INDEX# J2/61J2/61J2/61J2/61 I-U Index indicates the beginning of a FDD track. MTR0#MTR0#MTR0#MTR0# J2/63J2/63J2/63J2/63

MTR1#MTR1#MTR1#MTR1# J2/69J2/69J2/69J2/69

O-TP Motor Select 1 and 0 motor enable lines for drives 1 and 0 respectively.

RDATA#RDATA#RDATA#RDATA# J2/83J2/83J2/83J2/83 I-U Read Data holds raw serial data read from the FDD. STEP#STEP#STEP#STEP# J2/73J2/73J2/73J2/73 O-TP Step signal issues pulses to the disk drive at a programmable rate to

move the head during a seek operation. TRK0#TRK0#TRK0#TRK0# J2/79J2/79J2/79J2/79 I-U Track 0 indicates to the controller that the head of the selected

floppy disk drive is at track 0. WDATA#WDATA#WDATA#WDATA# J2/75J2/75J2/75J2/75 O-TP Write Data holds the write precompensated serial data that is written

to the selected floppy disk drive. WGATE#WGATE#WGATE#WGATE# J2/77J2/77J2/77J2/77 O-TP Write Gate enables the write circuitry of the selected disk drive. WP#WP#WP#WP# J2/81J2/81J2/81J2/81 I-U Write Protected indicates that the disk in the selected drive is writing

protected.

Table 2-11 Floppy Disk Drive Interface Signals




2.4.4.1 FDD Function Module The standard STX interface supports one or two standard floppy disk drive. The following diagram shows the proper design layout of all circuitry when defining the FDD function module.

Figure 2-9 FDD Function Module Schematic




2.4.5 PPI STX Interface supports one parallel port to connect to printers, mass storage units and other devices.

Signal Pin Type Description ACK#ACK#ACK#ACK# J2/117J2/117J2/117J2/117 I-U Acknowledge signal is pulsed low by the printer to indicate that it has

received data from the parallel port. AFD#AFD#AFD#AFD# J2/93J2/93J2/93J2/93 O-U Automatic Feed forces the printer to automatically feed a line after

printing each line. BUSYBUSYBUSYBUSY J2/119J2/119J2/119J2/119 I-U Busy is set high by the printer when it cannot accept another

character. ERR#ERR#ERR#ERR# J2/97J2/97J2/97J2/97 I-U Error is set active low by the printer when it has detected an error. INIT#INIT#INIT#INIT# J2/101J2/101J2/101J2/101 O-U Initialize causes the printer to be initialized when this signal is low. PD0PD0PD0PD0 J2/95J2/95J2/95J2/95

PD1PD1PD1PD1 J2/99J2/99J2/99J2/99

PD2PD2PD2PD2 J2/103J2/103J2/103J2/103

PD3PD3PD3PD3 J2/107J2/107J2/107J2/107

PD4PD4PD4PD4 J2/109J2/109J2/109J2/109

PD5PD5PD5PD5 J2/111J2/111J2/111J2/111

PD6PD6PD6PD6 J2/113J2/113J2/113J2/113

PD7PD7PD7PD7 J2/115J2/115J2/115J2/115

B-U PPI Data transfer data from the appropriate parallel port data register to the peripheral data bus. Can be configured as a bi-directional bus also.

PEPEPEPE J2/121J2/121J2/121J2/121 I-U Paper End is set high by the printer when it is out of paper. SLCTSLCTSLCTSLCT J2/123J2/123J2/123J2/123 I-U Select is set active high by the printer when the printer is selected. SLIN#SLIN#SLIN#SLIN# J2/105J2/105J2/105J2/105 O-U Select Input selects the printer when this signal is low. STB#STB#STB#STB# J2/91J2/91J2/91J2/91 O-U Data Strobe indicates to the printer that valid data is available at the

printer port.

Table 2-12 PPI Interface Signals

2.4.5.1 PPI Function Module STX Interface supports one parallel port to connect to printers, mass storage and other device. The following diagram shows the proper design layout of all circuitry when defining the PPI function module.




Figure 2-10 PPI Function Module Schematic




2.4.6 SPI 1,2 Serial port interface on the STX Interface is TTL-level only. STX Baseboard can convert the SPI to RS-232, RS-485 or other protocols depending on application needs.

Signal Pin Type Description CTS1# J2/139 I-U Clear to Send indicates that the modem or other data transfer device is

ready to exchange data. DCD1# J2/127 I-U Data Carrier Detected indicates that the modem or other data transfer

device has detected the data carrier. DSR1# J2/135 I-U Data Set Ready indicates that the data transfer device, e.g. modem, is

ready to establish a communications link. DTR1# J2/133 O-TP Data Terminal Ready indicates to the modem or other data transfer

device that the corresponding UART is ready to establish a communications link.

RI1# J2/141 I-U Ring Indicator indicates that a telephone ring signal has been received by the modem.

RTS1# J2/137 O-TP Request to Send indicates to the modem or other data transfer device that the corresponding UART is ready to exchange data.

SIN1 J2/129 I-U Serial Input receives composite serial data from the communications link (peripheral device, modem or other data transfer device).

SOUT1 J2/131 O-TP Serial Output sends composite serial data to the communications link (peripheral device, modem or other data transfer device).

Table 2-13 SPI 1 Interface Signals

Signal Pin Type Description CTS2# J2/155 I-U Clear to Send indicates that the modem or other data transfer device is

ready to exchange data. DCD2# J2/143 I-U Data Carrier Detected indicates that the modem or other data transfer

device has detected the data carrier. DSR2# J2/151 I-U Data Set Ready indicates that the data transfer device, e.g. modem, is

ready to establish a communications link. DTR2# J2/149 O-TP Data Terminal Ready indicates to the modem or other data transfer

device that the corresponding UART is ready to establish a communications link.

RI2# J2/157 I-U Ring Indicator indicates that a telephone ring signal has been received by the modem.

RTS2# J2/153 O-TP Request to Send indicates to the modem or other data transfer device that the corresponding UART is ready to exchange data.

SIN2 J2/145 I-U Serial Input receives composite serial data from the communications link (peripheral device, modem or other data transfer device).

SOUT2 J2/147 O-TP Serial Output sends composite serial data to the communications link (peripheral device, modem or other data transfer device).

Table 2-14 SPI 2 Interface Signals




2.4.6.1 SPI 1,2 Function Modules Serial port interface on the STX interface is TTL-level only. STX Baseboard can convert the SPI to RS-232, RS-485 or protocols based on application needs. The following diagram shows the proper design layout of all circuitry when defining the SPI 1,2 function modules.




Note: The resistor reserved for IBSmm STX module. Because need the design to setting I/O address. If use the Axiomtek STX module doesn’t need it. Figure 2-11 SPI 1,2 Function Module Schematic




2.4.7 IrDA Supported IrDA protocols are not a part of this STX Hardware Specification, see datasheet of the particular STX Module.

Signal Pin Type Description IR_RXIR_RXIR_RXIR_RX J1/38J1/38J1/38J1/38 I-U Infrared Reception is used for infrared serial input data. IR_TXIR_TXIR_TXIR_TX J1/40J1/40J1/40J1/40 O-TP Infrared Transmit is used for infrared serial output data.

Table 2-15 IrDA Interface Signals

2.4.8 KB/MS STX Interface supports standard AT- and PS/2-style keyboards and PS/2-style pointing devices (mouse, touchpad etc.)

Signal Pin Type Description KBCLKKBCLKKBCLKKBCLK J1/21J1/21J1/21J1/21 B-OD-U Keyboard Clock transfers the keyboard clock between the keyboard controller and

the keyboard using the PS/2 protocol. KBDATAKBDATAKBDATAKBDATA J1/23J1/23J1/23J1/23 B-OD-U Keyboard Data transfers the keyboard data between the keyboard controller and

the keyboard using the PS/2 protocol. MSCLKMSCLKMSCLKMSCLK J1/25J1/25J1/25J1/25 B-OD-U Mouse Clock transfers the mouse clock between the controller and the pointing

device using the PS/2 protocol. MSDATAMSDATAMSDATAMSDATA J1/27J1/27J1/27J1/27 B-OD-U Mouse Data transfers the mouse data between the controller and the pointing

device using the PS/2 protocol.

Table 2-16 Keyboard and Mouse Signals

2.4.8.1 KB/MS Function Module The standard STX interface supports AT- and PS/2- type keyboard and PS/2-type pointing devices (mouse, touchpad etc.). The following diagram shows the proper design layout of all circuitry when defining the keyboard and mouse function module.




Figure 2-12 Keyboard and Mouse Function Module Schematic




2.4.9 USB 1&2 STX Interface supports two USB ports. Both USB ports have over-current detection so they can signal to the application software that over-current condition appeared on the particular USB port.

Signal Pin Type Description USB1_NUSB1_NUSB1_NUSB1_N

J2/161J2/161J2/161J2/161

USB1_PUSB1_PUSB1_PUSB1_P J2/163J2/163J2/163J2/163

B Universal Serial Bus Port signal pair comprises the differential data signals (positive and negative) for USB port. Required 15 K pull-down resistors have to be implemented on the STX Baseboard even if USB port is not used.

USB1_OC#USB1_OC#USB1_OC#USB1_OC# J2/173J2/173J2/173J2/173 I-U Over current Detect is used to monitor the status of the USB power supply lines. USB2_NUSB2_NUSB2_NUSB2_N

J2/167J2/167J2/167J2/167

USB2_PUSB2_PUSB2_PUSB2_P J2/169J2/169J2/169J2/169

B Universal Serial Bus Port signal pair comprises the differential data signals (positive and negative) for USB port. Required 15 K pull-down resistors have to be implemented on the STX Baseboard even if USB port is not used.

USB2_OC#USB2_OC#USB2_OC#USB2_OC# J2/175J2/175J2/175J2/175 I-U Over current Detect is used to monitor the status of the USB power supply lines.

Table 2-17 Universal Serial Bus 1 Interface Signals

2.4.9.1 USB 1&2 Function Module STX interface supports two USB ports. AXIOMTEK STX module, however, can support four USB ports. The following diagram shows the proper design layout of all circuitry when defining the USB 1&2 function module.




Figure 2-13 USB 1&2 Function Module Schematic




2.4.10 USB 3&4

Signal Pin Type Description USB 3_NUSB 3_NUSB 3_NUSB 3_N J2/107J2/107J2/107J2/107

USB 3_PUSB 3_PUSB 3_PUSB 3_P J2/109J2/109J2/109J2/109

B-D Universal Serial Bus Port signal pair comprises the differential data signals (positive and negative) for USB port. Required 15 K pull-down resistors have to be implemented on the STX Baseboard even if USB port is not used.

USB 4_NUSB 4_NUSB 4_NUSB 4_N J2/113J2/113J2/113J2/113

USB 4_PUSB 4_PUSB 4_PUSB 4_P J2/111J2/111J2/111J2/111

B-D Universal Serial Bus Port signal pair comprises the differential data signals (positive and negative) for USB port. Required 15 K pull-down resistors have to be implemented on the STX Baseboard even if USB port is not used.

Table 2-18 Universal Serial Bus 3&4 Interface Signals

2.4.10.1 USB 3&4 Function Module

Figure 2-14 USB 3&4 Function Module Schematic




2.4.11 ETH STX Interface supports standard 10/100Mbit Ethernet interface. Note that net isolation transformer is not present on STX Module.

Signal Pin Type Description NET_GNDNET_GNDNET_GNDNET_GND J1/12J1/12J1/12J1/12 DC Network Ground should be used for termination circuitry and for the transformer

center tap bypassing. NET_RX_NNET_RX_NNET_RX_NNET_RX_N J1/10J1/10J1/10J1/10

NET_RX_PNET_RX_PNET_RX_PNET_RX_P J1/8J1/8J1/8J1/8

I Receive Data is analog twisted pair Ethernet differential input pair (positive and negative) that can be configured to accept either 100BASE-TX or 10BASE-T signaling. These signals interface directly that an isolation transformer.

NET_TX_NNET_TX_NNET_TX_NNET_TX_N J1/4J1/4J1/4J1/4

NET_TX_PNET_TX_PNET_TX_PNET_TX_P J1/2J1/2J1/2J1/2

O-A Transmit Data is analog twisted pair Ethernet differential pair (positive and negative) which is configurable to either 10BASE-T or 100BASE-TX signaling. These signals interface directly with an isolation transformer.

NET_TX_CTNET_TX_CTNET_TX_CTNET_TX_CT J1/6J1/6J1/6J1/6 DC TX Center Tap pin should be connected to TX center tap of isolation transformer.

Table 2-19 Ethernet 10/100Mbit Interface Signals

2.4.11.1 ETH Function Module STX interface supports standard 10/100Mbit Ethernet interface. Note that net isolation transformer is not present on STX Module. The following diagram shows the proper design layout of all circuitry when defining the ETH function module.




Note1: These components are option for signal terminator. If use Axiomtek STX module doesn’t place these component. Note2: The capacitor is option base on the transformer. Figure 2-15 ETH Function Module Schematic




2.4.12 AC’97 STX Interface features AC’97 interface to connect to the AC’97-compatible codec on STX Baseboard. See particular STX Module datasheet for list of the supported AC’97 codes.

Signal Pin Type Description AC97_RST#AC97_RST#AC97_RST#AC97_RST# J1/20J1/20J1/20J1/20 O-TP Reset initializes all AC’97 logic (including registers) to its default state. BIT_CLKBIT_CLKBIT_CLKBIT_CLK J1/24J1/24J1/24J1/24 I-U Serial Bit Clock is 12.288 MHz serial data clock providing clocking

granularity. SDATA_INSDATA_INSDATA_INSDATA_IN J1/22J1/22J1/22J1/22 I-U Serial Data In transfers the time division multiplexed AC’97 output stream.SDATA_OUTSDATA_OUTSDATA_OUTSDATA_OUT J1/26J1/26J1/26J1/26 O-TP Serial Data Out transfers the time division multiplexed AC’97 input stream.SYNCSYNCSYNCSYNC J1/28J1/28J1/28J1/28 O-TP Synchronization is 48 kHz fixed rate sample synchronization signal.

Table 2-20 Audio Codec ‘97 Interface Signals

2.4.12.1 AC’97 Function Module STX Interface features AC’97 interface to connect to an AC’97 compatible codec onto the STX Baseboard.

AC’97 An AC’97 Controller is in the Southbridge of the STX module. AC-link is a digital serial link between the AC’97 Controller and AC’97 devices. For more details, refer to the AC’97 Component Specification Revision 2.1.

Audio Codec Design The reference Design of VT1612A Audio Codec is available at http://www.via.com.tw/.

The following diagram shows the proper design layout of all circuitry when defining the AX’97 function module.

http://www.via.com.tw/




Figure 2-16 AC’97 Function Module Schematic




2.4.13 CRT STX Interface support standard CRT interface for connecting CRT monitors or analog flat panels.

Signal Pin Type Description CRT_BCRT_BCRT_BCRT_B J2/191J2/191J2/191J2/191 O-A Analog DAC Blue drives the blue signal of the CRT monitor. CRT_GCRT_GCRT_GCRT_G J2/183J2/183J2/183J2/183 O-A Analog DAC Green drives the green signal of the CRT monitor. CRT_GNDCRT_GNDCRT_GNDCRT_GND J2/185J2/185J2/185J2/185

J2/189J2/189J2/189J2/189

DC CRT Ground is analog ground dedicated to the RGB analog signals on CRT monitors.

CRT_HSCRT_HSCRT_HSCRT_HS J2/199J2/199J2/199J2/199 O-TP Horizontal Sync provides the horizontal synchronization pulses for the CRTmonitor.

CRT_RCRT_RCRT_RCRT_R J2/187J2/187J2/187J2/187 O-A Analog DAC Red drives the red signal of the CRT monitor. CRT_VSCRT_VSCRT_VSCRT_VS J2/195J2/195J2/195J2/195 O-TP Vertical Sync provides the vertical synchronization pulses for the CRT monitor.DDC_SCLDDC_SCLDDC_SCLDDC_SCL J2/177J2/177J2/177J2/177 O-OD-U DDC Clock transfers the DDC clock between the graphics controller and the

CRT monitor using the VESA DDC protocol. DDC_SDADDC_SDADDC_SDADDC_SDA J2/179J2/179J2/179J2/179 B-OD-U DDC Data transfers the DDC data between the graphics controller and the

CRT monitor using the VESA DDC protocol.

Table 2-21 CRT Interface Signals

2.4.13.1 CRT Function Module STX Inter face supports standard CRT interface for connecting CRT monitors or analog flat panels.

� Analog R,G, and B traces should be designed to be as short as possible.

� The RGB output is current source and therefore require 75 ohm load resistor from each rgb line to CRT_GND to create the output voltage (approximately 0 to 0.7 volts).

� The trace of CRT_GND surrounding the RGB lines and their RLC components should be at lease 15 mil wide and spaced away from outside signal as much as possible.

� The connection between CRT_GND and digital ground should be a ferrite bead.

The following diagram shows the proper design layout of all circuitry when defining the CRT function module.




Figure 2-17 CRT Function Module Schematic




2.4.14 FPI & TV-Out Flat Panel Interface directly supports TTL-level flat panels and converters from TTL to other interfaces (LVDS, Panel Link etc.).

Signal Pin Type Description FP_BKL_ENFP_BKL_ENFP_BKL_ENFP_BKL_EN J1/156J1/156J1/156J1/156 O-TP Back Light Enable controls the flat panel back light converter power. FP_BSELFP_BSELFP_BSELFP_BSEL J1/165J1/165J1/165J1/165 O-TP Bus Select indicates used data bus type (24-bit mode when high, 12-bit mode

when low) FP_CLK_PFP_CLK_PFP_CLK_PFP_CLK_P J1/164J1/164J1/164J1/164 O-TP Clock Primary is used to latch the pixel data in both 24-bit and 12-bit mode. FP_CLK_SFP_CLK_SFP_CLK_SFP_CLK_S J1/168J1/168J1/168J1/168 O-TP Clock Secondary is used to latch of the high half pixel in 12-bit mode when

dual edge clocking is turned off. In all other modes this signal is unused and driven low.

FPFPFPFP_D0_D0_D0_D0 J1/171J1/171J1/171J1/171

FP_D1FP_D1FP_D1FP_D1 J1/173J1/173J1/173J1/173











FP_D12FP_D12FP_D12FP_D12 J1J1J1J1/172/172/172/172












O-TP Flat Panel Data transfers the flat panel pixel data. FP_D[23..12] is used for top half of 24-bit pixel data in 24-bit mode, and it is driven low in 12-bit mode. FP_D[11..00] is used for bottom half of 24-bit pixel data in 24-bit mode, and contains multiplexed low and high half of pixel data in 12-bit mode.

FP_DEFP_DEFP_DEFP_DE J1/167J1/167J1/167J1/167 O-TP Data Enable signal is high when pixel data is valid for the flat panel and low otherwise.




FP_DSELFP_DSELFP_DSELFP_DSEL J1/161J1/161J1/161J1/161 O-TP Dual Edge Clock Select indicates usage of secondary clock FP_CLK_S to latch pixel data. In 12-bit mode is FP_CLK_P used to latch data on both falling and rising edges when FP_DSEL is high, while FP_CLK_P latches low half data and FP_CLK_S latches high half data when FP_DSEL is low. In 24-bit mode is always driven low.

FP_EDGEFP_EDGEFP_EDGEFP_EDGE J1/158J1/158J1/158J1/158 O-TP Edge Type Select determines the clock edge that will latch the data. In single edge mode (FP_DSEL is low) the falling edge of the clock is used when FP_EDGE is low and the rising one is used when FP_EDGE is high. In dual edge mode (FP_DSEL is high) the primary edge (first latch edge after FP_DE is asserted) is the falling edge when FP_EDGE is low and the primary edge is the rising one when FP_EDGE is high.

FP_HSYNCFP_HSYNCFP_HSYNCFP_HSYNC J1/160J1/160J1/160J1/160 O-TP Horizontal Sync provides the horizontal synchronization pulses for the flat panel.

FP_VDD_ENFP_VDD_ENFP_VDD_ENFP_VDD_EN J1/163J1/163J1/163J1/163 O-TP Flat Panel VDD Enable controls the flat panel digital power. FP_VSYNCFP_VSYNCFP_VSYNCFP_VSYNC J1/159J1/159J1/159J1/159 O-TP Vertical Sync provides the vertical synchronization pulses for the flat panel. FP_SCLFP_SCLFP_SCLFP_SCL J1/149J1/149J1/149J1/149 O-OD-U Flat Panel DDC Clock transfers the DDC clock between the graphics

controller and the flat panel monitor using the VESA DDC protocol. FP_SDAFP_SDAFP_SDAFP_SDA J1/150J1/150J1/150J1/150 B-OD-U Flat Panel DDC Data transfers the DDC data between the graphics controller

and the flat panel monitor using the VESA DDC protocol.

Table 2-22 Flat Panel Interface Signals

Signal Pin Type Description ZVD0 FC2/3 I-TP ZVD1 FC2/4 I-TP ZVD2 FC2/5 I-TP ZVD3 FC2/6 I-TP ZVD4 FC2/7 I-TP ZVD5 FC2/8 I-TP ZVD6 FC2/9 I-TP ZVD7 FC2/10 I-TP ZVD8 FC2/13 I-TP ZVD9 FC2/14 I-TP ZVD10 FC2/15 I-TP ZVD11 FC2/16 I-TP

Video RGB data from video encoder.

Continued . . . . .

Signal Pin Type Description ZVD12ZVD12ZVD12ZVD12 FC2/17FC2/17FC2/17FC2/17 I-TP




ZVD13ZVD13ZVD13ZVD13 FC2/18FC2/18FC2/18FC2/18 I-TP ZVD14ZVD14ZVD14ZVD14 FC2/19FC2/19FC2/19FC2/19 I-TP ZVD15ZVD15ZVD15ZVD15 FC2/20FC2/20FC2/20FC2/20 I-TP

ZVREFZVREFZVREFZVREF FC2/23FC2/23FC2/23FC2/23 I-TP VSYNC input from video decoder ZVSZVSZVSZVS FC2/24FC2/24FC2/24FC2/24 I-TP HSYNC input from video decoder ZVCLKZVCLKZVCLKZVCLK FC2/25FC2/25FC2/25FC2/25 I-TP Pixel Clock FPD24(TVD6)FPD24(TVD6)FPD24(TVD6)FPD24(TVD6) FC2/27FC2/27FC2/27FC2/27 O-TP FPD25(TVD4)FPD25(TVD4)FPD25(TVD4)FPD25(TVD4) FC2/28FC2/28FC2/28FC2/28 O-TP FPD26(TVD5)FPD26(TVD5)FPD26(TVD5)FPD26(TVD5) FC2/29FC2/29FC2/29FC2/29 O-TP FPD27(TVD7)FPD27(TVD7)FPD27(TVD7)FPD27(TVD7) FFFFC2/30C2/30C2/30C2/30 O-TP FPD28(TVD0)FPD28(TVD0)FPD28(TVD0)FPD28(TVD0) FC2/31FC2/31FC2/31FC2/31 O-TP FPD29(TVD1)FPD29(TVD1)FPD29(TVD1)FPD29(TVD1) FC2/32FC2/32FC2/32FC2/32 O-TP FPD30(TVD3)FPD30(TVD3)FPD30(TVD3)FPD30(TVD3) FC2/34FC2/34FC2/34FC2/34 O-TP

Multifunction Pin: 1. Panel Data for 36 Bit TFT LCD. Internally pulled down

during reset. 8 mA is the default. 16mA is selected. 2. TV data RGBdata is output at one pixel/clock. Internally

pulled down during reset.

FPD31(TVVS)FPD31(TVVS)FPD31(TVVS)FPD31(TVVS) FC2/35FC2/35FC2/35FC2/35 O-TP Multifunction Pin: 1. Panel Data for 36 Bit tft LCD. Internally pulled down

during reset. 8 mA is the default. 16mA is selected 2. TV VSYNC. Internally pulled down during reset.

FPD32(TVCLK)FPD32(TVCLK)FPD32(TVCLK)FPD32(TVCLK) FC2/36FC2/36FC2/36FC2/36 O-TP Multifunction Pin: 1. Panel Data for 36 Bit TFT LCD. Internally pulled down

during reset. 8 mA is the default. 16mA is selected 2. TV clock. Output clock to TV encoder. Internally pulled

down during reset. FPD33(TVD2)FPD33(TVD2)FPD33(TVD2)FPD33(TVD2) FC2/37FC2/37FC2/37FC2/37 O-TP Multifunction Pin:

1. Panel Data for 36 Bit TFT LCD. Internally pulled down during reset. 8 mA is the default. 16mA is selected.

2. TV data RGB data is output at one pixel/clock. Internally pulled down during reset.

FPD34(TVHS)FPD34(TVHS)FPD34(TVHS)FPD34(TVHS) FC2/38FC2/38FC2/38FC2/38 O-TP Multifunction Pin: 1. Panel Data for 36 bit TFT LCD. Internally pulled down

during reset. 8 mA is the default. 16mA is selected 2. TV HSYNC. Output clock to TV encoder. Internally pulled

down during reset. FPD35FPD35FPD35FPD35 FC2/39FC2/39FC2/39FC2/39 O-TP Panel Data for 36 bit TFT LCD. Internally pulled down during

reset. 8 mA is the default. 16mA is selected

Table 2-23 FC2 Connector Pinout




2.4.14.1 FPI & TV-Out Function Module Flat Panel Interface directly supports TTL-Level flat panels and converters from TTL to other interfaces (LVDS, Panel Link etc.) AXIOMTEK STX module increased the FC2 connector features to provide TV-out and panel interface upgrade capabilities into 36 bits. The following diagram shows the proper design layout of all circuitry when defining the FPI function module.

Figure 2-18 FPI Function Module Schematic

TV-Out Function Module You may visit to http://www.chrontel.com/ for related details on CH7006. The following diagram shows the proper design layout of all circuitry when defining the TC-Out function module.

http://www.chrontel.com/




Figure 2-19 TV-Out Function Module Schematic




2.4.15 FEAT Feature signals provide standard functionality of common motherboard's feature connector (signaling LEDs, keylock, reset and power buttons etc.).

Signal Pin Type Description ACT_LED#ACT_LED#ACT_LED#ACT_LED# J1/3J1/3J1/3J1/3 O-TP Ethernet TX/RX Activity is driven low to indicate active transmission or

reception, and can be used to drive a LED. The activity event is stretched to a minimum duration to be always visible.

DSK_LED#DSK_LED#DSK_LED#DSK_LED# J1/7J1/7J1/7J1/7 O-OD STX Module On-board Disk Activity is driven low to indicate that an on-board disk is active. It does not indicate activity on STX E-IDE interface; however external disk activity signal can be wired-OR with DSK_LED# if needed.

KBD_LOCK#KBD_LOCK#KBD_LOCK#KBD_LOCK# J1/11J1/11J1/11J1/11 I-U Keyboard Lock inhibits keyboard interface. LNK_LED#LNK_LED#LNK_LED#LNK_LED# J1/5J1/5J1/5J1/5 O-TP Ethernet 10/100Mbit/s Link is driven low to indicate Good Link status for 10

Mbit/s or 100 Mbit/s operation and can be used to drive a LED. PWR_BTN#PWR_BTN#PWR_BTN#PWR_BTN# J1/15J1/15J1/15J1/15 I-U Power Button input signal is used by power management logic to monitor

external system events, typically a front panel on/off button. RST_BTN#RST_BTN#RST_BTN#RST_BTN# J1/13J1/13J1/13J1/13 I-U Reset Button input signal is used as an external reset signal from front panel

button or external system supervisor. SPEAKERSPEAKERSPEAKERSPEAKER J1/9J1/9J1/9J1/9 O-TP Speaker output signal drives an external speaker device.

Table 2-24 Feature Signals

2.4.15.1 FEAT Function Module Feature signals provide standard functionality of common motherboard’s feature connector.

ACT_LED# Ethernet TX/RX Activity is driven low to indicate active transmission or reception, and can be used to drive a LED.

LNK_LED# Ethernet 10/100Mbit/s Link is driven low to indicate Good Link status for 10 Mbit/s or 100Mbit/s operation and can be used to drive a LED.

DSK_LED# It does not indicate activity on STX E-IDE interface, however external disk activity signal can be wired-or with DSK_LED# if needed.

SPEAKER Speaker out signal drives an external speaker device or buzzer.

KBD_LOCK# Keyboard Lock inhibits keyboard interface. Axiomtek STX module can’t support this function.




RST_BTN# Reset Button input signal is used as an external reset signal from front panel button or external system supervisor.

PWR_BTN# Power Button input signal is used by power management logic to monitor external system events, typically a front on/off button.

2.4.16 MISC Miscellaneous signals are most commonly used for hardware monitoring and system and power management.

Signal Pin Type Description CPU_TD_NCPU_TD_NCPU_TD_NCPU_TD_N J1/37J1/37J1/37J1/37

CPU_TD_PCPU_TD_PCPU_TD_PCPU_TD_P J1/35J1/35J1/35J1/35

O-A CPU Thermal Diode may be used to monitor the die temperature of the CPU for thermal management purposes. CPU_TD_P is connected to diode anode (P junction) and CPU_TD_N is connected to diode cathode (N junction).

EXT_SMI#EXT_SMI#EXT_SMI#EXT_SMI# J1/31J1/31J1/31J1/31 I-U External SMI Interrupt can be asserted by external logic to enter System Management Mode (SMM).

I2C_SCLI2C_SCLI2C_SCLI2C_SCL J1/32J1/32J1/32J1/32 O-OD-U I2C Clock transfers the clock between the I2C controller and the external device using the I2C protocol.

I2C_SDAI2C_SDAI2C_SDAI2C_SDA J1/34J1/34J1/34J1/34 B-OD-U I2C Data transfers the data between the I2C controller and the external device using the I2C protocol.

PS_ON#PS_ON#PS_ON#PS_ON# J1/18J1/18J1/18J1/18 O-OD Power Supply On turns on all the main power rails when active. Typically it is used for ATX power supply control.

V_COREV_COREV_COREV_CORE J1/42J1/42J1/42J1/42 O-A CPU Core Voltage can be monitored by the external HW monitor or system supervisor.

WUEWUEWUEWUE J1/17J1/17J1/17J1/17 I-U Wake-Up Event indicates that external wake-up event has occurred. This may cause the chipset to turn the power supply on, or to exit its current sleep state. The exact behavior (edge, level or pulse-train detection) can be programmed by software.

Table 2-25 Miscellaneous Signals




2.4.17 JTAG JTAG interface is used for manufacturing purposes. Input voltages are defined by pull-up/down resistors on the STX Module and should be left unconnected on the STX Baseboard.

2.4.17.1 JTAG Design Notes JTAG interface is used for manufacturing purposes only. AXIOMTEK STX module does not support this function.

2.4.18 PWR Power pins provide required power supply to the STX Module as well as AC return path for signals. Therefore, all the power pins have to be connected.

Signal Type Description GNDGNDGNDGND DCDCDCDC Digital ground V_BATV_BATV_BATV_BAT DCDCDCDC Backup battery cell voltage (typically 3V) for maintaining RTC and

CMOS functionality during the absence of power. V_SBV_SBV_SBV_SB DCDCDCDC +5V standby voltage for suspend and wake-up logic. Shall be left

unconnected if not used. VCCVCCVCCVCC DCDCDCDC +5V power supply VCC3VCC3VCC3VCC3 DCDCDCDC +3.3V power supply

Table 2-26 Power and Ground Pins

VCC & VCC3 STX Module requires both 5V & 3.3V power supply. The maximum current for VCC & VCC3 is 3.5A on any STX Module.

V_SB STX Module requires 5V for standby power. Typically it connects to ATX power.




Battery STX Module needs a battery to maintain operation of the Real-Time-Clock in power off state. The designer should choose a battery voltage between 2.2V~3.6V.Axiomtek used the Panasonic CR-2030 battery on the STX Baseboard.

2.4.20 Reserved Pins marked as RSVD are reserved for future use and must be left unconnected.

2.5 Pin Definitions In this section are described all used signals, their positions on STX Interface and their group classification.

2.5.1 P1/J1 Connector Pin out The following table shows pins arrangement of either P1 plug (used on STX Module) or J1 receptacle (used on STX Baseboard).

Pin Name Group Pin Name Group 1 GND PWR 2 NET_TX_P ETH 3 ACT_LED# FEAT 4 NET_TX_N ETH 5 LNK_LED# FEAT 6 NET_TX_CT ETH 7 DSK_LED# FEAT 8 NET_RX_P ETH 9 SPEAKER FEAT 10 NET_RX_N ETH 11 KBD_LOCK# FEAT 12 NET_GND ETH 13 RST_BTN# FEAT 14 V_SB PWR 15 PWR_BTN# FEAT 16 V_SB PWR 17 WUE MISC 18 PS_ON# MISC 19 GND PWR 20 AC97_RST# AC’97 21 KBCLK KB/MS 22 SDATA_IN AC’97 23 KBDATA KB/MS 24 BIT_CLK AC’97 25 MSCLK KB/MS 26 SDATA_OUT AC’97 27 MSDATA KB/MS 28 SYNC AC’97 29 VCC PWR 30 GND PWR 31 EXT_SMI# MISC 32 I2C_SCL MISC 33 EXT_BIOS# MISC 34 I2C_SDA MISC 35 CPU_TD_P MISC 36 GND PWR 37 CPU_TD_N MISC 38 IR_RX IrDA 39 V_BAT PWR 40 IR_TX IrDA

Continued. . . . .




Pin Name Group Pin Name Group 41 VCC PWR 42 V_CORE MISC 43 AD0 PCI 44 VCC PWR 45 AD1 PCI 46 VCC PWR 47 VCC PWR 48 AD2 PCI 49 AD4 PCI 50 AD5 PCI 51 AD3 PCI 52 GND PWR 53 GND PWR 54 C/BE0# PCI 55 AD6 PCI 56 AD7 PCI 57 AD8 PCI 58 GND PWR 59 GND PWR 60 AD9 PCI 61 AD10 PCI 62 AD11 PCI 63 VCC3 PWR 64 VCC3 PWR 65 — RSVD 66 AD14 PCI 67 AD12 PCI 68 AD13 PCI 69 AD15 PCI 70 VCC3 PWR 71 VCC3 PWR 72 C/BE1# PCI 73 VCC3 PWR 74 SERR# PCI 75 PAR PCI 76 GND PWR 77 GND PWR 78 GND PWR 79 GND PWR 80 PERR# PCI 81 LOCK# PCI 82 STOP# PCI 83 VCC3 PWR 84 VCC3 PWR 85 VCC3 PWR 86 VCC3 PWR 87 DEVSEL# PCI 88 TRDY# PCI 89 IRDY# PCI 90 FRAME# PCI 91 GND PWR 92 GND PWR 93 GND PWR 94 GND PWR 95 C/BE2# PCI 96 AD16 PCI 97 AD17 PCI 98 AD18 PCI 99 VCC3 PWR 100 VCC3 PWR 101 VCC3 PWR 102 AD21 PCI 103 AD19 PCI 104 AD20 PCI 105 AD22 PCI 106 VCC3 PWR 107 TRST# JTAG 108 AD23 PCI

Continued. . . . .




Pin Name Group Pin Name Group 109 TCK JTAG 110 — RSVD 111 TDI JTAG 112 GND PWR 113 TMS JTAG 114 AD24 PCI 115 TDO JTAG 116 C/BE3# PCI 117 AD25 PCI 118 GND PWR 119 GND PWR 120 AD26 PCI 121 AD28 PCI 122 AD29 PCI 123 AD27 PCI 124 VCC3 PWR 125 VCC3 PWR 126 VCC3 PWR 127 AD31 PCI 128 REQ1# PCI 129 AD30 PCI 130 REQ0# PCI 131 VCC PWR 132 VCC PWR 133 VCC PWR 134 VCC PWR 135 GNT0# PCI 136 GNT2# PCI 137 REQ2# PCI 138 GNT1# PCI 139 GND PWR 140 GND PWR 141 CLK1 PCI 142 GND PWR 143 GND PWR 144 CLK2 PCI 145 CLK0 PCI 146 VCC PWR 147 VCC PWR 148 __ RSVD 149 FP_SCL FPI 150 FP_SDA FPI 151 RST# PCI 152 INTD# PCI 153 INTC# PCI 154 INTA# PCI 155 INTB# PCI 156 FP_BKL_EN FPI 157 GND PWR 158 FP_EDGE FPI 159 FP_VSYNC FPI 160 FP_HSYNC FPI 161 FP_DSEL FPI 162 GND PWR 163 FP_VDD_EN FPI 164 FP_CLK_P FPI 165 FP_BSEL FPI 166 GND PWR 167 FP_DE FPI 168 FP_CLK_S FPI 169 VCC PWR 170 VCC PWR 171 FP_D0 FPI 172 FP_D12 FPI 173 FP_D1 FPI 174 FP_D13 FPI 175 FP_D2 FPI 176 GND PWR

Continued . . . . .




Pin Name Group Pin Name Group 177 FP_D3 FPI 178 FP_D14 FPI 179 GND PWR 180 FP_D15 FPI 181 FP_D4 FPI 182 FP_D16 FPI 183 FP_D5 FPI 184 FP_D17 FPI 185 FP_D6 FPI 186 GND PWR 187 FP_D7 FPI 188 FP_D18 FPI 189 GND PWR 190 FP_D19 FPI 191 FP_D8 FPI 192 FP_D20 FPI 193 FP_D9 FPI 194 FP_D21 FPI 195 FP_D10 FPI 196 GND PWR 197 FP_D11 FPI 198 FP_D22 FPI 199 GND PWR 200 FP_D23 FPI

Table 2-27 STX P1 / J1 Connector Pin out

2.5.2 P2/J2 Connector Pin out The following table shows pins arrangement of either P2 plug (used on STX Module) or J2 receptacle (used on STX Baseboard).

Pin Signal Name Group Pin Signal Name Group 1 RESET# E-IDE 2 GND PWR 3 DD7 E-IDE 4 IOCHCHK# ISA 5 DD8 E-IDE 6 SD7 ISA 7 DD6 E-IDE 8 RESETDRV ISA 9 DD9 E-IDE 10 SD6 ISA 11 DD5 E-IDE 12 VCC PWR 13 DD10 E-IDE 14 SD5 ISA 15 DD4 E-IDE 16 IRQ9 ISA 17 DD11 E-IDE 18 SD4 ISA 19 DD3 E-IDE 20 GND PWR 21 DD12 E-IDE 22 SD3 ISA 23 DD2 E-IDE 24 DRQ2 ISA 25 DD13 E-IDE 26 SD2 ISA 27 DD1 E-IDE 28 VCC PWR 29 DD14 E-IDE 30 SD1 ISA 31 DD0 E-IDE 32 ENDXFR# ISA

Continued . . . . .




Pin Signal Name Group Pin Signal Name Group 33 DD15 E-IDE 34 SD0 ISA 35 INTRQ E-IDE 36 — RSVD 37 DMARQ E-IDE 38 — RSVD 39 DIOW# E-IDE 40 — RSVD 41 DIOR# E-IDE 42 IOCHRDY ISA 43 IORDY E-IDE 44 GND PWR 45 DMACK# E-IDE 46 MEMCS16# ISA 16 47 DA1 E-IDE 48 SBHE# ISA 16 49 DA0 E-IDE 50 AEN ISA 51 DA2 E-IDE 52 SMEMW# ISA 53 CS0# E-IDE 54 IOCS16# ISA 16 55 CS1# E-IDE 56 LA23 ISA 16 57 GND PWR 58 SA19 ISA 59 DENSEL FDD 60 SMEMR# ISA 61 INDEX# FDD 62 IRQ10 ISA 16 63 MTR0# FDD 64 LA22 ISA 16 65 DR1# FDD 66 SA18 ISA 67 DR0# FDD 68 IOW# ISA 69 MTR1# FDD 70 IRQ11 ISA 16 71 DIR# FDD 72 LA21 ISA 16 73 STEP# FDD 74 SA17 ISA 75 WDATA# FDD 76 IOR# ISA 77 WGATE# FDD 78 IRQ12 ISA 16 79 TRK0# FDD 80 LA20 ISA 16 81 WP# FDD 82 SA16 ISA 83 RDATA# FDD 84 DACK3# ISA 85 HDSEL# FDD 86 IRQ15 ISA 16 87 DSKCHG# FDD 88 LA19 ISA 16 89 GND PWR 90 SA15 ISA 91 STB# PPI 92 DRQ3 ISA 93 AFD# PPI 94 IRQ14 ISA 16 95 PD0 PPI 96 LA18 ISA 16 97 ERR# PPI 98 SA14 ISA 99 PD1 PPI 100 DACK1# ISA

Continued . . . . .




Pin Signal Name Group Pin Signal Name Group 101 INIT# PPI 102 LA17 ISA 16 103 PD2 PPI 104 DACK0# ISA 16 105 SLIN# PPI 106 DRQ1 ISA 107 PD3 PPI 108 SA13 ISA 109 PD4 PPI 110 MEMR# ISA 16 111 PD5 PPI 112 DRQ0 ISA 16 113 PD6 PPI 114 REFRESH# ISA 115 PD7 PPI 116 SA12 ISA 117 ACK# PPI 118 MEMW# ISA 16 119 BUSY PPI 120 DACK5# ISA 16 121 PE PPI 122 SYSCLK ISA 123 SLCT PPI 124 SA11 ISA 125 GND PWR 126 SD8 ISA 16 127 DCD1# SPI1 128 DRQ5 ISA 16 129 SIN1 SPI1 130 IRQ7 ISA 131 SOUT1 SPI1 132 SA10 ISA 133 DTR1# SPI1 134 SD9 ISA 16 135 DSR1# SPI1 136 DACK6# ISA 16 137 RTS1# SPI1 138 IRQ6 ISA 139 CTS1# SPI1 140 SA9 ISA 141 RI1# SPI1 142 SD10 ISA 16 143 DCD2# SPI2 144 DRQ6 ISA 16 145 SIN2 SPI2 146 IRQ5 ISA 147 SOUT2 SPI2 148 SA8 ISA 149 DTR2# SPI2 150 SD11 ISA 16 151 DSR2# SPI2 152 DACK7# ISA 16 153 RTS2# SPI2 154 IRQ4 ISA 155 CTS2# SPI2 156 SA7 ISA 157 RI2# SPI2 158 SD12 ISA 16 159 GND PWR 160 DRQ7 ISA 16 161 USB 1/ 2_N USB 1/ 2 162 IRQ3 ISA 163 USB 1/ 2_P USB 1/ 2 164 SA6 ISA 165 GND PWR 166 SD13 ISA 16 167 USB 3/4_N USB 3/4 168 VCC PWR

Continued . . . . .




Pin Signal Name Group Pin Signal Name Group 169 USB 3/4_P USB 3/4 170 DACK2# ISA 171 GND PWR 172 SA5 ISA 173 USB 1/ 2_OC# USB 1/ 2 174 SD14 ISA 16 175 USB 3/4_OC# USB 3/4 176 MASTER# ISA 16 177 DDC_SCL CRT 178 TC ISA 179 DDC_SDA CRT 180 SA4 ISA 181 GND PWR 182 SD15 ISA 16 183 CRT_G CRT 184 — RSVD 185 CRT_GND CRT 186 BALE ISA 187 CRT_R CRT 188 SA3 ISA 189 CRT_GND CRT 190 VCC PWR 191 CRT_B CRT 192 SA2 ISA 193 GND PWR 194 OSC ISA 195 CRT_VS CRT 196 SA1 ISA 197 GND PWR 198 SA0 ISA 199 CRT_HS CRT 200 GND PWR

Table 2-28 STX P2/J2 Connector Pin out

2.5.3 FC2 – ZV from STX Module The ZV-Port, or Zoomed Video Port, allows direct transmission of video data from a STX module to STB Base board. This connector also includes EX_LCD signal and TV signal from STX module. FC2 connector is a 41 Pin 0.5m/m Pitch FPC/FFC-CONN ZIF 90D SMT type connector that provides interfaces for the following functions.

PinPinPinPin Signal PinPinPinPin Signal PinPinPinPin Signal PinPinPinPin Signal PinPinPinPin Signal

1111 GND 11111111 GND 21212121 GND 31313131 FPD28(TVD0) 41414141 NC

2222 GND 12121212 GND 22222222 GND 32323232 FPD29(TVD1)

3333 ZVD0 13131313 ZVD8 23232323 ZVREF 33333333 GND 4444 ZVD1 14141414 ZVD9 24242424 ZVS 34343434 FPD30(TVD7) 5555 ZVD2 15151515 ZVD10 25252525 ZVCLK 35353535 FPD31(TVVS) 6666 ZVD3 16161616 ZVD11 26262626 GND 36363636 FPD32(TVCLK) 7777 ZVD4 17171717 ZVD12 27272727 FPD24(TVD6) 37373737 FPD33(TVD2) 8888 ZVD5 18181818 ZVD13 28282828 FPD25(TVD4) 38383838 FPD34(TVHS) 9999 ZVD6 19191919 ZVD14 29292929 FPD26(TVD5) 39393939 FPD35 10101010 ZVD7 20202020 ZVD15 30303030 FPD27(TVD7) 40404040 NC

Table 2-29 FC2 Connector Pin out




2.5.4 FC1 – IDE2 from STX Module FC1 connector is a 41 Pin 0.5m/m Pitch FPC/FFC-CONN ZIF 90D SMT type connector that provides interfaces for the following functions.

Pin # Signal Name Pin # Signal Name 1 GND 22 SDD0 2 BRSTDRV- 23 SDD15 3 GND 24 GND 4 SDD7 25 GND 5 SDD8 26 SSDDREQ 6 SDD6 27 SSDIOW- 7 SDD9 28 SSDIOR- 8 GND 29 SSDIORDY 9 SDD5 30 SSDDACK- 10 SDD10 31 GND 11 SDD4 32 IRQ15 12 SDD11 33 SDA1 13 GND 34 SD66- 14 GND 35 GND 15 SDD3 36 SDA0 16 SDD12 37 SDA2 17 SDD2 38 SCS1- 18 SDD13 39 SCS3- 19 GND 40 N.C. 20 SDD1 41 GND 21 SDD14

Table 2-30 FC1 Connector Pin out

STXVEA STX Module Data bookVersion 1.0, March 2003

Page 56 of 96 AXIOMTEK reserves the right to make improvements

to this document and/or product at any time and without notice.

:

C h a p t e r 3 Electrical Characteristics

This chapter provides a detailed description of STX Interface signals. The signals are arranged in functional groups according to their associated interface. All signals are described from STX Module point of view – for example, input means direction from the STX Baseboard to the STX Module.

3.1 Flat Panel Interface Axiomtek STX Interface supports all modes of digital flat panel interface. It allows using the different types of graphics controllers on the STX Module. STX flat panel interface is compatible with the Silicon Image's SiI154 and SiI164 Panel Link transmitters that can be used to drive the flat panels with TMDS interface.

Flat panel interface mode in use is indicated by BIOS setting. The pixel data mapping is described in the following table.

Flat Panel Data Signal

24-bit Mode (Pixel Data)

12-bit Mode (Low/High Half of Pixel Data)

Flat Panel Data Signal

24-bit Mode (Pixel Data)

12-bit Mode (Low/High Half of Pixel Data)

FP_D23 R7 — FP_D11 G3 G3/R7 FP_D22 R6 — FP_D10 G2 G2/R6 FP_D21 R5 — FP_D9 G1 G1/R5 FP_D20 R4 — FP_D8 G0 G0/R4 FP_D19 R3 — FP_D7 B7 B7/R3 FP_D18 R2 — FP_D6 B6 B6/R2 FP_D17 R1 — FP_D5 B5 B5/R1 FP_D16 R0 — FP_D4 B4 B4/R0 FP_D15 G7 — FP_D3 B3 B3/G7 FP_D14 G6 — FP_D2 B2 B2/G6 FP_D13 G5 — FP_D1 B1 B1/G5 FP_D12 G4 — FP_D0 B0 B0/G4

Table 3-1 Flat Panel Pixel Data Mapping

R, G, B denotes red, green, and blue color pixel components. Bit significance within a color is defined by number (7 denotes MSB). When modes with color depth less than 8 bit are used, LSB pixel bits are driven low.




The FP_DSEL signal defines single or dual clock mode used in 12-bit mode. The FP_EDGE selects an active edge of the clock signal. See following tables for definition of the clock edge used for pixel data sampling in different modes.

DSTN TFT Pin 16-bit 24-bit 18-bit 24-bit LP LP LP HSYNC HSYNC

FLM FP FP VSYNC VSYNC SHFCLK XCK XCK CK CK

M DE DE ENAVDD ENAVDD ENAVDD ENAVDD ENAVDD ENABLK ENABLK ENABLK ENABLK ENABLK

P23 UR0 UR0 R5 R7 P22 UR1 UR1 R4 R6 P21 UR2 UR2 R3 R5 P20 UR3 R2 R4 P19 LR0 LR0 R1 R3 P18 LR1 LR1 R0 R2 P17 LR2 LR2 R1 P16 LR3 R0

P15 UG0 UG0 G5 G7 P14 UG1 UG1 G4 G6 P13 UG2 UG2 G3 G5 P12 UG3 G2 G4 P11 LG0 LG0 G1 G3 P10 LG1 LG1 G0 G2 P9 LG2 LG2 G1 P8 LG3 G0

P7 UB0 UB0 B5 B7 P6 UB1 UB1 B4 B6 P5 UB2 B3 B5 P4 UB3 B2 B4 P3 LB0 LB0 B1 B3 P2 LB1 LB1 B0 B2 P1 LB2 B1 P0 LB3 B0

Table 3-2 DSTN and TFT Flat Panel Pixel Data Mapping




Pin Name TFT2X9 TFT2X12 TFT2X18 LP LP LP HSYNC

FLM FP FP VSYNC SHFCLK XCK XCK CK

M DE ENAVDD ENAVDD ENAVDD ENAVDD ENABLK ENABLK ENABLK ENABLK

P35 B12 B13 B15 P34 B02 B03 B05 P33 B11 B12 B14 P32 B01 B02 B04

P31 B10 B11 B13 P30 B00 B01 B03 P29 B10 B12 P28 B00 B02 P27 B11 P26 B01 P25 B10 P24 B00 P23 G12 G13 G15 P22 G02 G03 G05 P21 G11 G12 G14 P20 G01 G02 G04 P19 G10 G11 G13 P18 G00 G01 G03 P17 G10 G12 P16 G00 G02

P15 G11 P14 G01 P13 G10 P12 G00 P11 R12 R13 R15 P10 R02 R03 R05 P9 R11 R12 R14 P8 R01 R02 R04

Continued . . . . .




Pin Name TFT2X9 TFT2X12 TFT2X18 P7 R10 R11 R13 P6 R00 R01 R03 P5 R10 R12 P4 R00 R02 P3 R11 P2 R01 P1 R10 P0 R00

Table 3-3 TFT Flat Panel Pixel Data Mapping

STN DSTN

Pin 8-bit 16-bit 24-bit 8-bit LP LP LP HSYNC HSYNC


M DE DE DE DE ENAVDD ENAVDD ENAVDD ENAVDD ENAVDD ENABLK ENABLK ENABLK ENABLK ENABLK

P0 R0 R0 R0 LR0 P1 G0 G0 G0 P2 B0 B0 B0 LG0 P3 R1 R1 R1 P4 G1 G1 G1 LB0 P5 B1 B1 B1 P6 R2 R2 R2 LR1 P7 G2 G2 G2 P8 B2 B2 P9 R3 R3 P10 G3 G3 P11 B3 B3 P12 R4 R4 P13 G4 G4 P14 B4 B4 P15 R5 R5 P!6 G5 P17 B5

Continued . . . . .




STN DSTN

Pin 8-bit 16-bit 24-bit 8-bit P18 R6 UR0 P19 G6 P20 B6 UG0 P21 R7 P22 G7 UB0 P23 B7 P24 UR1

DSTN TFT

Pin 16-bit 24-bit 9-bit 2X9-bit LP LP LP HSYNC HSYNC



P0 LB3 P1 LB2 P2 LB1 LB1 P3 LB0 LB0 P4 UB3 P5 UB2 P6 UB1 UB1 R0 R00 P7 UB0 UB0 R10 P8 LG3 R1 R01 P9 LG2 LG2 R11 P10 LG1 LG1 R2 R02 P11 LG0 LG0 R12 P12 UG3 P13 UG2 UG2 P14 UG1 UG1 P15 UG0 UG0 P16 LR3 P17 LR2 LR2 P18 LR1 LR1 G0 G00 P19 LR0 LR0 G10

Continued . . . . .




DSTN TFT

Pin 16-bit 24-bit 9-bit 2X9-bit P20 UR3 G1 G01 P21 UR2 UR2 G11 P22 UR1 UR1 G2 G02 P23 UR0 UR0 G12 P30 B0 B00 P31 B10 P32 B1 B01 P33 B11 P34 B2 B02 P35 B12

TFT TFT

Pin 12-bit 2X12-bit 15-bit 2X15-bit LP LP LP HSYNC HSYNC



P0 P1 P2 R0 R00 P3 R10 P4 R0 R00 R1 R01 P5 R10 R11 P6 R1 R01 R2 R02 P7 R11 R12 P8 R2 R02 R3 R03 P9 R12 R13 P10 R3 R03 R4 R04 P11 R13 R14 P12 P13 P14 G0 G00 P15 G10 P16 G0 G00 G1 G01

Continued . . . . .




TFT TFT

Pin 12-bit 2X12-bit 15-bit 2X15-bit P17 G10 G11 P18 G1 G01 G2 G02 P19 G11 G12 P20 G2 G02 G3 G03 P21 G12 G13 P22 G3 G03 G4 G04 P23 G13 G14 P24 P25 P26 B0 B00 P27 B10 P28 B0 B00 B1 B01 P29 B10 B11 P30 B1 B01 B2 B02 P31 B11 B12 P32 B2 B02 B3 B03 P33 B12 B13 P34 B3 B03 B4 B04 P35 B13 B14

TFT TFT

Pin 18-bit 24-bit 2X18-bit LP LP LP HSYNC

FLM FP FP VSYNC SHFCLK XCK XCK CK

M DE DE DE ENAVDD ENAVDD ENAVDD ENAVDD ENABLK ENABLK ENABLK ENABLK

P0 B0 R00 P1 B1 R10 P2 B0 B2 R01 P3 B1 B3 R11 P4 B2 B4 R02 P5 B3 B5 R12 P6 B4 B6 R03 P7 B5 B7 R13

Continued . . . . .




TFT TFT

Pin 18-bit 24-bit 2X18-bit P8 G0 R04 P9 G1 R14 P10 G0 G2 R05 P11 G1 G3 R15 P12 G2 G4 G00 P13 G3 G5 G10 P14 G4 G6 G01 P15 G5 G7 G11 P16 R0 G02 P17 R1 G12 P18 R0 R2 G03 P19 R1 R3 G13 P20 R2 R4 G04 P21 R3 R5 G14 P22 R4 R6 G05 P23 R5 R7 G15 P24 B00 P25 B10 P26 B01 P27 B11 P28 B02 P29 B12 P30 B03 P31 B13 P32 B04 P33 B14 P34 B05 P35 B15

Table 3-4 Flat Panel Interface Pins of Color DSTN and Color TFT LCD

FP_DSEL FP_EDGE 24-bit Pixel Data 0 0 FP_CLK_P falling edge 0 1 FP_CLK_P rising edge 1 0 — 1 1 —

Table 3-5 Sampling Edge in 24-bitMode (FP_BSEL=1)




FP_DSEL FP_EDGE Low Half of Pixel Data High Half of Pixel Data 0 0 FP_CLK_P falling edge FP_CLK_S falling edge0 1 FP_CLK_P rising edge FP_CLK_S rising edge 1 0 FP_CLK_P falling edge FP_CLK_P rising edge 1 1 FP_CLK_P rising edge FP_CLK_P falling edge

Table 3-6 Sampling Edge in 12-bitMode (FP_BSEL=0)

3.2 PCI Bus Interface STX interface supports up to three external PCI devices with bus master capability. Additionally the fourth PCI device without bus master support can be connected provided that clock signal is replicated.

3.2.1 Clock Distribution The STX Module provides clock signals for three external PCI devices or slots on the STX Baseboard. The maximum skew of 2 ns shall be maintained across the system operating at 33 MHz between any two PCI devices at the clock input of the integrated circuits.

There are two components that contribute to clock skew in a STX system:

� STX Module clock skew

� STX Baseboard clock skew

The STX Module clock distribution circuitry has to be designed to accommodate the STX Baseboard skew. The clock distribution circuitry provides a discrete clock signal to each of the STX connector pins defined as PCI clock (CLK[3..0]). The routing of these signals shall be matched in length. Any on-board STX device shall be provided a clock that is delayed to accommodate the maximum propagation delay of the Baseboard clocks and still meet the 2 ns overall skew requirement.

Clock Signal Length Each external PCI device on STX Baseboard shall be provided a discrete clock signal. The clock signals on the STX Baseboard have to be designed with a delay of 800 ps between STX connector clock pins and PCI device clock input pins. As the typical trace velocity is in the range of 60–75 ps/cm, the trace length of the clock signals should be 10–14 cm.

The fourth PCI device can be connected provided that clock signal is replicated. The zero-delay buffer based on PLL technology must be used in this case to maintain the overall maximum skew.

3.2.2 IDSEL Mapping To avoid possibility of contention between selecting PCI devices on the STX Baseboard and PCI devices on the STX Module, AD[23..20] lines are used to support IDSEL signals on the STX Baseboard devices as can be seen in Table 30 “PCI Interrupt Routing” on page 35. This mapping is compatible with PC-104+ specification.




Expansion connectors and devices connected directly to STX connectors are considered to be on bus 0.

3.2.3 Interrupt Routing To standardize the interrupt assignation in the system BIOS and OS, the interrupt binding scheme is defined in the following table. Used interrupt routing is compatible with PC-104+ specification.

STX Interrupt Signal IDSEL Mapping INTA# INTB# INTC# INTD#

AD23 INTB INTC INTD INTA AD22 INTC INTD INTA INTB AD21 INTD INTA INTB INTC AD20 INTA INTB INTC INTD

Table 3-7 PCI Interrupt Routing

For example: INTA# pin of device with IDSEL=AD21 has to be connected to INTB# signal on the STX Interface.

Note Relation between PCI device number and IDSEL mapping depends on the used chipset and may differ on various STX Modules.

3.2.4 Signaling Voltage Level The STX Module can use 5V or 3.3V PCI signaling level. To allow design of universal STX Baseboard with PCI devices supporting the both signaling levels, the V_IO pin is defined on the STX Interface. This pin is connected to VCC when 5V signaling level is used and to VCC3 in 3.3V environment. V_IO can be used for PCI I/O buffer power supply and maximal current drawn from this pin must not exceed 250mA. There is no mechanical keying system defined for STX Module to specify whether the STX Module uses 5V or 3.3V signaling level. Note STX Module requires both 5V and 3.3V power supply irrespective of used PCI signaling

level.

3.3 Electrical Power Requirements Max. Cur Pin

Name Pin

Count Range Tolerance CPU400 CPU533 CPU667 CPU800 VCC 17 4.75-5.25V 5% 0.9A 1.8A 1.9A 3.2A VCC3 16 3.135-3.465V 5% 2A 2A 2A 2A V_SB 2 4.75-6.25V 5% 0.8A 0.8A 0.8A 0.8A V_BAT 1 2.8-3.6V -10%;+20% 5uA 5Ua 5uA 5uA

Table 3-8 STX88600 Electrical Power Requirements




Max. Cur Pin Name

Pin Count Range Tolerance

CPU400 CPU650 CPU933 VCC 17 4.75-5.25V 5% 1.65A 2.5A 3A VCC3 16 3.135-3.465V 5% 2.A 2A 2A V_SB 2 4.75-6.25V 5% 0.8A 0.8A 0.8A V_BAT 1 2.8-3.6V -10%;+20% 5uA 5Ua 5uA

Table 3-9 STX88601 Electrical Power Requirements




C h a p t e r 4 Mechanical Specifications

The standard STX compliant hardware, defined by IBS Industrieelektronik Multimedia, must comply with the following mechanical specifications.

Figure 4-1 STX Module Dimensions

4.1 STX Dimensions The STX defines its dimensions on the following illustrations.

Figure 4-2 STX Module Dimensions




Figure 4-3 STX Module Layout

NOTE: Fastening mechanism for STX Module consists of four mounting holes in PCB and four inner threads M3×5 mm.

Figure 4-4 STX Height Dimensions




Figure 4-5 J1/J2 Connector Specifications

Figure 4-6 FC1, FC2 Location of STX Baseboard




NOTES: 17 mm <A (mounting hole to FC1 tolerance) < 35 mm, 8 mm < B (vertical shift tolerance between FC1 and FC2 based on mounting hole) < 9 mm, 9 mm < C (gap between FC1 and FC2), 8 mm < D (distance of FC2 connector from PCB edge), 8 mm < E (restricted zone area), F is restricted zone (none components area)

STX Module STX Module P1 and P2 Plugs Type

P1 and P2 Plugs Height

STX Module Height (Without Plugs)

Bare A=10 mm Type II. AMP 1-179030-0 6.6 mm Boxed A=15 mm

Table 4-1 STX Module Type I. Heights

4.2 FPC1 and FPC2 Connectors The FPC1 and FPC2 connectors use the FPC-41P-SMD with a pitch of 0.5mm.

AXIOMTEK Part No

Circuits / Positions Dimension A Dimension B Dimension C Cable Thickness Carrier Tape

Width 5435412210 41 26 20 24.5 0.5 21

Figure 4-7 FPC41 Top View

AXIOMTEK Part No Vendor Refere nce BL112-41RL Switchtech Enterprise Limited http://www.mbmags.com/switchtech

The FPC1 and FPC2 matching cable is a 41-pin cable with 0.5mm pitch and 60mm length. The table below lists the part number and vendor used for this purpose.

http://www.mbmags.com/switchtech




AXIOMTEK Part No Vendor Refere nce FC1 P/N:5940866002 FC2 P/N:5940866001

Switchtech Enterprise Limited http://www.mbmags.com/switchtech

FC1 P/N:HV8-41P-54mm-B-5/5-3/3FC2 P/N:HV8-41P-54mm-A-5/5-3/3

http://www.hungfu.com.tw/

4.3 STX Base Board The STX architecture requires the STX Baseboard to use a +5V Fan wafer 2-pin connector with a 2.54mm pitch.

AXIOMTEK Part No Vendor Refere nce 5409102118 Switchtech Enterprise Limited http://www.mbmags.com/switchtech

For FC1, a straight wafer connector with 2.54mm pitch is used.

AXIOMTEK Part No Vendor Refere nce P/N: 2.54mm HOUSING TERMINAL & WAFER (STRAIGHT)

Amtek http://www.amtek-co.com.tw/wafer_housing_terminal.htm


http://www.hungfu.com.tw/


http://www.amtek-co.com.tw/wafer_housing_terminal.htm




C h a p t e r 5 Award BIOS Defaults

The Award BIOS that comes with the STX bundles DMI, Plug-and-Play & Y2K Compliant in a 4Mbit Flash ROM, SmartView VGA BIOS function; and integrated Ethernet RPL, and the PXE Boot ROM features. For convenience, the following sections list all menus, options, and default settings.

5.1 Standard CMOS Features Menu Options Default Setting Menu Options Default Setting

Drive A 1.44M, 3.5 in. Display Type During Post VGA Default Drive B None Display Type After Post VGA Default LCD Type T9 800x600 TFT Halt on All, But keyboard Screen Expansion Enable Base Memory 640K TV Type NTSC Extended Memory 65535K

5.2 Advanced BIOS Features Menu Options Default Setting Menu Options Default Setting

Virus Warning Disabled CPU Internal Cache Enabled External Cache Enabled CPU L2 Cache ECC Checking Enabled Processor Number Feature Enabled Quick Power On Self Test Enabled First Boot Device Floppy Second Boot Device HDD-0 Third Boot Device LS120 Boot Other Device Enabled Onboard LAN boot Rom Disable Optimized default select BIOS O optimizedCardbus IRQ Mode select STB97200 Swap Floppy Drive Disabled Boot Up Floppy Seek Enabled Boot Up NumLock Status On Gate A20 Option Fast Typematic Rate Setting Disabled Typematic Rate (Chars/Sec) 6 Typematic Delay (Msec) 250 Security Option Setup PS/2 Mouse Control Enable OS Select For DRAM > 64MB Non-OS2 Video BIOS Shadow Enabled C8000-CBFFF Shadow Disabled CC000-CFFFF Shadow Disabled D0000-D3FFF Shadow Disabled D4000-D7FFF Shadow Disabled D8000-DBFFF Shadow Disabled DC000-DFFFF Shadow Disabled Small Logo(EPA) Show Disabled




5.3 Advanced Chipset Features Menu Options Default Setting Menu Options Default Setting

DRAM Timing By SPD Enabled DRAM Clock Host CLK SDRAM Cycle Length 3 Bank Interleave Disabled Memory Hole Disabled P2C/C2P Concurrency Enabled System BIOS Cacheable Disabled Video RAM Cacheable Disabled Frame Buffer Size 16M AGP Aperture Size 64M AGP-4X Mode Enabled OnChip USB Enabled USB Keyboard Support Disabled OnChip Sound Auto CPU to PCI Write Buffer Enabled PCI Dynamic Bursting Enabled PCI Master 0 WS Write Enabled PCI Delay Transaction Disabled PCI#2 Access #1 Retry Enabled AGP Master 1 WS Write Disabled AGP Master 1 WS Read Disabled

5.4 Integrated Peripherals Menu Options Default Setting Menu Options Default Setting

OnChip IDE Channel0 Enabled OnChip IDE Channel1 Enabled IDE Prefect Mode Enabled Primary Master PIO Auto Primary Slave PIO Auto Secondary Master PIO Auto Secondary Slave PIO Auto Primary Master UDMA Auto Primary Slave UDMA Auto Secondary Master UDMA Auto Secondary Slave UDMA Auto Init Display First PCI Slot IDE HDD Block Mode Enabled Onboard FDD Controller Enabled Onboard SPI 1 3F8/IRQ4 Onboard SPI 2 2F8/IRQ3 UART 2 Mode Standard IR Function Duplex Half TX, RX inverting enable No, Yes Onboard PPI 378/IRQ7 Onboard Parallel Mode Normal ECP Mode Use DMA 3 PPI EPP Type EPP1.9 Onboard SPI 3 3E8H SPI 3 Use IRQ IRQ10 Onboard SPI 4 2E8H SPI 4 Use IRQ IRQ11 Onboard Legacy Audio Enabled Sound Blaster Disabled SB I/O Base Address 220H SB IRQ Select IRQ 5 SB DMA Select DMA 1 MPU-401 Disabled MPU-401 I/O Address 330-333H




5.5 Power Management Setup Menu Options Default Setting Menu Options Default Setting

ACPI Function Disabled Power Management Press Enter PM Control by APM Yes Video Off Option Suspend -> Off Video Off Method V/H SYNC+Blank MODEM Use IRQ 3 Soft-Off by PWRBTN Instant-Off Wake Up Events Press Enter

5.5.1 Wake up Events Menu Options Default Setting Menu Options Default Setting

VGA OFF RTC Alarm Resume Disabled LPT&COM LPT/COM X Date (of Month) 0 HDD&FDD ON X Resume Time (hh:mm:ss) 0:0:0 PCI Master OFF Primary INTR ON PowerOn by PCI Card Disabled IRQ Activity Monitoring Press Enter Modem ring Resume Enabled

5.6 PnP/PCI Configurations Menu Options Default Setting Menu Options Default Setting

PNP OS Installed No Reset Configuration Data Disabled Resources Controlled By Manual IRQ Resources Press Enter DMA Resources Press Enter PCI/VGA Palette Snoop Disabled Assign IRQ For VGA Enabled Assign IRQ For USB Enabled

5.6.1 IRQ Resources Menu Options Default Setting Menu Options Default Setting

IRQ -3 assigned to PCI/ISA PnP IRQ -4 assigned to PCI/ISA PnP IRQ -5 assigned to PCI/ISA PnP IRQ -7 assigned to PCI/ISA PnP IRQ -9 assigned to Legacy ISA IRQ -10 assigned to PCI/ISA PnP IRQ -11 assigned to PCI/ISA PnP IRQ -12 assigned to PCI/ISA PnP IRQ -14 assigned to PCI/ISA PnP IRQ -15 assigned to PCI/ISA PnP




5.6.2 DMA Resources Menu Options Default Setting Menu Options Default Setting

DMA - 0 assigned to PCI/ISA PnP DMA - 1 assigned to PCI/ISA PnP

DMA -3 assigned to PCI/ISA PnP DMA -5 assigned to PCI/ISA PnP DMA - 6 assigned to PCI/ISA PnP DMA - 7 assigned to PCI/ISA PnP

5.7 Frequency/Voltage Control

Menu Options Default Setting Auto Detect DIMM/PCI Clk Enabled Spread Spectrum Disabled CPU Host/PCI Clock Default




A p p e n d i x A Troubleshooting

This appendix lists the most common encountered questions/problems when using the STX module. If you come across a dilemma not listed in this appendix, please send the nature and symptoms of your problem and e-mail them to [email protected].

Question: What’s the hardware revision history of STX?

A n s w e r :A n s w e r :A n s w e r :A n s w e r :

PCB Version Description Note A0~A1 NOT FOR SALE Engr. Sample A2 Changed layer for Impedance control

Added CPU clock ratio BR0~4 Added ATX power support Added TXCT to +3VSB for Standard USE Added Power LED (Green color)

Trial Run 1

A3 NOT FOR SALE Trial Run 2 A4 Fixed A3 power net to GND

Solved “+2.5V PWM Linear to switching” heat issue Fixed unusable ISA SCSI card (Master device)

Trial Run 3

A5 Fixed the reversed LAN Link & active LEDs Added LAN TX Impedance to match Standard design

Pilot Run

B0 NOT FOR SALE Engr. Sample B1 Fixed B0 Crystal Y3 mechanically error

Y1~Y3 Crystal DIP to SMD for common component with STX Added USB3&4 (Use JTAG) � Axiomtek STX Added: P2-38 to PCS0- � STX Standard P1-17 to Wake on LAN � STX Standard P1-110 to PME- � STX Standard To enhance +Vcore for C3-1GHZ CPU use, added:

PCI4 signal � Axiomtek STX FC1, FC2 rename FC1, FC2 � Axiomtek STX

Release

mailto:[email protected]




Question: How do I select the correct BIOS when I pair off STX and STB86600 in my system?

A n s w e r : A n s w e r : A n s w e r : A n s w e r :

STX \ STB86600 PCB ver. A0~A2 31/30/29/28 (Axiomtek)

PCB ver. A3~A4 28/20/21/22/23 (STX)

A0 (sample version) A10.1F.0 (2M) A12.1f.0 (2M) A11.1F.0 (2M)

A1 (sample version) A10.1F.0 (2M) A12.1f.0 (2M) A11.1F.0 (2M)

A2 (T/R 1) A10.1F.0 (2M) A12.1f.0 (2M) A11.1F.0 (2M)

A4 (T/R 2) A10.1F.0 (2M) A12.1f.0 (2M) B10.1F.0 (4M)

A11.1F.0 (2M) B11.1F.0 (4M) B12.1F.0 (4M) B13.1F.0 (4M) B14.1F.0 (4M) B15.1F.0 (4M)* B16.1F.0 (4M) B17.2F.0 (4M)

A5 (P/R) A10.1F.0 (2M) A12.1f.0 (2M) B10.1F.0 (4M)


B1 (Release) A10.1F.0 (2M) A12.1f.0 (2M) B10.1F.0 (4M)





Question: Where can I find the hardware modification list of STB86600?


PCB Version History Note A0~A1 NOT FOR SALE Engr. Sample A2 Added ATX power support

Changed 5V to 3.3V PWM circuit for IC phase out issue Shifted CF1 connector position for mechanical reasons Changed 5V Fan connector only from 3pin to 2pin

Trial Run 1

A3 Fixed extend Buzzer error Fixed extend HDD LED error Added CN3 ATX connector characters Changed PCI routing from AD20~AD23 � STX Standard

Pilot Run

A4 Fixed the reversed LAN Link & active LEDs Release

Question: Can I use STX ver. A4 to work with STB86600 ver. A5?

A n s w e r :A n s w e r :A n s w e r :A n s w e r : The STX (A4) and STB86600 (A5) cannot work within a system. There is an impedance compatibility issue between STX and STB86600. We recommend you to first check the list below before proceeding.

STB86600 \ STX A2~A4 (without Impedance)

A5~B1 (Impedance onboard)

A2~A3 (Impedance onboard) OK NG

(Note 1)

A4 (without Impedance)

NG (Note 2) OK

If you install STX and STB86600 in the same system, only one between them can add Impedance onboard. Otherwise, the system of Network function will not work properly.

Note 1: If the PCB version of STX is within A5~B1, and the STB86600 falls within version A2~A3, the system of Network function will not work properly. The solution to this problem is to take out R218, R219, C246 and C247 from STX. The following figuresl show the locations of these components onboard the STX86600 module.




Note 2: If the PCB version of STX is within versions A2~A4, and the STB86600 is A4., the

system of Network function still will not work properly. The STX (A2~A4) does not have any available address to add these Impedance components. Therefore the sole solution for this problem is to directly add Impedance components onto the Baseboard.




Question: How do all STX BIOS versions differ from each other?


No. Version Perversion Release Date

SBC Model No.

Notice

1 A10.1F.0 NONE 07/29/02 1. For Trial Run BIOS 2. Modified from 886006KA.BIN

2 A11.1F.0 NONE 08/07/02 1. Changed VGA BIOS 2. Supported >137G HDD 3. USB Device Bootable 4. Modified from 8860086A.BIN

3 A12.1F.0 NONE 09/27/02 1. Modified from 886009BA.BIN 2. Com3/4 default IRQ10/11 3. ACPI default Disable 4. Always set IRQ9 to Legacy to solve inability of

installing WinXP when ACPI is disabled 5. Removed S3 support

4 B10.1F.0 NONE 09/27/02 1. Modified from 886009QA.BIN 2. Used 4Mbit FlashROM 3. Added PXE/RPL BootROM 4. Added “Optimized Setup Select” BIOS item to

select “BIOS Optimized” or “Previous Setup” 5 B11.1F.0 NONE 10/31/02 1. Modified from 88600ASA.BIN

2. Used 4Mbit FlashROM 3. PCI Slot 20/21/22/23 (STX spec.) 4. Added Onboard LAN ROM Selected

6 B12.1F.0 NONE 12/02/02 STX 1. Modified from 88600BPA.BIN 2. Changed VGA BIOS to fix JP-DOS installation

problem 7 B13.1F.0 NONE 12/19/02 STX 1. Modified from 88600CHA.BIN

2. Changed Card Bus using Serial IRQ mode for Delta Baseboard

8 B14.1F.0 NONE 01/15/03 STX 1. Modified from 8860016A.BIN 2. Card Bus used Serial IRQ mode 3. Fixed Smart View CRT+TV problem 4. Released for Pilot Run

9 B15.1F.0 B14.1F.0 01/29/03 STX 1. Changed VGA BIOS for Samsung LTN104S2 Panel (Type 1) support

2. This BIOS could not use others panel 10 B16.1F.0 NONE 03/07/03 STX 1. Modified from 8860037A.BIN

2. Changed Serial IRQ to PCKN4000, Parallel IRQs to STB97200

3. Removed Temperature 4. Added VTT voltage sensor

11 B17.2F.0 NONE 03/20/03 STX 1. Modified from 886003KA.BIN 2. Updated VGA ROM from 7005sw3 to 7005sw5 3. Removed VTT voltage sensor 4. Changed Card Bus Mfunc6 IRQ from 15 to 7




Question: When I enter the OS, I see COM Ports 3 & 4 display a ‘? ‘ message even if I don’t have COM Ports 3&4 on my Baseboard. What should I do?

A n s w e r :A n s w e r :A n s w e r :A n s w e r : There are two solutions to this problem:

1. Disable COM3 and COM4 from the BIOS setting.

2. Request for the new BIOS from AXIOMTEK’s FAE and use software tool to update the BIOS, that does not have COM3 & 4 built-in.

Question: After connecting the IDE2 cable onto the Axiomtek STX Baseboard, it didn’t work. Is there anything I need to check?

A n s w e r :A n s w e r :A n s w e r :A n s w e r : If you need to use IDE2, make sure the 41-pin flat cable from the STX connector ‘FC1’ to the STX Baseboard connector ‘FC1’ is firmly connected. Otherwise, there will be no IDE2 signal produced from the STX to the Baseboard.

Question: After connecting the TV monitor from the Baseboard’s ‘Composite Video Output’ or ‘S-Video Output’, it didn’t work. Did I forget to check on something?

A n s w e r :A n s w e r :A n s w e r :A n s w e r : A: If you need to use a TV display, please take note of the following hardware/software reminders:

Hardware: The 41-pin flat cable must be connected from the STX connector ‘FC2’ to the STX Baseboard connector ‘FC2’. Failing to do so will not yield any TV signal from the STX to the Baseboard.

Software: Configure the BIOS display setting choice into ‘TV’ or ‘CRT + TV’.

Question: When I changed my LCD from 18bit TFT to 36bit TFT using Axiomtek’s 44-pin and 20-pin interface, and the BIOS smart view into TYPE2 1024x768 36bit LCD, I still couldn’t see anything on the display. What should I do?

A n s w e r :A n s w e r :A n s w e r :A n s w e r : If you shift and use a 36bit TFT, make sure the 41-pin flat cable is firmly connected from the STX connector ‘FC2’ to the STX Baseboard connector ‘FC2’. Extended LCD signal from the STX to the Baseboard will not be available if the above procedure is not done.




Question: I bought a USB bootable device but it doesn’t work with your board. The device operates normally on other PCs. Is there anything I need to check?

A n s w e r :A n s w e r :A n s w e r :A n s w e r : Please configure the USB Port3 & Port4 BIOS settings into ‘ENABLE’.

Question: I use your STB97200 Baseboard, which supports Card bus for PCMCIA Flash ATA cards. Unfortunately, I could not make it work. What should I do?

A n s w e r :A n s w e r :A n s w e r :A n s w e r : As mentioned on the STB97200 manual (pages 38~39), here again are the installation notes concerning this issue.

Installing the card drive 1. Turn off the main power of your computer.

2. Remove the computer’s case. Some computer cases can be opened by removing the screws on the rear of the computer and then lifting its cover away from your computer. ATX cases are opened by removing the computer’s front panel and pulling it off from the bottom. Remove the screws attaching the side panel to the computer and then slide the two panels that cover the sides of the computer outwards. Refer to your computer’s documentation for the proper procedure when removing your computer’s case cover.

3. Insert the PCI-bus expansion card that contains the PCMCIA drive into your computer’s PCI-bus expansion slot. Using a screw, tighten it into the back plate of the PCI-bus PCMCIA drive to secure it to the case of your computer.

4. Return the case of your computer. Hardware installation is now complete. Turn on your computer and proceed with the software installation section compatible to the operating system your computer uses.

5. STB97200 uses PCI+ ISA Legacy Parallel Interrupt mode; each slot’s installed 16bits or 32bits cards would need an available IRQ (3, 4, 5, 7, 10, 11) to use (we suggest the use of IRQ4 [COM1] or IRQ11 [COM4]).

� For a 32bit card (ex. LAN card) use, set BIOS setting from disable COM1 (IRQ4) into OS make sure LAN card is using IRQ4.

� For 16bit card (ex. LAN card) use, set the BIOS settings from “disable COM1 (IRQ4)” and “IRQ Resource set IRQ4 to Legacy ISA” into OS make sure LAN card is using IRQ4.

� When using two PCMCIA slots (ex. LAN card), set the BIOS setting from disable COM1 (IRQ4), COM4 (IRQ11) into OS make sure LAN card is using IRQ4 and IRQ11.

6. Make sure the Advanced BIOS Features’ setting of Card bus IRQ Mode select is set as [STB97200]




Question: I will design a new Baseboard for my system, is it possible to remove the battery feature on my Baseboard design? What important information should I need to know beforehand?

A n s w e r :A n s w e r :A n s w e r :A n s w e r : We included a function on the BIOS setting called Optimized Default Select. You can make your selection from any of the following:

� Optimized Default Select This item allows you to load the BIOS default setup or your previous setup.

� [BIOS Optimized] When you select on the BIOS Optimized item then save & exit the BIOS setup program, the system will automatically load the BIOS defaults next time you hit the [DEL] key to enter the BIOS Main Menu Load Optimized Defaults.

� [Previous Setup] When you select on the Previous Setup item then save & exit the BIOS setup program, the BIOS will backup your changes into the flash bios. Save & exit the BIOS setup afterwards to save your settings. The contents in the flash bios will not be cleared, only until you change the choice into BIOS Optimized and after saving & exiting will it be erased.




A p p e n d i x B Technical References

This STX Hardware Specification makes reference to, and is based on, the current versions of the following specifications:

� STX Specifications, References and Overview at http://www.stx.info

� AXIOMTEK Co/. Ltd. website at http://www.axiomtek.com.tw

� PC/104 Specification, Version 2.3, PC/104 Consortium, visit http://www.PC104.org

� PC/104-Plus Specification, Version 1.1, PC/104 Consortium, visit http://www.PC104.org

� Intel Corporation at http://www.intel.com

� PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group

� ISA Bus Specification, IEEE P996

� AT Attachment - 5 with Packet Interface (ATA/ATAPI-5), ANSI NCITS 340–2000

� Standard Test Access Port and Boundary Scan Architecture, IEEE 1149.1

� Display Data Channel Standard, Version 3, VESA

� Audio Codec ‘97 Specification, Revision 2.1, Intel Corporation

� Universal Serial Bus Specification, Revision 1.1, Compaq, Intel, Microsoft, NEC

� Standard Signaling Method for a Bidirectional Parallel Peripheral Interface for Personal Computers, IEEE 1284–1994

� VIA Technologies, Inc. at http://www.via.com.tw

� Realtek Semiconductor Corp. at http://www.realtek.com.tw

� Switchtech Enterprise Limited at http://www.mbmags.com/switchtech

� Amtek Technology Co., Ltd. at http://www.amtek-co.com.tw/wafer_housing_terminal.htm

http://www.stx.info/

http://www.pc104.org/

http://www.intel.com/

http://www.via.com.tw/

http://www.realtek.com.tw/


http://www.amtek-co.com.tw/wafer_housing_terminal.htm




A p p e n d i x C Abbreviations

Abbreviation Description AC’97 Audio Codec '97 ATA AT Attachment CPU Central Processor Unit CRT Cathode Ray Tube DDC Display Data Channel E-IDE Enhanced Integrated Drive Electronics ETH Ethernet Interface FDD Floppy Disk Drive FEAT Feature Interface FPI Flat Panel Interface HDD Hard Disk Drive IrDA Infrared Data Association ISA Industry Standard Architecture JTAG Joint Test Action Group LSB Least Significant Bit LVDS Low Voltage Differential Signaling MSB Most Significant Bit PCB Printed Circuit Board PCI Peripheral Component Interconnect PPI Parallel Port Interface RSVD Reserved SMI System Management Interrupt SMM System Management Mode SPI Serial Port Interface STX Smarter Technology eXtended TAP Test Access Port TMDS Transition Minimized Differential Signaling USB Universal Serial Bus VESA Video Electronics Standards Association

Table B-1 Abbreviations Used

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