Substrate maturity and readiness in large volume to support mass adoption of ULP FDSOI platforms

Christophe MalevilleChristophe Maleville

January 21st, 2016SOI Consortium Conference – Tokyo 2016

Substrate readiness – 3 lenses view

C1 - Restricted 2January 21st, 2016SOI Consortium Conference – Tokyo 2016

SOI maturity curve

2005PC

2015Mobile

• NXP/Philips reliability thruthick isolation

• IBM and AMD leveragedPerformanceBoost of SOI

1992Satellite

Boost of SOI

• RFSOI bringsPerformance/costbreakthru

• FDSOI enableslow power devices

• ~2 millions wafer/year HVM

3January 21st, 2016SOI Consortium Conference – Tokyo 2016

4January 21st, 2016SOI Consortium Conference – Tokyo 2016

Planar FDSOI: Undoped Channel

Thin Silicon Channel

0.6

Thre

shold

Voltage (

mV)

V

(V)

LG=25nm - multiple sources contributing to VT variation

• FDSOI Substrate: Thin Si & Thin buried oxide

• Ultra thin BOX option �Back bias control

• Silicon thickness variations contribution to VT variations - VT sensitivity ~ 25mV/nm

• “All transistors should have Si thickness within ±5Å”

5January 21st, 2016SOI Consortium Conference – Tokyo 2016

6.5 7.0 7.5 8.0 8.50.3

0.4

0.5

VTsat

Thre

shold

Voltage (

mV)

Silicon Thickness (nm)

VTlin(V

)

Challenges and Opportunities of Extremely Thin SOI (ETSOI) CMOS Technology, A. Khakifirooz, VLSI-TSA 2010

Source: J. Hartmann, GSA Apr. 2012

FD-SOI: long term collaboration

ResearchInstitute

Advanced R&D

IndustrialisationDonor substrate

2005 20082005 2010

• Key achievements

Smart Cut & device experts

2005

FDSOI ∆Vt Yield BBias• Key achievements FDSOI ∆Vt Yield BBias

● ●

● ●

• Advanced crystal for 6nm active layer

• Wafering quality for thin Box bonding

● ● ●• ±5 Å Thickness uniformity

• All spatial frequency thickness control ● ●

• HVM ready ● ● ● ●

6January 21st, 2016SOI Consortium Conference – Tokyo 2016

Smart-Cut 1.0 – On-wafer uniformity

• Oxide uniformity • Post-split Silicon uniformity

Box WiW thickness post oxidation (Å) Post split WiW Si uniformity (Å)

0 5 10 15 20

7January 21st, 2016SOI Consortium Conference – Tokyo 2016

0 5 10 15 20

FD-SOI Uniformity – Bandwith for improvements

• Current ellipsometry accurately describes FD-SOI wafer

95% of wafer surface compliant @ +/-4A

90% of wafer surface compliant @ +/-3A

8January 21st, 2016SOI Consortium Conference – Tokyo 2016

SmartCut 2.0 for FDSOI

Implant

Cleaning

Start Material

OxTop

Adapted to Oxide Film Thickness

Splitting

Final sorting

Finishing

Bonding

Adapted to SOI Film Thickness

9January 21st, 2016SOI Consortium Conference – Tokyo 2016

Smart-Cut 2.0

• Ultrathin Box Capability • Uniformity vs roughness

rela

ted

defe

cts

FDSOIPDSOI

Bon

ding

rela

ted

10January 21st, 2016SOI Consortium Conference – Tokyo 2016

Thermal smoothing principle

• Silicon surface smoothing at high temperature (RTA, BA)• Material transport mechanism

�Bulk diffusion

�Evaporation / Condensation

�Surface diffusion�Surface diffusion

Silicon

Gas

Bulk diffusion

Evaporation / condensation

Surface diffusion

Reaction withcontaminant

F.De Crecy – CEA/LETI

Simulation of silicon smoothing under high temp anneal

11January 21st, 2016SOI Consortium Conference – Tokyo 2016

Layer Total Thickness Variation (Å)

“Conventional” control plan – Thickness + Roughness

BoxHandle

SOI

µm-1

10-6 10-2 1WtW

Ellipso

WiW

EllipsoDRM

0AFM

Performance +/-5 Å 6-10 Å P-V 0.8Å RMS

Evidence

12January 21st, 2016SOI Consortium Conference – Tokyo 2016

• Reflectivity of a FD-SOI stack (SOI + BOX) is function of wavelengths

• By filtering specific wavelength, reflectivity becomes only sensitive to SOI layer thickness variations

Differential Reflective Microscopy (DRM) for complete SOI thickness monitoring

Microscope calibration

100

105

110

115

120

125

130

135

6000 7000 8000 9000 10000 11000 12000

Grey scale

Elli

pso

thk,

A

ElipsoTheory, 540nm

Grey scale map

Signal treatmentCalibration wafers

Grey scale calibration curve Thickness profile

HSEB Baldur tool

Spatial wavelength range: 0.5µm – 80µm

13January 21st, 2016SOI Consortium Conference – Tokyo 2016

Layer Total Thickness Variation (Å)

All included SOI thickness control – (all wafers, all points, all frequencies)

BoxHandle

SOI

µm-1

10-6 10-2 1WtW

Ellipso

WiW

EllipsoDRM

0AFM

Performance +/-5 Å 6-10 Å P-V 0.8Å RMS

Evidence

14January 21st, 2016SOI Consortium Conference – Tokyo 2016

FD28nm: 30 000 Wafers: ± 1 Atomic Layer !

12nm

Handle

SOI (12nm)

Box (25nm)

Wafer

FDSOIPDSOI

∆SiStack

Micro

Local

15January 21st, 2016SOI Consortium Conference – Tokyo 2016

1 sigma (Å)

Improved thickness control for 22nm node

20 nm

Stack

• Polished Bulk• 20FD• 28FD

∆SiWafer

MicroLocal

16January 21st, 2016SOI Consortium Conference – Tokyo 2016

1 sigma (Å)

17January 21st, 2016SOI Consortium Conference – Tokyo 2016

Soitec – SOI adoption via Partnerships and CollaborationsFrom technology development to manufacturing

2005 2009 2011 2012 2015

RF-SOI 300mm ramp

Soitec RFeSisubstrate ramp

RF-SOI switch mainstream

1st RF-SOI switch

TR-SOI UCL & Soitec IP

RF-

SOI

>50%

FD-S

OI

Advanced R&D

IndustrialPartner

Materials Research28FD

Foundry offer

2005 2008 2010 2014 2015

…

22FDFoundry offer

18January 21st, 2016SOI Consortium Conference – Tokyo 2016

Antenna Switch Module

(SP9T ) Cost

RF-SOI value propositionEnabling best performance, integration and cost-efficiency

Integration

¢

Cost efficientPerformance

4G/LTE-A & beyond

performance enabler

High integration of RF Front-End module

Cost effectivetechnology

0

5

10

15

20

25

30

GaAS BSOS RFSOI

(SP9T ) Cost¢

Cheaper process cost

SOI Bulk GaAs

Switch

PA output stage

PA first stages

Integration on-goingin all 4G smartphones

x2die size reduction

19January 21st, 2016SOI Consortium Conference – Tokyo 2016

More expensive Substrates for cheaper dies

COST

1. FDSOI allows up to 6 mask levelsreduction

2. From 28nm, FDSOI processed wafer isless expensive than equivalent HKMG on bulk silicon

Processed wafer cost, FDSOI vs bulk

Source: GF, Semicon West 2013COST

IBS, 2014

20January 21st, 2016SOI Consortium Conference – Tokyo 2016

FD-SOI value propositionEnabling best performance, power and cost-efficiency

Energy EfficientEnergy EfficientUnique PerformanceUnique Performance Cost effectiveCost effective

+60% Faster than 28 nm Bulk SLP

5x more battery life than current generation

50% lower mask cost than FinFET

FD-SOI14 FinFET

Nor

rmal

ized

Per

form

ance

1.8

2

>20% Lower die cost

FD-SOI extends Moore’s Law beyond 28 nm enabling co st sensitive applications

Sources: GlobalFoundries FD-SOI technology webinar June 2015.EETimes article: Freescale, Cisco, Ciena Give Nod to FD-SOI | EE Times, March 1,2015

Used in Networking ASICs for datacenters

Cisco

40 bulk 28 bulk FinFET FD-SOI

19.9

4.5 6.411.6

Day

sof

bat

tery

life

$$$$

FD-SOI14 FinFET

20 nm Bulk

28 nm Bulk HPP

28 nm Bulk SLP

Norrmalized Cost/die (Mature Yields, Q1’19)

Nor

rmal

ized

Per

form

ance

0.9 1 1.1 1.2 1.30.8

1

1.2

1.4

1.6

Source: GlobalFoundries FD-SOI technology webinar, June 2015

Sources: GlobalFoundries FD-SOI technology webinar, June 2015

21January 21st, 2016SOI Consortium Conference – Tokyo 2016

22January 21st, 2016SOI Consortium Conference – Tokyo 2016

Multi-sourcing in place for HVM SOI platforms

200mm

300mm

23January 21st, 2016SOI Consortium Conference – Tokyo 2016

Take-aways

• FDSOI substrate is active part of the transistor

• SmartCut technology allows to meet FDSOI requirement s

• Metrology defined to predict/protect variability on device

• Die cost reduction can be supported thru right balance

between cost and simplification, delivering a pre-proc essed

wafer.

• Substrate availability /maturity is ready to suppor t FDSOI

mass adoption.

24January 21st, 2016SOI Consortium Conference – Tokyo 2016

SOI end customers in 2025

25January 21st, 2016SOI Consortium Conference – Tokyo 2016