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Subtractor /Multiplier

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Subtractor /Multiplier. Section 4.5 & 4.7. Outline. Delay Four Bit Subtractor Multiplier. Four Bit Adder. Erroneous Results When Delay is inserted in half_adder.v. Four-Bit Adder. C 4 is calculated last because it takes C 0 8 gates to reach C 4 . - PowerPoint PPT Presentation
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Subtractor/Multiplier Section 4.5 & 4.7
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Page 1: Subtractor /Multiplier

Subtractor/Multiplier

Section 4.5 & 4.7

Page 2: Subtractor /Multiplier

Outline

• Delay • Four Bit Subtractor• Multiplier

Page 3: Subtractor /Multiplier

Four Bit Adder

Page 4: Subtractor /Multiplier

Erroneous Results When Delay is inserted in half_adder.v

Page 5: Subtractor /Multiplier

Four-Bit Adder

C4 is calculated last because it takes C0 8 gates to reach C4.Each FA uses 2 XOR, 2 AND and 1 OR gate.A four-bit adder uses 8 XOR, 8 AND and 4 OR gate.

Page 6: Subtractor /Multiplier

Build a Full-Adder Circuit

w1

w2 w3

M1 M2

One gate-delay

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Wait for the four bit adder circuit to compute the results

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Verilog and JobsJob: Mixed signal design job in San Jose, CALevel: BS/MS in EE• Job Description:We are seeking a Mixed-Signal ASIC Verification Engineer. The successful candidate will be a key member of the team developing custom ICs for display modules based on the QMT SMI display technology. Hands on technical contributor in verification of Mixed-Signal ASICs and IP development projects. A candidate will help architect, specify, and lead the implementation of mixed Analog/Digital verification projects using high level verification languages. You will work very closely with analog circuit design team, digital design team, and mixed-signal ASIC project leaders to implement complete verification environments and methodologies. Design Mixed-Mode testbenches using SystemVerilog, create VerilogAMS models for analog circuit, create checkers, use ADE/Irun environment to simulate and execute tests in NCSIM/SimVision. Log results and verify with automatic checker. Responsibilities: Create re-usable AMS testbenches from grounds up using advanced verification methodologies (like UVM, OVM etc.) with emphasis towards behavioral modeling of analog blocks, closed-loop simulation with digital design and analog behavioral models and/or transistors by using Cadence Virtuoso schematic editor and ICFB tool environment, and automated & coverage-driven verification. Develop and maintain behavioral models (VerilogA/VerilogAMS) of analog and mixed-signal blocks including data converters(ADC/DAC), power converters (charge pump, buck converter, boost converter), switch mode power supplies, LDOs, analog switches/muxes, PLLs, level-shifters, amplifiers, thermal sensors.

Page 9: Subtractor /Multiplier

Verilog and FPGAParker Aerospace, an operating segment of Parker Hannifin Corporation, is one of the world’s leading producers of flight control, hydraulic, fuel, inerting, fluid conveyance, thermal management, and engine systems and components for the aerospace industry. We design and build equipment for virtually every aircraft and aero engine being produced in the world today.

ENGINEER III – AIRCRAFT ELECTRONICS SUMMARYResponsible for design, verification and certification of FPGA based aerospace firmware. Requirements creation and validation, conceptual design, detail design and testing. Create control circuits, design (writing of VHDL), develop timing constraints, simulate (functional and timing), place and route synthesized designs. Ensure all required data items and artifacts to support FAA SIO audits are correct and complete. Creation of verification requirements based test cases and oversight of verification simulations by supplier. Verify test cases, procedures, and test benches are created to satisfy existing design requirements. Perform independent audit of verification artifacts. Participate in peer design reviews and support continuous process improvements. Bachelor’s Degree in Electrical Engineering or related engineering discipline with preferably six plus years of experience in the design, development and certification of aerospace firmware. A Master’s Degree is a plus. Specific experience in DO-254 certification required. Specific experience in motor drive and flight control applications is a plus. Experience with ARINC-429, CAN, SPI or other serial interfaces. Experience in requirements capture and validation. Experience with VHDL design and verification. Experience with Xilinx and Altera development tools. Experience with ModelSim/QuestaSim to perform simulation and debug of VHDL design. Experience with in-circuit verification techniques. Possess excellent trouble shooting skills and knowledgeable in Chipscope / Signal Tap FGPA debugging tools. Experience creating requirements based test cases. Experience creating simulation / verification test bench using VHDL / Verilog language. Experience in supporting FAA SOI audits. Leadership experience a plus. Strong technical writing, verbal and written communication skills. Excellent work ethic. Able to work well in teams (local as well as remote) and is self-motivated.

Page 10: Subtractor /Multiplier

Verilog and Local Jobs

Auto req ID 23524BRJob Posting Title Intern, HardwareBusiness Unit Broadband CommunicationsJob Description Intern required to support ATE, Design and Design Verification.Job Requirements - Experience coding in Perl and a hardware description language (Verilog or VHDL).

- Experience with Linux or UNIX.- Candidate must be pursuing a undergraduate or post-graduate university degree in computer science or electrical engineering

Country United StatesState/Province CaliforniaCity/Town PetalumaShift 1st Shift - DayPercent of Travel Required

None

Function EngineeringDiscipline Intern

Page 11: Subtractor /Multiplier

Subtraction

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Unsigned Number

Decimal b1 b0

0 0 0

1 0 1

2 1 0

3 1 1

(2-bit example)

Page 13: Subtractor /Multiplier

Unsigned Addition

• 1+2=

Decimal b1 b0

0 0 0

1 0 1

2 1 0

3 1 1

Decimal b1 b0

1 0 1

+ 2 1 0

3 1 1

Page 14: Subtractor /Multiplier

Unsigned Addition

• 1+3=

Decimal b1 b0

0 0 0

1 0 1

2 1 0

3 1 1

Decimal b1

b0

1 1

1 0 1

+ 3 1 1

4 1 0 0

(Carry Out)

(Indicates Overflow)

Overflow can be an issue in unsigned addition.

Page 15: Subtractor /Multiplier

Unsigned Subtraction (1)

• 1-2=

Decimal b1 b0

0 0 0

1 0 1

2 1 0

3 1 1

Decimal b1

b0

1 0 1

+ -2 1 0

1 1

0 0

-1 0 1

(1’s complement)

(2’s complement)

Page 16: Subtractor /Multiplier

Unsigned Subtraction (2)

• 2-1=

Decimal b1 b0

0 0 0

1 0 1

2 1 0

3 1 1

Decimal b1 b0

1

2 1 0

+ -1 1 1

3 1 0 1

Discarded

Page 17: Subtractor /Multiplier

Summary for Unsigned Addition/Subtraction

• Overflow can be an issue in unsigned addition (An overflow is detected from the end carry out of the most significant position)

• Unsigned Subtraction (M-N)– If M≥N, and end carry will be produced.

The end carry is discarded.– If M<N, • Take the 2’s complement of the sum• Place a negative sign in front

Page 18: Subtractor /Multiplier

Four-Bit Adder-Subtractor

For detecting overflow in addition/subtraction of signed numbers

For detecting overflow in unsigned numbers

Page 19: Subtractor /Multiplier

The Mode Input (1)

B0

If M=0, = If M=1, =

Page 20: Subtractor /Multiplier

The Mode Input (2)

If M=0, If M=1,

Page 21: Subtractor /Multiplier

M=0 (Addition)

0

B3 B2 B1 B0

Page 22: Subtractor /Multiplier

M=1 (Subtraction)

1

2’s complement is generated of B is generated!

Page 23: Subtractor /Multiplier

Four-Bit Adder-Subtractor

FA0FA1FA2FA3

X0X1X2X3

X4

X_FA_0X_FA_1X_FA_2X_FA_3

Page 24: Subtractor /Multiplier

Verilog Model of a 4 bit adder/subtractor

Page 25: Subtractor /Multiplier

Sample output of adder/subtractor circuit

Ignore V if you are working with unsigned numbers.

Page 26: Subtractor /Multiplier

Binary Multiplication

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Two-Bit Binary Multiplier

(multiplicand)

(multiplier)

Page 28: Subtractor /Multiplier

𝐴 0𝐵00 0 0

0 1 0

1 0 0

1 1 1

Use an AND gate to multiply A0 and B0

Page 29: Subtractor /Multiplier

Hardware Correlation

Page 30: Subtractor /Multiplier

Hardware Correlation

G0G1

G2G3

W0W1W2

W3

HA1 HA0


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