Sudheer Mini

8/2/2019 Sudheer Mini

1/32

1

CHAPTER 1

INTRODUCTION TO EMBEDDED SYSTEMS

1.1 EMBEDDED SYSTEM

An embedded system is a special-purpose computer system designed to perform one

or a few dedicated functions, sometimes with real-time computing constraints. It is usually

embedded as part of a complete device including hardware and mechanical parts. In contrast,

a general-purpose computer, such as a personal computer, can do many different tasks

depending on programming. Embedded systems have become very important today as they

control many of the common devices we use.

Since the embedded system is dedicated to specific tasks, design engineers can

optimize it, reducing the size and cost of the product, or increasing the reliability and

performance. Some embedded systems are mass-produced, benefiting from economies of

scale.

Physically, embedded systems range from portable devices such as digital watches

and MP3 players, to large stationary installations like traffic lights, factory controllers, or the

systems controlling nuclear power plants. Complexity varies from low, with a single

microcontroller chip, to very high with multiple units, peripherals and networks mounted

inside a large chassis or enclosure.

In general, "embedded system" is not an exactly defined term, as many systems have

some element of programmability. For example, Handheld computers share some elements

with embedded systems such as the operating systems and microprocessors which power

thembut are not truly embedded systems, because they allow different applications to be

loaded and peripherals to be connected.

An embedded system is some combination of computer hardware and software, either

fixed in capability or programmable, that is specifically designed for a particular kind of

application device. Industrial machines, automobiles, medical equipment, cameras, household

appliances, airplanes, vending machines, and toys (as well as the more obvious cellular phone

and PDA) are among the myriad possible hosts of an embedded system. Embedded systems


2/32

2

that are programmable are provided with a programming interface, and embedded systems

programming is a specialized occupation.

Certain operating systems or language platforms are tailored for the embedded

market, such as Embedded Java and Windows XP Embedded. However, some low-end

consumer products use very inexpensive microprocessors and limited storage, with the

application and operating system both part of a single program. The program is written

permanently into the system's memory in this case, rather than being loaded into RAM

(random access memory), as programs on a personal computer are.

1.2 APPLICATIONS OF EMBEDDED SYSTEM

We are living in the Embedded World. You are surrounded with many embedded

products and your daily life largely depends on the proper functioning of these gadgets.

Television, Radio, CD player of your living room, Washing Machine or Microwave Oven in

your kitchen, Card readers, Access Controllers, Palm devices of your work space enable you

to do many of your tasks very effectively. Apart from all these, many controllers embedded

in your car take care of car operations between the bumpers and most of the times you tend to

ignore all these controllers.

In recent days, you are showered with variety of information about these embedded

controllers in many places. All kinds of magazines and journals regularly dish out details

about latest technologies, new devices; fast applications which make you believe that your

basic survival is controlled by these embedded products. Now you can agree to the fact that

these embedded products have successfully invaded into our world. You must be wondering

about these embedded controllers or systems. What is this Embedded System?

The computer you use to compose your mails, or create a document or analyze the

database is known as the standard desktop computer. These desktop computers are

manufactured to serve many purposes and applications.

You need to install the relevant software to get the required processing facility. So,

these desktop computers can do many things. In contrast, embedded controllers carryout a

specific work for which they are designed. Most of the time, engineers design these


3/32

3

embedded controllers with a specific goal in mind. So these controllers cannot be used in any

other place.

Military and aerospace software applications

From in-orbit embedded systems to jumbo jets to vital battlefield networks, designers of

mission-critical aerospace and defense systems requiring real-time performance, scalability,

and high-availability facilities consistently turn to the LynxOS RTOS and the LynxOS-178

RTOS for software certification to DO-178B.

Rich in system resources and networking services, LynxOS provides an off-the-shelf

software platform with hard real-time response backed by powerful distributed computing

(CORBA), high reliability, software certification, and long-term support options.

Communications applications

"Five-nine" availability, CompactPCI hot swap support, and hard real-time response

LynxOS delivers on these key requirements and more for today's carrier-class systems.

Scalable kernel configurations, distributed computing capabilities, integrated

communications stacks, and fault-management facilities make LynxOS the ideal choice for

companies looking for a single operating system for all embedded telecommunications

applicationsfrom complex central controllers to simple line/trunk cards.

Industrial automation and process control software

Designers of industrial and process control systems know from experience that

LynuxWorks operating systems provide the security and reliability that their industrial

applications require.

From ISO 9001 certification to fault-tolerance, POSIX conformance, secure partitioning

and high availability, we've got it all. Take advantage of our 20 years of experience.
http://www.lynuxworks.com/products/jumpstart/communications.php3http://www.lynuxworks.com/board-support/cpci.phphttp://www.lynuxworks.com/rtos/rtos.phphttp://www.lynuxworks.com/solutions/industrial/industrial.phphttp://www.lynuxworks.com/solutions/industrial/industrial.phphttp://www.lynuxworks.com/products/iso9001.php3http://www.lynuxworks.com/rtos/rtos-mmu-high-availability.phphttp://www.lynuxworks.com/products/posix/posix.php3http://www.lynuxworks.com/products/whitepapers/partition.phphttp://www.lynuxworks.com/rtos/high-availability.php3http://www.lynuxworks.com/rtos/high-availability.php3http://www.lynuxworks.com/products/whitepapers/partition.phphttp://www.lynuxworks.com/products/posix/posix.php3http://www.lynuxworks.com/rtos/rtos-mmu-high-availability.phphttp://www.lynuxworks.com/products/iso9001.php3http://www.lynuxworks.com/solutions/industrial/industrial.phphttp://www.lynuxworks.com/solutions/industrial/industrial.phphttp://www.lynuxworks.com/rtos/rtos.phphttp://www.lynuxworks.com/board-support/cpci.phphttp://www.lynuxworks.com/products/jumpstart/communications.php3


4/32

4

1.3 MICROPROCESSORVERSUS MICROCONTROLLER

What is the difference between a Microprocessor and Microcontroller? By

microprocessor is meant the general purpose Microprocessors such as Intel's X86 family

(8086, 80286, 80386, 80486, and the Pentium) or Motorola's 680X0 family (68000, 68010,

68020, 68030, 68040, etc.). These microprocessors contain no RAM, no ROM, and no I/O

ports on the chip itself. For this reason, they are commonly referred to as general-purpose

Microprocessors.

A system designer using a general-purpose microprocessor such as the Pentium or the

68040 must add RAM, ROM, I/O ports, and timers externally to make them functional.

Although the addition of external RAM, ROM, and I/O ports makes these systems bulkierand much more expensive, they have the advantage of versatility such that the designer can

decide on the amount of RAM, ROM and I/O ports needed to fit the task at hand. This is not

the case with Microcontrollers.

1.4 MICROCONTROLLERS FOR EMBEDDED SYSTEMS

In the Literature discussing microprocessors, we often see the term Embedded

System. Microprocessors and Microcontrollers are widely used in embedded system

products. An embedded system product uses a microprocessor (or Microcontroller) to do one

task only. A printer is an example of embedded system since the processor inside it performs

one task only; namely getting the data and printing it. Contrast this with a Pentium based PC.

A PC can be used for any number of applications such as word processor, print-server, bank

teller terminal, Video game, network server, or Internet terminal. Software for a variety of

applications can be loaded and run. Of course the reason a pc can perform myriad tasks is that

it has RAM memory and an operating system that loads the application software into RAMmemory and lets the CPU run it.

In an Embedded system, there is only one application software that is typically burned

into ROM. An x86 PC contains or is connected to various embedded products such as

keyboard, printer, modem, disk controller, sound card, CD-ROM drives, mouse, and so on.

Each one of these peripherals has a Microcontroller inside it that performs only one task. For

example, inside every mouse there is a Microcontroller to perform the task of finding the

mouse position and sending it to the PC.


5/32

5

CHAPTER 2

8051 BLOCK DIAGRAM, PIN DESCRIPTION

2.1 8051 ARCHITECTURE

The generic 8051 architecture supports a Harvard architecture, which contains

two separate buses for both program and data. So, it has two distinctive memory

spaces of 64K X 8 size for both programmed and data. It is based on an 8 bit central

processing unit with an 8 bit Accumulator and another 8 bit B register as main

processing blocks. Other portions of the architecture include few 8 bit and 16 bit

registers and 8 bit memory locations.

Each 8051 device has some amount of data RAM built in the device for

internal processing. This area is used for stack operations and temporary storage of

data.

This bus architecture is supported with on-chip peripheral functions like I/O

ports, timers/counters, versatile serial communication port. So it is clear that this

8051 architecture was designed to cater many real time embedded needs.

2.2 FEATURES OF 8051 ARCHITECTURE

Optimized 8 bit CPU for control applications and extensive Boolean processing

capabilities.

64K Program Memory address space. 64K Data Memory address space. 128 bytes of on chip Data Memory. 32 Bi-directional and individually addressable I/O lines. Two 16 bit timer/counters. On chip clock oscillator. 6-source / 5-vector interrupt structure with priority levels.

Now we may be wondering about the non-mentioning of memory space meant for

the program storage, the most important part of any embedded controller. Originally

this 8051 architecture was introduced with on-chip, one time programmable


6/32

6

version of Program Memory of size 4K X 8. Intel delivered all these

microcontrollers (8051) with users program fused inside the device. The memory

portion was mapped at the lower end of the Program Memory area. But, after getting

devices, customers couldnt change anything in their program code, which was

already made available inside during device fabrication.

2.3 BLOCK DIAGRAM OF 8051

Figure 2.1 - Block Diagram of the 8051 Core

So, very soon Intel introduced the 8051 devices with re-programmable type of

Program Memory using built-in EPROM of size 4K X 8. Like a regular EPROM, this

memory can be re-programmed many times. Later on Intel started manufacturing these

8031 devices without any on chip Program Memory.


7/32

7

2.4 MICROCONTROLLER LOGIC SYMBOL

Fig 2.2 microcontroller logic symbol

ALE/PROG: Address Latch Enable output pulse for latching the low byte of the address

during accesses to external memory. ALE is emitted at a constant rate of 1/6 of the oscillator

frequency, for external timing or clocking purposes, even when there are no accesses to

external memory. (However, one ALE pulse is skipped during each access to external Data

Memory.) This pin is also the program pulse input (PROG) during EPROM programming.

PSEN: Program Store Enable is the read strobe to external Program Memory. When the

device is executing out of external Program Memory, PSEN is activated twice each machine

cycle (except that two PSEN activations are skipped during accesses to external Data

Memory). PSEN is not activated when the device is executing out of internal Program

Memory.

EA/VPP: When EA is held high the CPU executes out of internal Program Memory (unless

the Program Counter exceeds 0FFFH in the 80C51). Holding EA low forces the CPU to

execute out of external memory regardless of the Program Counter value. In the 80C31, EA

must be externally wired low. In the EPROM devices, this pin also receives the programming

supply voltage (VPP) during EPROM programming.

XTAL1: Input to the inverting oscillator amplifier.


8/32

8

XTAL2: Output from the inverting oscillator amplifier.

The 8051s I/O port structure is extremely versatile and flexible. The device has

32 I/O pins configured as four eight bit parallel ports (P0, P1, P2 and P3). Each pin

can be used as an input or as an output under the software control. These I/O pins

can be accessed directly by memory instructions during program execution to get

required flexibility.

These port lines can be operated in different modes and all the pins can be made

to do many different tasks apart from their regular I/O function executions.

Instructions, which access external memory, use port P0 as a multiplexed

address/data bus. At the beginning of an external memory cycle, low order 8 bits of

the address bus are output on P0. The same pins transfer data byte at the later stage

of the instruction execution.

2.5 MEMORY ORGANISATION

The alternate functions can only be activated if the corresponding bit latch in the port

SFR contains a 1. Otherwise the port pin remains at 0.All 80C51 devices have separate

address spaces for program and data memory, as shown in Figures 1 and 2. The logicalseparation of program and data memory allows the data memory to be accessed by 8-bit

addresses, which can be quickly stored and manipulated by an 8-bit CPU. Nevertheless, 16-

bit data memory addresses can also be generated through the DPTR register.

Program memory (ROM, EPROM) can only be read, not written to. There can be up

to 64k bytes of program memory. In the 80C51, the lowest 4k bytes of program are on-chip.

In the ROM less versions, all program memory is external. The read strobe for external

program memory is the PSEN (program store enable). Data Memory (RAM) occupies a

separate address space from Program Memory. In the 80C51, the lowest 128 bytes of data

memory are on-chip. Up to 64k bytes of external RAM can be addressed in the external Data

Memory space. In the ROM less version, the lowest 128 bytes are on-chip. The CPU

generates read and write signals, RD and WR, as needed during external Data Memory

accesses.


9/32

9

Basic Registers

A number of 8052 registers can be considered "basic." Very little can be done without

them and a detailed explanation of each one is warranted to make sure the reader understands

these registers before getting into more complicated areas of development.

The Accumulator: If you've worked with any other assembly language you will be

familiar with the concept of an accumulator register.

The Accumulator, as its name suggests, is used as a general register to accumulate the

results of a large number of instructions. It can hold an 8-bit (1-byte) value and is the most

versatile register the 8052 has due to the sheer number of instructions that make use of the

accumulator. More than half of the 8052's 255 instructions manipulate or use the

Accumulator in some way. For example, if you want to add the number 10 and 20, the

resulting 30 will be stored in the Accumulator. Once you have a value in the Accumulator

you may continue processing the value or you may store it in another register or in memory.

The "R" Register: The "R" registers are sets of eight registers that are named R0, R1,through R7. These registers are used as auxiliary registers in many operations. To continue

with the above example, perhaps you are adding 10 and 20. The original number 10 may be

stored in the Accumulator whereas the value 20 may be stored in, say, register R4. To process

the addition you would execute the command:

ADD A, R4

The B Register: The "B" register is very similar to the Accumulator in the sense that it

may hold an 8-bit (1-byte) value. The "B" register is only used implicitly by two 8052

instructions: MUL AB and DIV AB. Thus, if you want to quickly and easily multiply or

divide A by another number, you may store the other number in "B" and make use of these

two instructions.

Aside from the MUL and DIV instructions, the "B" register are often used as yet

another temporary storage register much like a ninth "R" register.


10/32

10

The Program Counter: The Program Counter (PC) is a 2-byte address that tells the

8052 where the next instruction to execute is found in memory. When the 8052 is initialized

PC always starts at 0000h and is incremented each time an instruction is executed

The Data Pointer: The Data Pointer (DPTR) is the 8052s only user-accessible 16-bit (2-

byte) register. The Accumulator, "R" registers, and "B" register are all 1-byte values. The PC

just described is a 16-bit value but isn't directly user-accessible as a working register.

DPTR, as the name suggests, is used to point to data. It is used by a number of

commands that allow the 8052 to access external memory. When the 8052 accesses external

memory it accesses the memory at the address indicated by DPTR.

While DPTR is most often used to point to data in external memory or code memory,

many developers take advantage of the fact that it's the only true 16-bit register available. It is

often used to store 2-byte values that have nothing to do with memory locations.

The Stack Pointer: The Stack Pointer, like all registers except DPTR and PC, may hold

an 8-bit (1-byte) value. The Stack Pointer is used to indicate where the next value to be

removed from the stack should be taken from.

When you push a value onto the stack, the 8052 first increments the value of SP and

then stores the value at the resulting memory location. When you pop a value off the stack,

the 8052 returns the value from the memory location indicated by SP and then decrements the

value of SP.

2.6 CENTRAL PROCESSING UNIT

The CPU is the brain of the microcontrollers reading users programs andexecuting the expected taskas per instructions stored there in. Its primary elements

are an 8 bit Arithmetic Logic Unit (ALU ) , Accumulator (Acc ) , few more 8 bit

registers , B register, Stack Pointer (SP ) , Program Status Word (PSW) and 16 bit

registers, Program Counter (PC) and Data Pointer Register (DPTR).

The ALU (Acc) performs arithmetic and logic functions on 8 bit input

variables. Arithmetic operations include basic addition, subtraction, and multiplication


11/32

11

and division. Logical operations are AND, OR, Exclusive OR as well as rotate, clear,

complement and etc. Apart from all the above, ALU is responsible in conditional

branching decisions, and provides a temporary place in data transfer operations

within the device.

Program Status Word (PSW): It keeps the current status of the ALU in

different bits. Stack Pointer (SP) is an 8 bit register. This pointer keeps track of

memory space where the important register information is stored when the program

flow gets into executing a subroutine. The stack portion may be placed in

anywhere in the on-chip RAM. But normally SP is initialized to 07H after a device

reset and grows up from the location 08H. The Stack Pointer is automatically

incremented or decremented for all PUSH or POP instructions and for all subroutine

calls and returns.

Program Counter (PC): It is the 16 bit register giving address of next

instruction to be executed during program execution and it always points to the

Program Memory space. Data Pointer (DPTR) is another 16 bit addressing register

that can be used to fetch any 8 bit data from the data memory space. When it is not

being used for this purpose, it can be used as two eight bit registers.

Timers/Counters 8051 have two 16 bit Timers/Counters capable of working in

different modes. Each consists of a High byte and a Low byte which can be

accessed under software. There is a mode control register and a control register to

configure these timers/counters in number of ways.

Serial Ports Each 8051 microcomputer contains a high speed full duplex (means

you can simultaneously use the same port for both transmitting and receiving

purposes) serial port which is software configurable in 4 basic modes: 8 bit UART; 9

bit UART; inter processor Communications link or as shift register I/O expander.

For the standard serial communication facility, 8051 can be programmed for UART

operations and can be connected with regular personal computers, teletype writers,

modem at data rates between 122 bauds and 31 kilo bauds. Getting this facility is

made very simple using simple routines with option to elect even or odd parity


12/32

12

CHAPTER 3

AT89S52 MICROCONTROLLERS

3.1 FEATURES OF AT89S52

Compatible with MCS-51 Products 8K Bytes of In-System Programmable (ISP) Flash Memory Endurance: 10,000 Write/Erase Cycles 4.0V to 5.5V Operating Range Fully Static Operation: 0 Hz to 33 MHz Three-level Program Memory Lock 256 x 8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters Eight Interrupt Sources

3.2 DESCRIPTION OF AT89S52

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with

8K bytes of in-system programmable Flash memory. The device is manufactured using

Atmels high-density nonvolatile memory technology and is compatible with the industry

standard 80C51 instruction set and pin out. The on-chip Flash allows the program memory to

be reprogrammed in-system or by a conventional nonvolatile memory pro-grammar. By

combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip,

the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S52 provides the

following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog

timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt

architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the

AT89S52 is designed with static logic for operation down to zero frequency and supports two

software selectable power saving modes. The Idle Mode stops the CPU while allowing the

RAM, timer/counters, serial port, and interrupt system to continue functioning.


13/32

13

3.3 PIN DIAGRAM OF AT89S52

Fig 3.1 40-lead pdip

Pin Description

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can

sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-

impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data

bus during accesses to external program and data memory. In this mode, P0 has internal pull-

ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes

during program verification.


14/32

14

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output

buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled

high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are

externally being pulled low will source current (IIL) because of the internal pull-ups. In

addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input

(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the

following table. Port 1 also receives the low-order address bytes during Flash programming

and verification.

Table 3.1 Alternate function of port 1Port 2



high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are

externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2

emits the high-order address byte during fetches from external program memory and during

accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In thisapplication, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external

data memory that uses 8-bit addresses (MOVX @ RI); Port 2 emits the contents of the P2

Special Function Register. Port 2 also receives the high-order address bits and some control

signals during Flash programming and verification.


15/32

15

Port 3



high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that areexternally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives

some control signals for Flash programming and verification. Port 3 also serves the functions

of various special features of the AT89S52, as shown in the following table.

Table 3.2 Alternate function of port 3

RST

Reset input. A high on this pin for two machine cycles while the oscillator is running

resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out.

The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the

default state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG

Address Latch Enable (ALE) is an output pulse for latching the low byte of the

address during accesses to external memory. This pin is also the program pulse input (PROG)

during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the

oscillator frequency and may be used for external timing or clocking purposes. Note,

however, that one ALE pulse is skipped during each access to external data memory. If

desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,

ALE is active only during a MOVX or MOVC instruction.


16/32

16

PSEN

Program Store Enable (PSEN) is the read strobe to external program memory. When

the AT89S52 is executing code from external program memory, PSEN is activated twice

each machine cycle, except that two PSEN activations are skipped during each access to

external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to

fetch code from external program memory locations starting at 0000H up to FFFFH. Note,

however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should

be strapped to VCC for internal program executions. This pin also receives the 12 volt

programming enable voltage (VPP) during Flash programming.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

3.4 SPECIAL FUNCTION REGISTERS

A map of the on-chip memory area called the Special Function Register (SFR) space

is shown in Table 5-1. Note that not all of the addresses are occupied, and unoccupied

addresses may not be implemented on the chip. Read accesses to these addresses will in

general return random data, and write accesses will have an indeterminate effect. User

software should not write 1s to these unlisted locations, since they may be used in future

products to invoke new features. In that case, the reset or inactive values of the new bits will

always be 0.


17/32

17

Timer 2 Registers:

Control and status bits are contained in registers T2CON (shown in Table 5- 2) and

T2MOD (shown in Table 10-2) for Timer 2. The register pair (RCAP2H, RCAP2L) is the

Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.

Interrupt Registers:

The individual interrupt enable bits are in the IE register. Two priorities can be set for

each of the six interrupt sources in the IP register.

Memory Organization MCS-51 devices have a separate address space for Program and Data

Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.

Program Memory

If the EA pin is connected to GND, all program fetches are directed to external

memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H

through 1FFFH are directed to internal memory and fetches to addresses 2000H through

FFFFH are to external memory.

Data Memory

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a

parallel address space to the Special Function Registers. This means that the upper 128 bytes

have the same addresses as the SFR space but are physically separate from SFR space. When

an instruction accesses an internal location above address 7FH, the address mode used in the

instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR

space. Instructions which use direct addressing access the SFR space.

Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be

subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer

Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the

WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location


18/32

18

0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator

is running. The WDT timeout period is dependent on the external clock frequency. There is

no way to disable the WDT except through reset (either hardware reset or WDT overflow

reset). When WDT over-flows, it will drive an output RESET HIGH pulse at the RST pin.

Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST

register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by

writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter

overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is

enabled, it will increment every machine cycle while the oscillator is running. This means theuser must reset the WDT at least every 16383 machine cycles. To reset the WDT the user

must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT

counter cannot be read or written. When WDT overflows, it will generate an output RESET

pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC = 1/FOSC. To

make the best use of the WDT, it should be serviced in those sections of code that will

periodically be executed within the time required to prevent a WDT reset.

UART

The UART in the AT89S52 operates the same way as the UART in the AT89S52 and

AT89C52.

Timer 0 and 1

Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in

the AT89S52 and AT89C52.

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event

counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 5-

2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud

rate generator. The modes are selected by bits in T2CON, as shown in Table 10-1. Timer 2


19/32

19

consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is

incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the

count rate is 1/12 of the oscillator frequency.

Table 3.3 Timer 2 operating modes

In the Counter function, the register is incremented in response to a 1-to-0 transition

at its corresponding external input pin, T2. In this function, the external input is sampled

during S5P2 of every machine cycle. When the samples show a high in one cycle and a low

in the next cycle, the count is incremented. The new count value appears in the register

during S3P1 of the cycle following the one in which the transition was detected. Since two

machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the

maximum count rate is 1/24 of the oscillator frequency.

Capture Mode

In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 =

0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit

can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same

operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2

and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition

at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an

interrupt. The capture mode is illustrated in Figure 10-1.


20/32

20

Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-

reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the

SFR T2MOD (see Table 10-2). Upon reset, the DCEN bit is set to 0 so that timer 2 willdefault to count up. When DCEN is set, Timer 2 can count up or down, depending on the

value of the T2EX pin.

Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure

12-1. This pin, besides being a regular I/O pin, has two alternate functions. It can be

programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle

clock ranging from 61 Hz to 4 MHz (for a 16 -MHz operating frequency). To configure the

Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE

(T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out

frequency depends on the oscillator frequency and the reload value of Timer 2 capture

registers (RCAP2H, RCAP2L), as shown in the following equation. In the clock-out mode,

Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is

used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a

clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies

cannot be determined independently from one another since they both use RCAP2H and

RCAP2L

Fig 3.2 Timer 2 in clock-out mode


21/32

21

3.5 INTERRUPTS

The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and

INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These

interrupts are all shown in Figure 13-1. Each of these interrupt sources can be individually

enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also

contains a global disable bit, EA, which disables all interrupts at once. Note that Table 13-1

shows that bit position IE.6 is unimplemented. User software should not write a 1 to this bit

position, since it may be used in future AT89 products. Timer 2 interrupt is generated by the

logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by

hardware when the service routine is vectored to. In fact, the service routine may have to

determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to

be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the

cycle in which the timers overflow. The values are then polled by the circuitry in the next

cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which

the timer overflows.

Table 3.4 Interrupt enables table register


22/32

22

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain

active. The mode is invoked by software. The content of the on-chip RAM and all the special

functions registers remain unchanged during this mode. The idle mode can be terminated by

any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a

hardware reset, the device normally resumes pro-gram execution from where it left off, up to

two machine cycles before the internal reset algorithm takes control. On-chip hardware

inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To

eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by

a reset, the instruction following the one that invokes idle mode should not write to a port pin

or to external memory

Power-down Mode

In the Power-down mode, the oscillator is stopped, and the instruction that invokes

Power-down is the last instruction executed. The on-chip RAM and Special Function

Registers retain their values until the Power-down mode is terminated. Exit from Power-

down mode can be initiated either by a hardware reset or by an enabled external interrupt.

Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be

activated before VCC is restored to its normal operating level and must be held active long

enough to allow the oscillator to restart and stabilize.

Programming the Flash Parallel Mode

The AT89S52 is shipped with the on-chip Flash memory array ready to be

programmed. The programming interface needs a high-voltage (12-volt) program enable

signal and is compatible with conventional third-party Flash or EPROM programmers. The

AT89S52 code memory array is programmed byte-by-byte.


23/32

23

CHAPTER 4

LDR, MOTOR

4.1 LIGHT DEPENDENT RESISTOR

Light dependent resistors are used to re-charge a light during different changes in the

light, or they are made to turn a light on during certain changes in lights. One of the most

common uses for light dependent resistors is in traffic lights. The light dependent resistor

controls a built in heater inside the traffic light, and causes it to recharge overnight so that the

light never dies. Other common places to find light dependent resistors are in: infrared

detectors, clocks and security alarms.

Identification

1. A light dependent resistor is shaped like a quarter. They are small, and can be nearlyany size. Other names for light dependent resistors are: photoconductors, photo

resistor, or a CdS cell. There are black lines on one side of the light dependent

resistor. The overall color of a light dependent resistor is gold. Usually other electrical

components are attached to the light dependent resistor by metal tubes soldered to the

sides of the light dependent resistor.

Function

2. The main purpose of a light dependent resistor is to change the brightness of a light indifferent weather conditions. This can easily be explained with the use of a watch.

Some watches start to glow in the dark so that it is possible to see the time without

having to press any buttons. It is the light dependent resistor that allows the watch to

know when it has gotten dark, and change the emissions level of the light at that time.

Traffic lights use this principle as well but their lights have to be brighter in the day

time.

Considerations

3. Light dependent resistors have become very useful to the world. Without them lightswould have to be on all the time, or they would have to be manually adjusted. A light


24/32

24

dependent resistor saves money and time for any creation that needs a change in light.

Another feature of the light dependent resistor is that it can be programmed to turn on

with changes in movements. This is an extremely useful feature that many security

systems employ. Security would be harder without light dependent resistors.

Expert Insight

4. It is possible to build a light dependent resistor into an existing light circuit. There aremany electrical plans that outline how to install one. Usually the sign for a light

dependent resistor on these plans is marked by a rectangle with two arrows pointing

down to it. This shows the placement of the light dependent resistor in the circuit so

that it will work properly. Usually only an electrician can build new circuits, however.

Benefits

5. There are many great benefits to light dependent resistors. They allow less power tobe used in many different kinds of lights. They help lights last much longer. They can

be trigged by several different kinds of triggers, which is very useful for motion lights

and security systems. They are also very useful in watches and cars so that the lights

can turn on automatically when it becomes dark. There are a lot of things that light

dependent resistors can do.

4.2 DC MOTOR

Principles of operation

In any electric motor, operation is based on simple electromagnetism. A current-

carrying conductor generates a magnetic field; when this is then placed in an external

magnetic field, it will experience a force proportional to the current in the conductor, and to

the strength of the external magnetic field. As you are well aware of from playing with

magnets as a kid, opposite (North and South) polarities attract, while like polarities (North

and North, South and South) repel. The internal configuration of a DC motor is designed to

harness the magnetic interaction between a current-carrying conductor and an external

magnetic field to generate rotational motion.
http://encyclobeamia.solarbotics.net/articles/current.htmlhttp://encyclobeamia.solarbotics.net/articles/current.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.htmlhttp://encyclobeamia.solarbotics.net/articles/current.htmlhttp://encyclobeamia.solarbotics.net/articles/current.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.htmlhttp://encyclobeamia.solarbotics.net/articles/current.htmlhttp://encyclobeamia.solarbotics.net/articles/current.html


25/32

25

Let's start by looking at a simple 2-pole DC electric motor (here red represents a

magnet or winding with a "North" polarization, while green represents a magnet or winding

with a "South" polarization).

Every DC motor has six basic parts -- axle, rotor (a.k.a., armature), stator,

commutator, field magnet(s), and brushes. In most common DC motors (and all that

BEAMers will see), the external magnetic field is produced by high-strength permanent

magnets1. The stator is the stationary part of the motor -- this includes the motor casing, as

well as two or more permanent magnet pole pieces. The rotors (together with the axle and

attached commutator) rotate with respect to the stator. The rotor consists of windings

(generally on a core), the windings being electrically connected to the commutator. The

above diagram shows a common motor layout -- with the rotor inside the stator (field)

magnets.

The geometry of the brushes, commutator contacts, and rotor windings are such that

when power is applied, the polarities of the energized winding and the stator magnet(s) are

misaligned, and the rotor will rotate until it is almost aligned with the stator's field magnets.

As the rotor reaches alignment, the brushes move to the next commutator contacts, and

energize the next winding. Given our example two-pole motor, the rotation reverses the

direction ofcurrent through the rotor winding, leading to a "flip" of the rotor's magnetic field,

driving it to continue rotating.

In real life, though, DC motors will always have more than two poles (three is a very

common number). In particular, this avoids "dead spots" in the commutator. You can imagine

how with our example two-pole motor, if the rotor is exactly at the middle of its rotation

(perfectly aligned with the field magnets); it will get "stuck" there. Meanwhile, with a two-

pole motor, there is a moment where the commutator shorts out the power supply (i.e., bothbrushes touch both commutator contacts simultaneously). This would be bad for the power

supply, waste energy, and damage motor components as well. Yet another disadvantage of

such a simple motor is that it would exhibit a high amount of torque "ripple" (the amount of

torque it could produce is cyclic with the position of the rotor).

So since most small DC motors are of a three-pole design, let's tinker with the

workings of one via an interactive animation
http://encyclobeamia.solarbotics.net/articles/dc.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.htmlhttp://encyclobeamia.solarbotics.net/articles/beam.htmlhttp://encyclobeamia.solarbotics.net/articles/current.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.htmlhttp://encyclobeamia.solarbotics.net/articles/torque.htmlhttp://encyclobeamia.solarbotics.net/articles/torque.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.htmlhttp://encyclobeamia.solarbotics.net/articles/torque.htmlhttp://encyclobeamia.solarbotics.net/articles/torque.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.htmlhttp://encyclobeamia.solarbotics.net/articles/current.htmlhttp://encyclobeamia.solarbotics.net/articles/beam.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.html


26/32

26

You'll notice a few things from this -- namely, one pole is fully energized at a time

(but two others are "partially" energized). As each brush transitions from one commutator

contact to the next, one coil's field will rapidly collapse, as the next coil's field will rapidly

charge up (this occurs within a few microsecond). We'll see more about the effects of this

later, but in the meantime you can see that this is a direct result of the coil windings' series

wiring:

The use of an iron core armature (as in the Mabuchi, above) is quite common, and has

a number of advantages. First off, the iron core provides a strong, rigid support for the

windings a particularly important consideration for high-torque motors. The core also

conducts heat away from the rotor windings, allowing the motor to be driven harder than

might otherwise be the case. Iron core construction is also relatively inexpensive compared

with other construction types.

But iron core construction also has several disadvantages. The iron armature has a

relatively high inertia which limits motor acceleration. This construction also results in high

winding inductances which limits brush and commutator life.

In small motors, an alternative design is often used which features a 'coreless' armature

winding. This design depends upon the coil wire itself for structural integrity. As a result, the

armature is hollow, and the permanent magnet can be mounted inside the rotor coil. Coreless

DC motors have much lower armature inductance than iron-core motors of comparable size,

extending brush and commutator life.

Fig 4.1 Diagram courtesy ofMicro Motors

The coreless design also allows manufacturers to build smaller motors; meanwhile, due to the

lack of iron in their rotors, coreless motors are somewhat prone to overheating. As a result,

this design is generally used just in small, low-power motors. BEAMers will most often see

coreless DC motors in the form of pager motors.
http://encyclobeamia.solarbotics.net/articles/torque.htmlhttp://encyclobeamia.solarbotics.net/articles/inductance.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.htmlhttp://encyclobeamia.solarbotics.net/articles/inductance.htmlhttp://www.micromo.com/http://www.micromo.com/http://encyclobeamia.solarbotics.net/articles/beam.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.htmlhttp://encyclobeamia.solarbotics.net/articles/beam.htmlhttp://www.micromo.com/http://encyclobeamia.solarbotics.net/articles/inductance.htmlhttp://encyclobeamia.solarbotics.net/articles/dc.htmlhttp://encyclobeamia.solarbotics.net/articles/inductance.htmlhttp://encyclobeamia.solarbotics.net/articles/torque.html


27/32

27

CHAPTER 5

WORKING FLOW OF THE PROJECT

5.1 BLOCK DIAGRAM

Fig 5.1 Block diagram

8051

MICRO

CONTRPLLER

REGULATED

POWER SUPPLY

MOTOR

LDR1

LDR 2

LDR 3


28/32

28

In this project SMART SOLAR TRACKING SYSTEM FOR OPTIMAL

POWER GENERATION we are going to use LDRs and DC Motor. And the power supply

will be given from the regulated power supply.

In this project the LDRs will sense the sun light and whichever the side there is more

sunlight at that side the motor will rotates. Here the motor will be connected to the SOLAR

PANEL unit. By this process we can easily gain more power for the solar panel.

5.2 HARDWARE:

Regulated Power Supply

A variable regulated power supply, also called a variable bench power supply,

is one where you can continuously adjust the output voltage to your requirements.

Varying the output of the power supply is the recommended way to test a project after

having double checked parts placement against circuit drawings and the parts

placement guide.

This type of regulation is ideal for having a simple variable bench power

supply. Actually this is quite important because one of the first projects a hobbyist

should undertake is the construction of a variable regulated power supply. While a

dedicated supply is quite handy e.g. 5V or 12V, it's much handier to have a variable

supply on hand, especially for testing.

Most digital logic circuits and processors need a 5 volt power supply. To use

these parts we need to build a regulated 5 volt source. Usually you start with an

unregulated power to make a 5 volt power supply; we use a LM7805 voltage regulator

IC (Integrated Circuit). The IC is shown below.


29/32

29

Fig5.2: Top view of LM7805

The LM7805 is simple to use. You simply connect the positive lead of your

unregulated DC power supply (anything from 9VDC to 24VDC) to the Input pin,

connect the negative lead to the Common pin and then when you turn on the power,

you get a 5 volt supply from the Output pin.

5.3 Circuit Features

Brief description of operation: Gives out well regulated +5V output, output

current capability of 100 mA

Circuit protection: Built-in overheating protection shuts down output when

regulator IC gets too hot

Circuit complexity: Very simple and easy to build

Circuit performance: Very stable +5V output voltage, reliable operation

Availability of components: Easy to get, uses only very common basic

components


30/32

30

Design testing: Based on datasheet example circuit, I have used this circuit

successfully as part of many electronics projects

Applications: Part of electronics devices, small laboratory power supply

Power supply voltage: Unregulated DC 8-18V power supply

Power supply current: Needed output current + 5 mA

Component costs: Few dollars for the electronics components + the input

transformer cost

Block Diagram

Fig 5.3 components of a linear power supply


31/32

31

CHAPTER 6

CONCLUSSION

The project DEVELOPMENT OF SUN TRACKING SOLAR PANEL FOR

OPTIMAL ENERGY GENERATED has been successfully designed and tested.

It has been developed by integrating features of all the hardware components used.

Presence of every module has been reasoned out and placed carefully thus contributing to the

best working of the unit.

Secondly, using highly advanced ICs and with the help of growing technology the

project has been successfully implemented.


32/32

32

REFERENCES

1. The 8051 Micro controller and Embedded Systems, Muhammad AliMazid2. The 8051 Micro controller Architecture, Programming &Applications -Kenneth

J.Ayala

3. Fundamentals of Microprocessors and Microcomputers-B.Ram4. Microprocessor Architecture, Programming & Applications-Ramesh S.Gaonkar5. "Electronic Components-D.V.Prasad6. Wireless Communications - Theodore S. Rappaport7. Mobile Tele Communications - William C.Y. Lee

Date post:	05-Apr-2018
Category:	Documents
Upload:	ram-sankar-pradeep
View:	221 times
Download:	0 times

Sudheer Mini

Documents