Suming Lai, Boyuan Yan and Peng Li Department of Electrical and Computer Engineering

ICCAD 2012 Stability Assurance and Design Optimization of Large PDNs with Multiple LDOs

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Stability Assurance and Design Optimization of Large Power Delivery Networks with Multiple On-Chip Voltage Regulators

Suming Lai, Boyuan Yan and Peng LiDepartment of Electrical and Computer EngineeringTexas A&M University{laisuming, byan, pli} @ tamu.edu


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Low Power and Power Delivery Design Trends

[ITRS 2011]

Current

Vcc

[Hazucha et al./Intel JSSC, 2005] [Guo et al., JSSC, 2010] [El-Nozahi et al., JSSC, 2010]

On-chip Power Grids~10-100 million nodes

WireSizing/Decap

Insertion

PCB/Package Design[source: Ansys]

On-Chip Voltage Regulation: A Significant Current Trend


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Moving Towards Distributed On-Chip Voltage Regulation

Benefits in Supply Noise and Efficiency[Zeng et al., DAC, 2010]

VRM VRM

VRMVRM

D1 D2D4D3

Increase the number of regulators

VRM VRM

VRMVRM

VRM VRM

VRMVRM

VRM VRM

VRMVRM

VRM VRM

VRMVRM

[Bulzacchelli et al. IBM/JSSC, 2012]Recent Industrial Demonstration

A Network of Micro-Regulators


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Design Management Challenge

Analog Design Team Physical Design Team

Gain Bandwidth Bias

Current Phase

Margin Noise Load …

Amp

IR Drop Decap

insertion Wire

Sizing Package DFM …

Regulator Design Power Grids Design

Integrate LDOs with the grids

Stability??

Decoupled Design Still Very Desirable!


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Phase Margin

How does it work?► Target one loop► Single input/single output► Lump load (capacitor)

Analog Designer’s View of Stability

Reality: Loops between LDOs Distributive load network


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Heavily Oscillate

Quickly Settled

Slightly Fluctuate

Load Current

“Analog Designer’s” Approach to PDN Stability

LDO LDO LDO LDO

Global VDD Grids

Regulated Grids

Global GND GridsPCB & Pckg

Pole Movements

Come up a ‘stable’ LDO w/ a lump load (~120º phase margin) Hope it will work for the network


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Multiple regulators in the network

Complex interactions between active regulators and distributed load (lots of loops)

Complex interactions between different regulators (lots of loops)

Why Doesn’t It Work?

Global VDD Grids

Regulated Grids

Global GND Grids

LDOLDO LDO…

Pckg

& P

CB


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“Numerical Analyst’s” Approach: Pole AnalysisTreat the PDN as a

whole

Perform exhaustivepole/eigenvalue analysis

(cubic cost)

Too costlyfor typical PDNs

Even more intractable if LDO design is iterated


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Proposed Work Goals

► Feasible checking of network stability► Feasible stability-ensuring LDO design with network stability► Localized checking and design methodologies

How► Develop Hybrid Stability Theory for PDNs with distributed regulation► New (localized) Hybrid Stability Margin (HSM) for regulator design► Efficient stability checking method

Largely separated design methodology► LDO design with minimum load information

Regulator design implications and design exploration► Identify key design parameters/knobs for achieving HSM► Identify LDO topology dependency and new design technique► Tradeoffs with other performances


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Basic Theoretical Approach Partitioning and modeling

► Separate LDOs from the passive loads► Use MIMO modeling for both parts► Expose key network-level interactions and loops

Key system properties for ensuring stability► Small-Gain network-level loops► Passivity both passive loads & active regulators

– Counterintuitive for analog design but it works …

Hybrid Stability Theory► Combine Small-Gain & Passivity ► Provide more flexibility and reduce pessimism


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Our Network Modeling Strategy

G Block:

Spatially spread LDOs

H Block:

RLC Sub-Network

PDN wih multiple LDOs


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Block Models LDOs: Y-parameter model

RLC network: Z-parameter model

V1 V2

Admittance Matrix of LDO Block

Impedance Matrix of the RLC sub-network


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System Model for Stability Analysis

LDOLDOLDO …

Signal Loops

LDO

RLC

LDO

RLC


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L-2 gain, g

► General definition:

System Concepts (1): Gain

InputsOutputs

System

1

2

2n

…

1

2

2n

…

2

2

,2

supxy

xx 0

Lg System output

System input

}))()((max{max T

0g

jjii

HH

LTI systems:

Maximum Possible Amplification


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Stability Approach #1: Small-Gain How to stabilize the system by controlling the gain?

Small-Gain Theorem

gH

gG

gH

gG

gGgH < 1[V. D. Schaft, L2-gain and passivity techniques in nonlinear control. 2000]


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Problems? Useful but a stringent condition

Over-constrains gain in practice

Issues with voltage regulation► RLC sub-network resonance:

impedance peaking at mid/high frequencies

► Must control LDO’s gain across the entire frequency

gH

gG

Severe Load/Line Regulation Performance Degradation


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Can We Do It Differently? Intuition: leverage Passivity

Can Active analog circuits be made Passive?► Designers do not usually think about it this way► Full Passivity can be practically hard or wasteful …

Passive NetworkLDO Block

If passive

NetworkStable!


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System Concepts (2): Passivity Passive systems do not produce power

Strictly passive systems burn power

LTI system with transfer matrix Y is passive if 0)}

2)()((min{min)(

T

0min

jjii

YYY

strictly passive

≥d >0


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Stability Approach #2: PassivityPassivity theorem

► Interconnection of H and G is stable, if they are passive, and at least one of them is strictly passive

[V. D. Schaft, L2-gain and passivity techniques in nonlinear control. 2000]


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Can Active Analog Circuit Look Passive? A real study of LDO passivity

– Not fully passive in general – Don’t want to be fully passive:

No ‘active’ voltage regulation!

Define Local Passivity– Intuitive definition:

More formal definition: Exist d ≥0 and e ≥0, s.t.

].,[,0)2

)()((min)( 21

T

min

jj

ii

YYY

Realistic LDO Circuit[Lai/Li, AICSP’12]

[Lai/Yan/Li,TCAD, submitted]


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Our design insights based on realistic LDO designs

Explore Local Passivity for Stability

LDO Bandwidth Package

Resonance High Freq.

High LDO gain High RLC

impedance Apply repartitioning

technique

Force loop gain <1

[Lai/Yan/Li,TCAD,Submitted]

Impedance peaking due to package resonance

Force passivity of LDOs

Either gain or passivity

Not critical

Force loop gain <1

Frequency Low High


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Stability Approach #3: General Hybrid Stability The interconnection of two LTI systems H and G is

stable, if at each frequency ► Either H(j) or G(j) is passive and the other one is strictly

passive; (Passivity condition)► Loop gain (Gain condition)1)()(

22 jj GH

[Forbes et al., IET Control Theory and Application 2010]


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Stability Approach #3: Application to PDNHow to apply to our case

Practical RLC sub-network is strictly passive

Rigorous proof

Gain Condition Passivity Either Condition

Strict Passivity ?RLC:

Each port has a serial resistor

LDO LDO LDO LDO

Global VDD Grids

Regulated GridsLoading Circuits

Global GND GridsPCB & Pckg

PDN:

[Lai/Yan/Li,TCAD, submitted]


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Localized Stability Checking – LDOs Passivity check

Gain check

G2nx2n = (Block Diagonal)

))}.()(({min)( T,22,22,,1;2,1min jj jjinji YYG 2n2n

.)(max)(22,2,,12

jj ini YG

AC analysis on individual LDOs!


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Localized Stability Checking – RLC NetowrkPassivity check

► Strictly passive, theoretically proved► No need to check

Gain check► One time AC analysis – frequency sweeping for ► Routinely done by power grid/package designers ► No need to re-run if LDOs are re-designed or tuned

2)( jH


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New Hybrid Stability Margin (HSM) 2D passivity/gain space

► LDOs: min(G) >0 passive

► LDOs & RLC network: ||H(j)||2||G(j)||2 < 1 small gain

Localized HSM for LDO design► Normalized Distance Measure to border of instability► Negative value means instability


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Localized Checking and Design Flow

Our flow using HSM Old flow using PM

TuneLDO design

TuneLDO design

AC SimulationAC Simulation

Check Phase Margin

Check Hybrid Stability Margin

Performance Check

P

F

P

F

Finish

Performance Check

P

PFinish

F

F

PG/Package Characterization


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HSM Design Implications (1) Design freedom along the

frequency axis ► Choose either passivity condition or

small-gain to satisfy HSM

Our findings► Key design knobs:

– DC/low-frequency gain, UGF, output impedance, dominant pole

► Choose one of the properties to minimize performance degradation and overhead: area/powerLDO Bandwidth

PackageResonance High Freq.

Small Gain Passivity Small Gain (or Passivity)

Width of Mp

Width of M’p Mc and Mdb

Cc1, Cc2, Cc3, and C1

Key Ckt Parameters:


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New Circuit

Add a small pull-down transistor to increase |is|

HSM Design Implications (2) Example: an effective way to control loop gain

► |is| > |iEA| (no degradation on “physical” load/line regulation)

New LDO Design Techniques

Topology Dependency

Change the topology of output stage to increase |is|


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Automated Design Optimization LDO design topology

Key design knobs► Width of Mp

► Width of M’p

► Mc and Mdb

► Cc1, Cc2, Cc3, and C1

Joint Perform/Stability Nonlinear Opt. driven by HSM constraint

[Lai & Li, AICSP’12]

Tune |is|, good for HSM

Tunes GBW and HSM

Tune Pg

Tune HSM, Accuracy, Zout and GBW


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Verification using a Small PDN (1) Resort to pole analysis for verification

Pole Movements

Initial LDO Design: Phase Margin = 118°

Cause Network Instability

Fixed/Optimized Design: Stable


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Verification using a Small PDN (2) Time-domain verification of network-level stability for the

fixed/optimized design

Stable


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Design for a 200K-Node PDN Initial design phase margin = 118°

Loop gain/min as functions of frequency


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Time-Domain Network-Level Stability Check Initial Design

Sustained Oscillation!


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Optimized Design for the 200K-Node PDN Fixed/optimized design

Loop gain/min as functions of frequency


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Time-Domain Network-Level Stability Check Fixed/Optimized Design

VoltageSettled!


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Runtime EfficiencyAC analysis of the passives

► Frequency range: 1Hz to 1THz ► Number of frequency samples (P): 2401► Our in-house simulator takes: 11 hours

LDO design iteration► ~100 design iterations ► LDO total optimization time: 116 minutes

Dominant Cost► One-time AC analysis of the passives


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Design Comparison & TradeoffsDesign performances

► DC regulation accuracy► Output Impedance (dynamic regulation accuracy)► Quiescent power (power efficiency under zero/light load)► Power utilization efficiency:

Defined by output admittance () achieved per unit quiescent power consumption

Reference design► Manual design with the best FOM (figure of merits on

performances) and a high phase margin

Compare with LDOs designed using our flow


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Design Comparison & Tradeoffs – Case 1 Stability-ensuring design using HSM constraint and our flow

► Performance optimization biased to output impedance

DC Accuracy Quiescent Power (mW)

Output Impedance (mW)

Power Utilization (1/mW∙W)

Initial LDO (Unstable)

99.96% 562.8 191.9 0.0092

Our Design(Stable)

99.90% 621.6 139.4 0.0115

Improvement - - 27.4% 24.9%

Degradation 0.06% 10.4% - -


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Design Comparison & Tradeoffs – Case 2

DC Accuracy

Quiescent Power (mW)

Output Impedance (mW)

Power Utilization (1/mW∙W)

Initial LDO(Unstable)

99.96% 562.8 191.9 0.0092

Our Design(Stable)

99.91% 408 234.7 0.0104

Improvement - 27.5% - 13.5%Degradation 0.05% - 22.3% -

Stability-ensuring design using HSM constraint and our flow► Performance optimization biased to Quiescent Power


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Summary (Distributed) on-chip voltage is a significant on-going

design trend

Stability is a great challenge for power delivery networks with distributed voltage regulation

To address this challenge requires to bring together:theory, CAD and circuit design

Developed a hybrid-stability based localized stability checking & design methodology

Studied the circuit design implications of imposing new HSM constraint and the resulting stability/performance tradeoffs


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Thanks !!

Q&A

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Suming Lai, Boyuan Yan and Peng Li Department of Electrical and Computer Engineering

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