Summary of EOC demonstrator

submissionpresented by A. Kluge

CERN/PH-ESEMarch 31, 2009

A. Klugea, G. Dellacasab, M. Fiorinia, P. Jarrona, J. Kaplona, F. Marchettob, E. Martina,d, S. Martoiub, G. Mazzab, M. Noya, A. Cotta Ramusinoc, P. Riedlera, A. Rivettib, S. Tiuraniemia

a CERN, Geneva Switzerland, b INFN Torino, Italy, c INFN Ferrara, Italy, d UCL Louvain la Neuve, Belgium

Outline

General architecture

submission procedure

submission problems

A. Kluge

EOC column architecture

A. Kluge

Jitter-free pixel signal to TDC in EOC

time-to-digital converter TDC

buffering & read-out processor

amplifier&

discriminator/time-walk-

compensator

reference clock

A. Kluge

45 x 40 pixel final chip

Addr.

Addr.

Addr.

Hit Arbiter Hit Arbiter Hit Arbiter

LVDSH

it Reg1

Addr.

Hit Arbiter

45

4045 45 45 45

Ref CLK320MHz

serializerDLL Digital processing

Hit R

eg2

Hit R

eg1

Hit R

eg2

Hit R

eg1

Hit R

eg2

Hit R

eg1

Hit R

eg2

32

45 x 1 demonstrator

LVDSH

it Reg1

Addr.

Hit Arbiter

45

45

Ref CLK320MHz

serializerDLL Digital processing

Hit R

eg2

32

45 x 1 demonstrator

Hit R

eg1

Addr

Hit Arbiter

45

Ref CLK320MHz

serializer &LVDS

DLL

Hit R

eg2

32

Pileup

EO

C0

EO

C1

EO

C2

EO

C3

EO

C4

EO

C5

EO

C6

EO

C7

EO

C8

Pixel cell frontend

Jan 18-22, 2009A. Kluge

Pixel cell frontend

A. Kluge

Pixel cell frontend

A. Kluge

Preamp; buffered cascode (NMOS input transistor), resistive feedback (200k)

Gain;70mV/fC (25mV/fC at preamp output)

Preamplifier AC coupled to shaper and discriminator stages

Consumption; 190 µA/pixel (70 µA in analog section, 40 µA digital part of comparator, 80 µA line driver )

Time to Digital Converter

Tapped delay line 32 cells, 100ps

Two hit registers One per both

leading and trailing edge

5 bit encoding

DLL

hit rising Hit Register 1

Ref CLK

32 to 5 bit encoder5

t0,t1,t3,…,tN-2,tN-1

32 to 5 bit encoder5

hit trailing Hit Register 2

Optimisation of transmission line drivers – pre-emphasis

Optimisation of transmission line drivers

Pre-emphasis

Amplitude

Transmission of pixel hit

Jan 18-22, 2009A. Kluge

Transmission of pixel hit

Jan 18-22, 2009A. Kluge

hit Arbiter

Aynchronous latch logic which

defines first arriving pixel hit out of 5 in one group

latches hit address unambiguiously

during time-over-threshold time + TDC acquisition time: ~ 10 ns, address of additional (piled up) hits in same pixel group is stored

March 17, 2009A. Kluge

Read-out

mode pin selects between 45 pixel column or 7 pixel column

9 x 320 MHz data stream can be disabled individually to test dependency

on digital noise

read-out is continuous stream of data

Verilog description of ASIC block & deserializer available

March 17, 2009A. Kluge

Several design changes after October-design-review on system level and on building block level.

4 design areas: Analog front-end – pixel cell hit information driver/receiver – pixel cell & EOC TDC & DLL & hit Arbiter – EOC digital read-out block – EOC

Design changes were practically terminated 3 weeks before submission dated

March 17, 2009A. Kluge

4 design areas: Analog front-end – pixel cell hit information driver/receiver – pixel cell &

EOC TDC & DLL & hit Arbitrer – EOC digital read-out block – EOC

March 17, 2009A. Kluge

Layout –EOC 130µm

A. Kluge6.7 mm

2.8

mm

Layout –EOC 130µm

A. Kluge

Ana

logu

e t

est

str

uctu

res

Dat

a g

rou

pin

g &

pix

el a

dd

res

s

Receiver2x23

Receiver2x23

pad

s

EO

C

test pads

test

pad

s

1 folded column of 45 pixels

test pixels

6.7 mm

2.8

mm

test

pix

els

Layout –EOC 130µm

A. Kluge

Ana

logu

e t

est

str

uctu

res

Dat

a g

rou

pin

g &

pix

el a

dd

res

s

pad

s

sensor 4.14 x 5.37 mm2

EO

C

test pads

test

pad

s 1 folded column of 45 pixels

6.7 mm

2.8

mm

ASIC

2 rows ASIC pads layout

Sensor edge

125 µ(90 µ?)

50 µ

50 µ

125µ(90 µ?)

>300 µ

62 µ

88 µ

50 µ

2000

at least 900 µ

Submission issues

Problems with submission of automatically generated digital blocks (in LM) in custom layout (in DM)

Problems with use of library I/O Pads both for design rule checks (ESD) and LVS (Calibre) Elena (&Jan & Xavier) were working for 3!

weeks At the end (simpler) Angelo-custom made

pads were used

March 17, 2009A. Kluge

Submission

Chip has been submitted: final LVS OK (with parameter mismatch due to extraction

of gate around). LVS has been checked also after stream in (with some

problems in LVDS_TX due to hierarchy; solved by flattening of the transmitter cell).

The new pads gives many ESD errors both in assura and calibre; difficult to solve in short time (new pad library needed).

Antenna errors with assura not detected (clean), few antenna errors with caliber (related to input bump bonding pad and triple well (this error appears only when chip option is switched -> most probably bug in caliber deck))

March 17, 2009A. Kluge

Submission

LVS match on full chip

DRC check, waivers on ESD design rules

Layout optimisation is possible – long lines between building blocks

Further simulation allows optimisation of full custom TDC part with automatically generated parts

March 17, 2009A. Kluge

Summary

Ambitious demonstrator functionality compared to initial approach

Difficult implementation as design kit needs optimisation and technology is new to us

These problems must be cleared for final submission

However, all LVS, DRC done

Required pre-submission simulations have been doneA. Kluge