SURFACE PASSIVATION AND JUNCTION ENGINEERING IN SILICON /
GERMANIUM METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-
TRANSISTORS FOR HIGH PERFORMANCE APPLICATION
A DISSERTATION
SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING
AND THE COMMITTEE ON GRADUATE STUDIES
OF STANFORD UNIVERSITY
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
Gaurav Thareja
March 2011
http://creativecommons.org/licenses/by-nc/3.0/us/
This dissertation is online at: http://purl.stanford.edu/xn709kq1250
© 2011 by Gaurav Thareja. All Rights Reserved.
Re-distributed by Stanford University under license with the author.
This work is licensed under a Creative Commons Attribution-Noncommercial 3.0 United States License.
ii
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Yoshio Nishi, Primary Adviser
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Paul McIntyre
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Krishna Saraswat
Approved for the Stanford University Committee on Graduate Studies.
Patricia J. Gumport, Vice Provost Graduate Education
This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file inUniversity Archives.
iii
ABSTRACT
The planar silicon MOSFET is facing diminishing performance returns in improvement
from device geometry scaling. Two alternative devices are being explored as possible
solutions to this problem. The first contender is a multi-gate device (FINFET or surround
gate) and the other is a MOSFET with high mobility channel material such as germanium, III-
V or carbon.
Ge has emerged as an important materials platform during recent years. With its high carrier
mobility and the ability to detect and emit photons at telecommunications wavelengths, Ge is
an attractive candidate for applications in both high performance electronics and
optoelectronics. Moreover due to its compatibility with conventional CMOS fabrication, it can
be processed using the standard manufacturing techniques that are currently used for silicon.
However Ge does present a number of unique challenges that must be overcome, including
issues of surface passivation, low n-type dopant solubility, and high dopant diffusivity.
In this work, the unique properties of surface passivation enabled by radical oxidation are
discussed. Some of the highlights are low temperature processing, substrate orientation
independent growth rate of dielectric and low interface density. Subsequently, this radical
oxidation is applied to 3D vertical gate all around (GAA) silicon MOSFET devices. Higher
drive current, lower gate leakage and higher gate dielectric breakdown voltage are
demonstrated for GAA devices using radical oxidation in comparison to thermal oxidation
In the second part, radical oxidation is investigated for GeO2 growth as an interfacial layer in
high-k / Ge gate stack. Using MOSCAP and n-MOSFET devices on Ge, low interface state
density combined with drive current and electron mobility enhancement is demonstrated for
Ge devices.
In the third part, the source/drain junctions for Ge are studied. Ultra-shallow junctions using
plasma immersion ion implantation are demonstrated. High n-type dopant activation in Ge
using laser annealing is realized along with high performance diodes, significant reduction of
contact resistance and integration in a MOSFET process flow.
iv
ACKNOWLEDGEMENTS
In Sanskrit, ‘gu’ means darkness and ‘ru’ means light. ‘Guru’ is a person who takes the
disciple from the darkness of ignorance to the light of knowledge. First and foremost, I would
like to thank my Guru, Prof. Yoshio Nishi for accepting me as his student and guiding me
through the PhD program and other walks of life. I am also grateful to my co-guru, Prof.
Krishna Saraswat for his valuable advice and tutelage. I have utmost respect for their vast
knowledge, experience and patience.
I would also like to thank Prof. Paul McIntyre for providing valuable comments on my PhD
thesis, Prof. Jelena Vuckovic for chairing my PhD oral examination and Prof. Ted Kamins for
providing me valuable research inputs.
I also extend my sincere thanks to Dr. Peter Griffin and Dr. James McVittie for their advice
and assistance on device fabrication and equipment design. I thank the entire SNF staff and
Sandra Eisensee for their equipment and financial management respectively.
I thank the Nishi, Saraswat and McIntyre group members for collaborations and making my
stay at Stanford memorable.
I especially value my friendship with Anshu, Sakshi, Kanupriya, Siddarth and Emel.
I would like to thank my mother, Dr.Vimal Thareja, for her love and inspiration; my father,
Dr. Dharam Vir Thareja for showing me throughout my life, the principles of dedication and
hard work. Without my parents, this mission would not have been successful. I would like to
thank my sister, Vrinda for her love and support.
v
TABLE OF CONTENTS
List of tables………………………………………………………………………………… viii
List of figures…………………………………………………………………………………..ix
Chapter 1: Introduction………………………………………………………………………....1
1.1 Scaling roadmap……………………………………………………………………...…1
1.2 Challenges in scaling of silicon MOSFETs……………………………………………..3
1.3 Device structures for better electrostatic control………………………………………..5
1.3.1 SOI MOSFETs…………………………………………………………..………..5
1.3.2 Multi gate MOSFETs……………………………………………………......…....7
1.4 High mobility channel materials……………………………………………………...…8
1.4.1 Surface passivation of germanium…………………………………………..…..10
1.4.2 Source/Drain junctions in Ge MOSFETs…………………………………...…...11
1.4.3 Germanium substrates……………………………………………………..….....13
1.4.4 Mobility enhancement due to strain and substrate/channel orientation of Ge
MOSFETs……………………………………………………………………….16
1.5 Conclusion.………………………………………………………………..…………..21
1.6 Layout of the thesis……………………………………………………………………21
References………………………………………………………………………………...21
Chapter 2: Surface passivation of 3D vertical MOS using radical oxidation………………....27
2.1 Introduction..………………………………………………………………………….27
2.2 Surface passivation of vertical surround gate MOSFET………………………...……28
2.3 Device fabrication…………………………………………………………...………...34
2.4 Results and discussion………………………………………………………………...34
2.5 Electrical characterization of vertical surround gate MOSFET…………………..…..36
2.6 Conclusion…………………………………………………………...………………..39
References………………………………………………………………………………...39
Chapter 3: Surface passivation of planar germanium MOS using radical oxidation…………42
3.1 Introduction……………………………………………………………..…………….42
3.2 Experiment…………………………………………………………………..………..47
vi
3.3 Results and discussion………………………………………………………………...47
3.4 Conclusion…………………………………………………………………………….51
References………………………………………………………………………………...51
Chapter 4: Source/Drain junction engineering in germanium n-MOSFET…………………...54
4.1 Introduction……………………………………………...…………………………….54
4.2 State of the art junction technology…………………………………………………...58
4.3 Junction metrology……………………………………………………………………61
4.4 Ultra-shallow junction (USJ) in Ge………………………………………………...…62
4.5 Activation of n-type dopants in Ge……………………………………………………63
4.6 Device fabrication……………………………………………………………………..66
4.7 Thermo-optical constants of Ge………….…………………………………………....66
4.8 Conclusion…………………………………...………………………………………..79
References……………………………………………………………………………...….80
Chapter 5: Conclusion and future work……………………………………………………….84
5.1 Conclusions……………………………………………………………………………84
5.2 Possible future work…………………………………………………………………..85
5.2.1 Surface passivation of three dimensional and planar Ge substrates…………….85
5.2.2 Source/Drain junction engineering in Ge MOS devices………………………..85
vii
LIST OF TABLES
Table 1.1 Material properties of bulk semiconductor………………………………...………...9
Table 4.1 Benchmark of annealing, dopant type and electrical activation across literature…..64
Table 4.2 Thermo-optical constants for Ge for a 532 nm laser…………………………...…..67
viii
LIST OF FIGURES
Fig 1.1 Moore’s law of scaling………………………………………………………...……….1
Fig. 1.2 Device feature size scaling…………………………………………………...………..2
Fig. 1.3 Sub 100nm CMOS technology scaling………………………………………...……...2
Fig. 1.4 Physical limits in scaling bulk silicon MOSFETs………………………………...…...3
Fig. 1.5 Possible sources of reduced mobility in high-k MOS gate stacks………………..…...4
Fig. 1.6 Partially depleted (PD) SOI MOSFET…………………………………………...……6
Fig. 1.7 Fully depleted (FD) SOI MOSFET……………………………………………...…….6
Fig. 1.8 Double gate MOSFET ...…………………………………………………...………….7
Fig. 1.9 Schematic of FINFET…………………………………………………………...…….8
Fig. 1.10 Higher rapid thermal nitridation temperature degrades the interfacial quality…..…10
Fig. 1.11 CV characteristics of GeO2 using plasma oxidation……………………..………....11
Fig. 1.12 Solid solubility of various dopants in Ge……………………………………...……12
Fig. 1.13 Low dopant diffusivity of p-type dopants in Ge………………………………...….12
Fig. 1.14 High dopant diffusivity and poor dopant activation of n-type dopants in Ge……....13
Fig. 1.15 Epitaxial growth of Ge on top of Si is not possible due to lattice mismatch……….14
Fig. 1.16 Multiple hydrogen anneal heteroepitaxy (MHAH) of Ge on Si………………….....14
Fig. 1.17 Gate-all-around (GAA) GeOI MOSFET structures using Rapid Melt Growth of
Ge……………………………………………………………………………………………...15
Fig. 1.18 Schematic diagram of the constant energy contours in the conduction band for
various substrate orientations. Longitudinal and transverse effective masses are mentioned for
each band……………………………………………..……………………………………….16
Fig. 1.19 Electron mobility enhancement as a function of strain under different stress
conditions, channel directions and substrate orientations……………………………...……...17
Fig. 1.20 (a) Calculated Id-Vg characteristics of bulk Si and bulk Ge NMOSFETs without
stress and bulk Ge nMOSFETs with uniaxial stress. (b) Calculated injection velocity vs.
inversion charge density………………………………………………………...…………….17
Fig. 1.21 Performance comparisons for nanoscale MOSFETs with different channel
materials……………………………………………………………………………………….18
Fig. 1.22 (a) XSTEM of Si/Ge/Si hetero-epitaxial layers (b) Effective electron mobility vs.
electric field of nFETs with decreasing Si cap layer thickness……………………………….18
ix
Fig. 1.23 BTBT reduction by quantum confinement in an HFET. Confinement leads to
effective widening of Ge band gap, which leads to smaller overlap integral and BTBT
reduction…………………………………………………………………………………..…..19
Fig. 1.24 (a) Strained SiGe on SOI device (b) Strained Si / strained Ge double hetero-structure
device grown on SiGe…………………………………………...………………………….....20
Fig. 1.25 (a) Unstrained Ge and Si PMOSFETs (b) Uniaxially strained Ge and Si showing
hole mobility enhancement………………………………………...………………………….20
Fig. 2.1 Vertical cross-section schematic of the n-type vertical surround gate
MOSFET……………………………………………………………………………………....27
Fig. 2.2 Growth rate data for thermal oxidation and the associated dependence on substrate
orientation ………………………………………………………………...…………………..28
Fig. 2.3 Effect of substrate orientation on Dit for thermal oxidation and radical oxidation of
silicon………………………………………………………………………...………………..29
Fig. 2.4 Schematic of the slot plane antenna (SPA) radical oxidation
equipment.……………………………………………..……………………………………...30
Fig. 2.5 (Left) Proposed mechanism of radical oxidation using O* species (Right) Surface
roughness of SiO2/Si interface vs. substrate orientation for radical and thermal
oxidation……………………………………………………………………………………....31
Fig. 2.6 Si 2p3/2 photoelectron spectra measured for silicon dioxide films (thermal oxide and
three flavors of plasma oxide). The thickness of SiO2 was fixed to 1.4nm. (Left) Si (100)
surface; (Right) Si (111) surface…………………………………………………………..…..31
Fig. 2.7 Parabolic rate constant of oxidation as a function of substrate temperature by radical
oxidation (o) with reference thermal oxidation ( )………………………………...…………32
Fig. 2.8 Growth rate data for radical oxidation on different substrate orientations of
silicon……………………………………………………………………………………….…32
Fig. 2.9 TEM images of Si (100) surfaces after removal of the (a) O* and (b) dry oxides
(nominal oxide thickness of 10nm). Atomically flat interface is achieved by radical
oxidation……………………………………………………………………………….……...33
Fig. 2.10 Vertical XSTEM images of Si pillar. Conformal oxidation of the silicon pillar is
observed for (b) SPA radical oxidation as compared to (a) thermal oxidation……………….35
Fig. 2.11 Vertical XSTEM images of silicon pillar edge. Radical oxidation provides conformal
silicon edge coverage…………………………………………...…………..............................35
x
Fig. 2.12 Vertical XSTEM images of silicon pillar edge. Thermal oxidation (1100C, 2min)
does not provide conformal silicon edge coverage....................................................................36
Fig. 2.13 Idrain-Vgate (Id-Vg) characteristics of the vertical surround gate MOSFET oxidized
using thermal oxidation or radical oxidation…………...……………………………………..36
Fig. 2.14 Output characteristics (Id-Vd) of vertical surround gate MOSFET comparing radical
oxidation and thermal oxidation…………..……………………………………...…………...37
Fig. 2.15 Gate leakage characteristics (Igate-Vgate) of vertical surround gate MOSFET
comparing radical oxidation and thermal oxidation…………………………………….….…37
Fig. 2.16 Gate dielectric breakdown characteristics of vertical surround gate MOSFET
comparing radical oxidation and thermal oxidation………….……………….….…………...38
Fig. 3.1 Schematic illustration showing possible mechanisms of formation and evolution of
GeO2 on Ge substrate using O* species…………………………………………………….…42
Fig. 3.2 Ge 3d core level spectra of XPS for thermal and radical oxidation…………………43
Fig. 3.3 Optical emission spectrum for SPA radical oxidation……………………………….44
Fig. 3.4 Growth rate of GeO2 and its dependence on substrate orientation…………………...44
Fig. 3.5 Band gap and band offsets reconstruction using EELS, SRPES………………...…...45
Fig. 3.6 Dit measurement using conductance method for the gate stack shown on the right…46
Fig. 3.7 Thermal stability of the GeO2/Ge dielectric stack as compared to Al2O3/GeO2/Ge
dielectric stack………………………………………………………………………………...46
Fig. 3.8 High frequency (1MHz) and Low frequency (QSCV) for Ge MOS…………………48
Fig. 3.9 Mid-gap Dit for the Ge MOS structures…………………………………………...…48
Fig. 3.10 Gate leakage vs. EOT for the Ge MOS……………………………………………..49
Fig. 3.11 Drive current and Trans-conductance enhancements for MOSFETs with GeO2
IL………………………………………………………………………………………………50
Fig. 3.12 Electron mobility enhancement for high-k/Ge gate stacks with GeO2 IL and substrate
orientation……………………………………………………………………………………..50
Fig. 4.1 Schematic of the on-resistance for the MOSFET consisting of Rch and Rseries = 2R…54
Fig. 4.2 Schematic representation of various components of S/D series resistance…………..55
Fig. 4.3 Series resistance vs. physical gate length as channel length scaling proceeds……….55
Fig. 4.4 Threshold voltage reduction as the device dimension is scaled……………………...56
Fig. 4.5 Techniques to reduce the short channel effects (SCE)……………………………….57
xi
Fig. 4.6 Requirement of sub-10nm junction depth for scaled technologies…………………..57
Fig. 4.7 Energy contamination in decel mode ion implanter. The implanted profile is deeper
than desired…………...……………………………………………………………………….58
Fig. 4.8 Gas cluster ion beam (GCIB) infusion doping…………………………………...…..59
Fig. 4.9 Schematic of plasma doping chamber……………………………………………......60
Fig. 4.10 Temperature-time ranges of various conventional and advanced annealing
techniques..................................................................................................................................60
Fig. 4.11 Top view of a M4PP………………………………………………………………...61
Fig. 4.12 SIMS profiles for p-type and n-type dopants in Ge………………………………...63
Fig. 4.13 P-type and n-type dopant activation using ion implantation and rapid thermal
annealing (RTA)……………………………………………………………………………....63
Fig. 4.14 Acceptor states causing donor concentration compensation in n-type Ge………….64
Fig. 4.15 Contact resistance vs. active n-type dopant concentration in Ge………………...…65
Fig. 4.16 Laser annealing setup……………………………………………………………….66
Fig. 4.17 Die by Die laser annealing performed on a wafer………………………………….67
Fig. 4.18 Laser annealing scenario…………………………………………………………....68
Fig. 4.19 Schematic illustrating the velocity of the liquid-solid interface…………………….69
Fig. 4.20 SIMS profiles for Plasma doped (a) P (b) As and (c) Ion Implanted Sb…………....69
Fig. 4.21 Sheet resistance of laser annealed junctions. Higher fluence provides lower sheet
resistance……………………………………………………………………………………....70
Fig. 4.22 Sheet Resistance as a function of laser fluence……………………………………..70
Fig. 4.23 TEM micrographs for (A) as-implanted samples (B) laser annealed with 0.2 J/cm2
(C) laser annealed with 0.4 J/cm2……………………………………………………………..71
Fig. 4.24 I-V Characteristics of n+/p Ge junction diode, measured from -0.5V to 1V……….71
Fig. 4.25 Raman analysis for as-implanted Ge and laser annealed Ge………………………..72
Fig. 4.26 Spreading resistance profiling (SRP) for estimating active dopant concentration….73
Fig. 4.27 n+/p diode I-V characteristic for the laser annealed diode………………………….73
Fig. 4.28 Measurement temperature dependent n+/p diode I-V characteristics……………….74
Fig. 4.29 Temperature variation of Leakage current density for n+/p diodes biased at -0.5
V………………………………………………………………………………………………74
Fig. 4.30 Linear transfer length method (TLM) structure for computation of contact
resistivity…………………………………………………………………………………...….75
xii
xiii
Fig. 4.31 Circular transfer length method (cTLM) structure for computation of contact
resistivity…………………………………………………………………………………...….75
Fig. 4.32 Contact resistance measurement results using TLM structure……………………...76
Fig. 4.33 Reflectance properties of various metals. Al provides high reflectance across
different wavelengths………………………………………………………………………….76
Fig. 4.34 Al gate pad with a 5u wide Al line running over the gate dielectric on a MOSFET
structure. The source (S) and drain (D) are labeled……………………………………...……77
Fig. 4.35 Design scheme of integration of laser annealing with MOSFET process…………..77
Fig. 4.36 MOSFET I-V characteristics with an optimized laser fluence of 0.3 J-cm-2…….…78
Fig. 4.37 MOSFET I-V characteristics with an optimized laser fluence of 0.5 J-cm-2……….78
Fig. 4.38 Performance projections for ITRS HP 22nm technology node……………………..79
CHAPTER 1: Introduction
1.1 Scaling roadmap
The planar silicon Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been
the workhorse of the semiconductor industry for the past four decades. It has enabled logic
operations as a voltage controlled switch and as an amplifier in analog applications. The
fundamental device architecture of the MOSFET has stayed the same. The number of transistors
per die have been increasing by a factor of 2-3 in accordance with Moore’s Law (Fig. 1.1)
resulting in faster chips [1].
Fig. 1.1 Moore’s law of scaling
This increased transistor density is achieved through aggressive transistor size scaling, which
is discussed in Fig. 1.2. The transistor size has scaled from “micro” dimension to “nano”
dimension. This entails new scientific technologies.
In the past, as this scaling reached the sub-100nm gate pitch, more non-silicon materials were
introduced to this silicon dominated technology (Fig. 1.3). At 90nm ITRS technology node,
SiGe was introduced to achieve uniaxial strain in the channel. This was followed by the
integration of metal gate and high-k dielectrics at 45nm node. The 32nm technology node has
higher process induced stress, realized using contacts and shallow trench isolation (STI)
structure adjacent to transistors. At present, the 22nm technology node is nearing production
with the physical gate length approaching 10nm. Beyond 22nm, more changes in materials and
transistor architecture are expected.
1
Fig. 1.2 Device feature size scaling
Likely changes in the future include multi-gate device. This comprises of various possible
architectures for the multi-gate device – FINFET, surround gate etc. The multi-gate MOSFET is
desirable for providing better gate control and reducing the problem of DIBL. The other likely
change is the MOSFET with a high mobility channel material such as Ge, III-V or carbon. This
is also shown in Fig. 1.3.
ProductionDevelopment
Fig. 1.3 Sub 100nm CMOS technology scaling (Source: Intel corp)
2
1.2 Challenges in scaling of silicon MOSFETs
rrent carriers are either electrons in the case of n-
istor built
n bulk Si substrates, identifying the various problems faced in scaling the transistor.
In a MOSFET, the gate is used as a control terminal to switch the conduction current channel
between the source and drain terminals. The cu
MOSFET or holes in the case of p-MOSFET.
In a traditional realization of this MOSFET architecture, the gate electrode was made of
heavily doped poly-crystalline silicon. The doping of this poly layer was n-type for n-MOSFET
and p-type for p-MOSFET. This gate electrode is separated from bulk silicon by a thin dielectric
layer. The channel region under the gate is moderately doped. The source and drain regions,
upon which the other electrode contacts are formed, are heavily doped to form n-p (or p-n)
junctions to the oppositely doped substrate. The simplest scaling approach involves reducing all
dimensions and supply voltage by the same factor in an attempt to keep the electric fields in the
scaled MOSFET same as before (constant-field scaling). However the actual scaling situation is
based on slightly modified approach where the geometry and voltages are reduced by different
factors (generalized scaling). Fig. 1.4 shows a schematic of conventional silicon trans
o
Fig. 1.4 Physical limits in scaling bulk silicon MOSFETs
In long channel transistors, the vertical electric field in the channel is much larger than the
lateral channel electric field. Using the gradual channel approximation (GCA), the transistor
operation can be portioned into two independent problems – gate controlled charge formation in
3
the channel and drain controlled charge transport. The threshold voltage is dependent only on
the gate voltage and is independent of drain voltage. When the gate voltage is applied, it lowers
the potential barrier near the source and allows electrons to flow from source to drain. The sub-
threshold swing is a measure of how sharply the drain current increases as a function of gate
the channel. The 2-D effects manifest in various ways
in voltage (drain induced barrier lowering - DIBL)
pressed by using the
voltage during switching from 0 to VTH.
The GCA is just a simplification of the complicated 2-D electrostatics in the MOSFET
channel. While the simplification holds in the long channel devices, as the gate length is
reduced, the drain influence becomes much stronger. As a result it becomes harder for gate to
control the source barrier and turn-off
called the short channel effects (SCE),
1. Reduction in threshold voltage with shrinking gate length (VTH roll-off)
2. VTH reduction with increasing dra
3. Degraded sub-threshold swing.
All these lead to increase in the off-state leakage. The SCE have to be sup
following methods, however there is trade-offs involved in each approach.
1. EOT reduction – In order to suppress the short channel effects, it is desirable to increase
the electrostatic control of the gate over the channel. This is achieved by using thinner
gate oxides at the cost of enhanced quantum mechanical tunneling or gate leakage. In
the direct tunneling regime, encountered for oxides thinner than 3nm, the gate leakage
current increases by > 3X for every 1A of thickness reduction [2]. The thinning of EOT
was achieved using nitridation of thin SiO2 and finally by high-k dielectrics. However,
introduction of high-k was very challenging with the associated defect control – which
was responsible for reduction of mobility and degradation of reliability. Some of the
challenges which were encountered with high-k before their successful incorporation in
the technology node are discussed in Fig. 1.5.
Fig. 1.5 Possible sources of reduced mobility in high-k MOS gate stacks [3]
4
2. Enhancement of channel doping – This helps in terminating the electric field lines
which originate from the drain and propagate towards the source. The channel doping is
tailored to have a complicated vertical and lateral doping profile so as to minimize the
effect of gate length variation on the SCE. The trade-off for this enhanced channel
doping is reduction in channel carrier mobility due to increased scattering from the
ionized dopant atoms. Also, the sub-threshold slope gets worse due to higher depletion
capacitance, which leaves a reduced part of gate voltage for surface potential variation.
High concentrated doping near the source-drain extension region increases the band to
band tunneling component of static power leakage. Finally as the device geometry and
volume shrinks, random placement of discrete dopants becomes an issue.
3. Reduction of junction depth – This is especially useful near the gate edge which is
labeled as source/drain (S/D) extension. This reduces the drain coupling to the source
barrier. However as the S/D region gets shallow, their doping must be increased so as to
keep the sheet resistance constant. Solid solubility of dopants puts an upper limit on the
doping density. Hence further reduction in junction depth causes an increase in the
series resistance encountered in accessing the channel. Also, forming an ultra-shallow
junction with abrupt doping profile and high dopant activation is a technological
pplement or even replace the conventional bulk MOSFET
future sub-22nm technology node.
.3 Device structures for better electrostatic control
challenge.
As a result of all these and many other problems, it is becoming clear that new materials
and/or structures will be needed to su
in
1
1.3.1 SOI MOSFETs- These come in two flavors – Partially depleted and fully depleted.
Partially depleted (PD) SOI MOSFET [4] is shown schematically in Fig. 1.6, where a layer of
insulating SiO2 separates the upper device containing film and rest of the bulk Si substrate. The
upper silicon film is ~ 100nm thick and is doped in the same way as a corresponding bulk
transistor having a similar geometry. In the off-state condition, with zero voltage applied on the
gate electrode, the maximum depletion width under the gate oxide is less than the Si film
thickness. The lower part of the PD layer has a quasi neutral region in the body, which is
typically left un-contacted. The potential of this floating Si region is determined dynamically by
5
capacitive coupling to the various electrodes and in steady state, by a balance of forward and
reverse bias currents to the source and drain junctions. This leads to a variety of floating body
effects such as
Fig. 1.6 Partially depleted (PD) SOI MOSFET
PD-SOI looks similar as bulk device and hence is not sufficient to
PD-SOI/bulk devices. In FD-SOI, the doping requirements of the channel region are relaxed.
the parasitic bipolar kink effect [5] as well as history dependent threshold voltage [6]. The main
advantage of PD-SOI device is somewhat higher speed and lower leakage due to reduced source
and drain junction capacitances. The floating body effects can be mitigated using ion-
implantation [7] and using body contacts [8] However, from a static leakage and electrostatic
scalability perspective, the
extend the device scaling.
Fully depleted (FD) SOI MOSFET is shown in Fig. 1.7. If the top Si film thickness of the PD
SOI is reduced, eventually the entire Si body beneath the gate is depleted at zero applied gate
bias. The film thickness below which the full depletion condition occurs depends inversely on
the square root of body doping. By elimination of the floating body, the kink effect and history
dependent behavior is suppressed. The SCE control in FD-SOI is potentially superior to that of
Fig. 1.7 Fully-depleted (FD) SOI MOSFET
6
This improves carrier transport since the mobility is enhanced, both due to lower ionized
impurity scattering as well as lower vertical electric field for the same channel carrier
concentration. Also, if the buried oxide is thick as compared to Si body thickness and gate oxide
thickness, the long channel sub-threshold swing approaches the ideal value of 60 mV/decade at
RT. However, a thick buried oxide can potentially degrade the short channel device
performance. This is due to the effect of fringing electric field lines originating from the drain,
oing through the buried oxide and lowering the barrier for the source to channel current. This
carrier transport due to increased
mobility resulting from lesser ionized impurity scattering and lower vertical electric field.
Undoped body is more immune to discrete dopant effects.
g
is similar to DIBL, instead occurring through the buried oxide.
1.3.2 Multi-gate (Double-gate, FINFET, Surround gate) MOSFETs
Multi-gate FETs in the FD operation allow much better control of SCE than single gate FD
SOI FETs. This is due to tighter capacitive coupling of the gates to the device channel region
from more than one direction. The gate control grows stronger as we go from double-gate (DG)
to tri-gate to surround gate by virtue of increased coupling. In the case of a DG FET (Fig 1.8)
[9] this can be thought of as an enhanced version of FD-SOI, has a very thin buried oxide, as
thick as the gate oxide. Only now the back substrate is heavily doped and connected to the top
gate. Both the gates drive the substrate together. The SCE control is very good by virtue of thin
fully depleted body and gate shielding the drain electric field lines from both sides. Due to the
action of two gates, the device can now be scaled to shorter gate lengths for the same body and
dielectric thickness. Since the two gates and the ultra-thin body are sufficient to suppress the
SCE, the body is left undoped, which improves channel
Fig. 1.8 Double gate MOSFET (G1 and G2 are the double gates, FG is front gate, BG is back
gate)
7
In tri-gate [10] FINFET [11] (Fig. 1.9) or surround-gate [12] MOS transistors, crystal
orientation effects play an important role, as the carrier transport occurs along various
orientations.
Fig. 1.9 Schematic of FINFET
1.4 High mobility channel materials
The MOSFET performance and further improvement in terms of material can be explained in
terms of the inverter delay,
ICV
=τ (1.1)
In this equation,
C = load capacitance of the inverter consisting of intrinsic gate capacitance of the next stage of
the inverter and other parasitic capacitance
V = supply voltage, I = drive current
This equation can be re-written in terms of the MOSFET saturation current and physical
dimensions,
( ) effthdd
ddg
VV
VL
μτ 2
2
−= (1.2)
In this equation,
μeff = effective mobility, Vth = threshold voltage, Lg = gate length, Vdd – Vth = gate over-drive of
MOSFET. There are various techniques applied for effective mobility enhancement and hence
inverter delay reduction. These techniques can be classified into two parts (i) Strain
enhancement and (ii) High mobility substrates. Strain application (SiGe S/D etc.) on existing
8
silicon technology is providing incremental reduction of inverter delay in further technologies,
however high mobility substrates e.g C, Ge, III-V are prospective candidates for future devices.
Higher (low field mobility) channel materials are useful when the device geometry is small
enough so that drift velocity saturation can have only a minor effect on speed performance.
Table 1.1 summarizes the material properties of bulk semiconductors. There is a clear trade-
off between dominant carrier mobility and band gap. Narrow band gap materials suffer from
junction leakage and band to band tunneling. Ge is the most promising material for PMOSFET
with high hole mobility, however its band gap is narrow. Other III-V and Si materials have
lower hole mobility. Ge has advantages over other materials – (a) compatibility to silicon VLSI
technology (b) low temperature process due to lower melting point (~940ºC) as compared to
silicon (~1400ºC) enables reduced thermal budget (c) current usage of Ge in the technology
node in terms of pre-amorphization implants and embedded SiGe source/drain for compressive
strain in the PMOSFET channel. For NMOSFET applications, Ge provides higher bulk mobility
than Si, but III-V materials have significantly higher bulk carrier mobility.
The low thermal budget processing is especially attractive for high-k/metal gate technology
because low thermal budget can maintain the integrity of the gate stack and three dimensional
(3D) integrated circuit technologies, which builds transistors on the interconnect layer without
deteriorating underlying device characteristics.
Table 1.1 Material properties of bulk semiconductors
The first semiconductor device was made using germanium [13] Despite that, Si has been the
mostly prevalent in LSI/VLSI technologies because Si has a chemically and electrically stable
oxide SiO2 while Ge oxides are water soluble and desorb at low temperatures [14] Ge attracted
attention recently when high-k/metal gate technologies were under research and development
[15] High-k/ metal gate is one of the key technology enabler for sub-45nm ITRS technology
node. It suppresses short channel effect and improves device performance by decreasing
9
equivalent-oxide-thickness (EOT), without increasing gate leakage. The initial motivation of Ge
was based on thermodynamic stability of metal-Ge-O system as compared to metal-Si-O system.
Ge is desirable channel material because it can avoid the interfacial layer and make EOT
scalable with high-k dielectrics [16] Also, Ge has smaller band gap than Si, band offset between
high-k dielectric layer and Ge becomes large, which leads to lower gate leakage than Si [17]
Therefore, high-k/Ge MOS system is more scalable in terms of the EOT and the gate leakage
current than Si. Si process typically requires high thermal budget especially for source/drain
dopant activation. This high thermal budget degrades the chemical and electrical properties of
high-k/metal gate. Therefore, Ge is more suitable material for high-k/ metal gate technology
because Ge allows low thermal budge process due to its lower melting point.
1.4.1 Surface passivation of germanium
In order to improve interface properties of high-k/Ge MOS gate stack, surface passivation has
been actively studied. Since Ge native oxide is chemically/electrically unstable, alternative
surface passivation on Ge without increasing EOT has been extensively researched. Several
types of surface passivation methods were proposed, such as GeON [18], GeN [19], and Si [20].
Although Ge oxide is unstable, it can be stabilized by incorporating nitrogen as GeON or GeN.
Nitrogen incorporation also contributes to the increase of the dielectric permittivity of interface
gate dielectric. Thermal nitridation [21] and plasma nitridation [22] were employed for GeON
and GeN formation and excellent MOS properties were demonstrated with high-k dielectric
and metal gate. The drawback of nitrogen incorporation is that nitrogen generally causes oxide
defects such as dangling bonds and fixed charges which degrade carrier mobility similarly to
SiON and SiN in Si [23] (Fig. 1.10).
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
0.0
0.5
1.0
1.5
2.0
RTN at 600 ºC
(EOT = 1.9 nm)
FGA300 Pt/HfO2/GeOxNy/Ge
Gat
e C
apac
itanc
e (μ
F/cm
2 )
Gate Voltage (V)
10 kHz 100 kHz 800 kHz
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
0.0
0.5
1.0
1.5
2.0
RTN at 700 ºC
(EOT = 2.0 nm)FGA300 Pt/HfO2/GeOxNy/Ge
Gat
e C
apac
itanc
e (μ
F/cm
2 )
Gate Voltage (V)
10 kHz 100 kHz 800 kHz
Fig. 1.10. Higher Rapid thermal nitridation temperature degrades the interfacial quality [21]
10
Another instance of low Dit passivation has been demonstrated with GeO2 [24]. The GeO2 was
grown by inductively coupled plasma (ICP) oxidation (Fig. 1.11) followed by SiN capping
shows very low interface state density on the order of 1010cm-2eV-1, which is the lowest value
ever reported. Thermally grown GeO2 [25], ozone oxidized GeO2 [26] followed by high-k
dielectric have also been investigated and show Dit on the order of 1011cm-2eV-1.
Epitaxial Si layer provides very clean interface between Si and Ge [27]. This Si passivation
layer is oxidized and SiO2 is formed with stable interface between SiO2 and Si. The possible
concerns about Si passivation are (1) inefficient EOT scaling by finite thickness of Si layer and
(2) valence band offset between silicon and germanium, only works for hole confinement.
Fig. 1.11 CV characteristics of GeO2 using plasma oxidation [24]
Therefore, Si passivation is only effective for Ge PMOS. The trade-off between EOT scaling
and mobility were recently investigated [28] Nevertheless, the current state-of-the-art Ge PFETs
have been fabricated and the minimum gate length of 65nm has been achieved.
Although hydrogen passivation of Ge is thermodynamically weaker than that of Si, it has been
reported that forming gas (dilute hydrogen gas) anneal can improve the interface properties by
hydrogen termination of oxide defects [29]. Furthermore, good electrical characteristics by
fluorine were demonstrated [30]. One potential issue on fluorine incorporation is HF formation
as a reaction in byproduct which etches gate oxide and degrades the reliability of gate stack [31].
1.4.2 Source/Drain junctions in Ge MOSFETs
Both n-type and p-type dopants in Ge have been investigated [32]. It has been understood that
p-type dopant has higher solid solubility and high dopant activation rate in typical rapid thermal
anneal process as shown in Fig. 1.12. P-type dopant diffusion is slow in Ge (Fig. 1.13),
11
therefore shallow junction formation is relatively easier with P-type dopants rather than N-type
dopants. On the other hand, N type dopant has lower solid solubility and lower activation rate in
typical rapid thermal anneal process. In addition, n-type dopant diffusion is fast in Ge and it is
quite challenging to achieve shallow junctions for NMOSFET. This is discussed in more detail
in chapter 4 of this thesis where we discuss ultra shallow junctions with high dopant activation
using laser annealing for NMOSFET.
400 500 600 700 800 900 10001018
1019
1020
1021
P
Sb
AsGa
Solid
Sol
ubili
ty (a
tom
/cm
3 )
Temperature (ºC)
Fig. 1.12. Solid solubility of various dopants in Ge [33]
This N-type dopant characteristic is not only problematic for S/D in NMOS but also for channel
implant in PMOS. Especially, steep profile of halo pocket doping is required to suppress short
channel effect.
0 100 200 300 4001015
1016
1017
1018
1019
1020
1021
1022
B (p -type)
700ºC, 1 sec 700ºC, 5 sec 700ºC, 10 sec
650ºC, 10 sec 650ºC, 60 sec 675ºC, 5 sec
Elec
tric
al C
once
ntra
tion
(cm
-3)
Depth (nm)
Fig. 1.13. Low dopant diffusivity of p-type dopants in Ge [34]
12
However, since N-type dopants diffuse fast, halo doping broadens and unintentionally
increases channel doping concentration, which may cause severe mobility degradation in Ge
PMOS [35]. To achieve shallow/highly activated junction, more elaborate source/drain
activation technique may be needed. In addition the poor n-type dopant activation and diffusion
leads to reduction of active surface n-type doping, causing enhancement of contact resistance.
These issues are addressed in chapter 4 of this thesis.
0 100 200 300 400 500 6001015
1016
1017
1018
1019
1020
Sb
AsAs
PP
Sb
650ºC60 sec675ºC
5 sec
Elec
tric
al C
once
ntra
tion
(cm
-3)
Depth (nm)
Fig. 1.14. High dopant diffusivity and poor dopant activation of n-type dopants in Ge [36]
1.4. 3 Germanium substrates
Bulk Ge wafer is very expensive and fragile to handle. In order to realize Ge CMOS fully
compatible to Si LSI technology, Ge active layer has to be made on Si substrate. Because of
large lattice mismatch, thick epitaxially pseudomorphic Ge layer growth is not possible because
misfit/threading dislocations (Fig. 1.15) are formed due to large strain energy at the interface,
except for very thin Ge layer growth below critical thickness [37], which is used for making Si-
Ge-Si hetero-structures [38].
13
Fig. 1.15. Epitaxial growth of Ge on top of Si is not possible due to lattice mismatch [39]
One possible solution, Multiple Hydrogen Anneal Hetero-epitaxy (MHAH) utilizes a
combination of low/high temperature growth combined with hydrogen annealing. The first low
temperature process enables smooth Ge layer growth with small surface roughness at slow
growth rate. The next high temperature growth enables thicker Ge layer on the underlying seed
Ge layer. After each deposition cycle, hydrogen anneal is performed to move out the threading
dislocation and improve surface roughness. MHAH successfully provides very low threading
dislocation density and small surface roughness (less than 1nm RMS) for about 1 micrometer
Ge layer thickness (Fig. 1.16) [40]. The quality of epitaxial Ge layer can be further improved by
applying selective epitaxial growth [41]. This technique can be easily realized in the technology
node as STI processes are widely used in manufacturing of silicon MOSFETs and isolation.
100 nm
Defect Region
Si
Crystalline -Ge
Fig. 1.16. Multiple hydrogen anneal heteroepitaxy (MHAH) of Ge on Si [40]
Short Channel Effects (SCE) is even more severe in Ge MOSFET as compared to silicon,
because Ge has a higher dielectric constant. Therefore, ultrathin body GeOI structure or multi-
gate structures are required to obtain better electrostatics for super scaled technologies. Viable
14
methods to produce GeOI substrate are (1) wafer bonding and etch-back technique [42] – this is
similar to SOI fabrication method and (2) Ge condensation technique in SiGe layer [43] - this
technique starts from SiGe on insulator (SGOI) substrate and utilizes selective oxidation of Si in
SiGe layer where Si is selectively oxidized by thermal oxidation and Ge concentration in SiGe
layer increases. Finally almost 100% Ge layer is formed on substrate oxide. By utilizing this
technique, almost 10x higher hole mobility has been achieved, which is comparable with SOI
NMOSFET electron mobility [44].
Another possible way to fabricate GeOI structure is to utilize liquid phase epitaxy or rapid
melt growth [45] Amorphous Ge layer is grown on an insulator with seed pattern. Then Ge film
is etched in the form of narrow patterns and then melted by rapid thermal anneal. The liquid
phase epitaxy takes place from the patterned seed layer during cooling process. This technique
is specifically applied to Fin FET [46] and gate-all-around (GAA) FET (Fig. 1.17) [47].
GeO2 + Al2O3
Fig. 1.17. Gate-all-around (GAA) GeOI MOSFET structures using Rapid Melt Growth of Ge
[47]
The excellent device characteristics were demonstrated with Fin FET and gate-all-around FET.
By reducing thermal budget in the melt process using laser annealing of a-Ge, this technique
can be applied to 3DIC integration [48].
15
1.4.4 Mobility enhancement due to strain and substrate/channel orientation of Ge MOSFETs.
Drive current enhancement has also been achieved using the effects of strain and
substrate/channel orientation. Various research groups have investigated substrate orientation
and strain effect for Ge NMOS and PMOS.
For the unstrained Ge NMOS channel, (111) Ge substrate can provide the highest mobility
among the three orientations, mainly due to its largest quantization mass and smallest
conductivity mass in L valley. The conduction valley configuration is shown in Fig. 1.18. In
addition to eight half ellipsoidal L valleys, six ellipsoidal Δ valleys and one conduction sphere
at Γ point are also taken into consideration due to their proximity to L valleys in terms of energy.
Note that the mass anisotropy is much stronger for L valleys of Ge (~20) than Δ valleys of Si
(~5). This high mass anisotropy for L valley of Ge, results in unstrained mobility to be
significantly dependent on substrate orientation, Ge (111) > Ge (110) [-110] > Ge (001) > Ge
(110) [00-1]. [49]
Fig. 1.18. Schematic diagram of the constant energy contours in the conduction band for various
substrate orientations. Longitudinal and transverse effective masses are mentioned for each
band [49].
In addition to substrate orientation, electron mobility enhancement can be achieved using
uniaxial and biaxial strain [49]. Fig. 1.19 (a) shows the mobility enhancement for electrons in a
Ge NMOSFET under uniaxial strain. The Ge (111) and Si (100) mobility values are shown for
comparison. Fig. 1.19 (b) shows mobility as a function of strain under different stress conditions,
channel directions and substrate orientations.
16
(a) (b)
Fig. 1.19 Electron mobility enhancement as a function of strain under different stress conditions,
channel directions and substrate orientations [49].
In another work focused on uniaxial strain for Ge (100) n-type MOSFET [50], two additive
stressors were considered in the study (i) longitudinal additive stressor of 0.5 GPa tensile SiN
stress liner and 1.5 GPa tensile SiGe (S/D) (ii) combination of longitudinal 1.5 GPa tensile SiGe
S/D and transverse 0.5 GPa compressive STI stressor. Under both stress applications, the
injected velocity was significantly enhanced over bulk Ge n-type FET as shown in Fig. 1.20 (b).
This results is a ~48% drive current gain under the stress as shown in Fig. 1.20 (a) at ITRS
22nm technology node specification.
1011 1012 10130.5
1.0
1.5
2.0
2.5
vF limit bulk Si bulk Ge 2GPa tens. 1.5GPa comp. 2GPa tens. + 1.5GPa comp.
Stress along <110> on (100) GeNinv=1x1013cm-2
Inje
ctio
n ve
loci
ty (c
m/s
)
Inversion charge density (cm-2)
vth limit
Additive velocity enhancement by combination
0.0 0.2 0.4 0.6 0.810-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
100
Idsat (lin) (A/μm
)
I dsat (l
og)(A
/μm
)
Gate voltage (V)
NFET Tox 0.5nm, Vdd 0.8V, Nsub 1x1018cm-3
(100)/<110> Si (100)/<110> Ge
22nm HP Idsat 2.2mA/μm
(100)/<110> Ge w/ 2GPa tensile P//J (100)/<110> Ge w/ 1.5GPa comp. P⊥J
0
1
2
3
4
5
6
Idsat additive +52%enhancement
(100)/<110> Ge w/ 2GPa tensile P//J + 1.5GPa compressive P⊥J
B
Fig. 1.20 (a) Calculated Id-Vg characteristics of bulk Si and bulk Ge NMOSFETs without stress
and bulk Ge nMOSFETs with uniaxial stress. (b) Calculated injection velocity vs. inversion
charge density [50].
17
Another work [51], compares the nanoscale ballistic MOSFETs on different high mobility
substrates. When the quantum confinement and DOS effects are taken into account, Si has the
largest inversion charge density and the inversion charge is reduced due to low DOS in other
high mobility materials. Due to lower transport effective mass, III-V materials have the highest
injection velocity. The value of inversion charge density and DOS in Ge is in between Si and
III-V materials. Combining inversion charge density and injection velocity, Ge shows the
highest ON current especially for super scaled body thickness. According to OFF current
simulation results, quantization helps Ge to reduce BTBT leakage and meet the off current
requirements.
Fig. 1.21 Performance comparisons for nanoscale MOSFETs with different channel materials
[51]
High electron mobility has been demonstrated in Si/Ge/Si hetero structured channel n-type
MOSFET with decreasing thickness of the top Si layer (Fig. 1.22), which is attributed to
increasing population of electrons in Ge, which certainly has higher mobility than silicon [52].
(a) (b)
Fig. 1.22 (a) XSTEM of Si/Ge/Si hetero-epitaxial layers (b) Effective electron mobility vs.
electric field of nFETs with decreasing Si cap layer thickness [52]
18
Higher mobility enhancement has been observed for hetero-structure (Si/Ge/Si) pMOSFETs
due to large hole band warping and sub-band energy splitting [53]. More than 4X higher
mobility has been achieved with strained Ge layer due to smaller effective mass and reduced
interband scattering. Another advantage of hetero-structure FET (H-FET) is the reduction of
band to band tunneling (BTBT). Ge is a narrow band gap material, which suffers BTBT at high
drain bias, especially in the off-state. The BTBT could be a dominant leakage in Ge rather than
sub-threshold leakage because, unless supply voltage is scaled, the BTBT is determined by a p-
n junction near the drain edge, where leakage is difficult to suppress due to high doping. The H-
FET consists of a silicon cap/Ge/Si hetero-structure, where Si act as a barrier layer and Ge acts
as a quantum well. This is due to the valence band discontinuity between Si and Ge. This
quantum confinement can effectively widen the Ge band gap and BTBT is reduced (Fig. 1.23).
Fig. 1.23 BTBT reduction by quantum confinement in an HFET. Confinement leads to effective
widening of Ge band gap, which leads to smaller overlap integral and BTBT reduction [54]
Strained ultra-thin SiGe MOSFETs with a high Ge fraction (80%) fabricated on SOI have
shown mobility enhancements of ~4X over bulk Si devices (Fig. 1.24 (a)) [54]. Ge PFETs
S
D
G BTBT
SSmmaallll TTuunnnneelliinngg RRaattee
ΨeΨh
Eg
SSttrroonngg QQuuaannttiizzaattiioonn LLaarrggee TTuunnnneelliinngg BBaarrrriieerr
Thin Body
Tbody
∆E
∆E Tbody
Thick Body G BTBT
S
D LLaarrggee TTuunnnneelliinngg RRaattee
ΨeΨh
Oxide
Eg
Eg Gate
19
fabricated with strained Si/strained Ge double hetero-structures grown on relaxed SiGe have
exhibited hole mobility enhancement as high as 10 times (Fig. 1.24 (b)) [53]
Fig. 1.24 (a) Strained SiGe on SOI device [54] (b) Strained Si / strained Ge double hetero-
structure device grown on SiGe [53].
The effect of channel orientation, strain and band structure on drive current and switching
delay was studied using Full-band Monte Carlo simulations on nanoscale Ge double gate PFETs
[54]. The highest unstrained hole mobility is for (110) surface with a [-1 1 0] channel
orientation. Maximum mobility enhancement (~2.2X) is observed for Ge (110) / [-1 1 -√2] and
(~3X) for Si (001) / [110]. These results are demonstrated in the polar plots of Fig 1.25
(a) (b)
Fig. 1.25 (a) Unstrained Ge and Si PMOSFETs (b) Uniaxially strained Ge and Si showing hole
mobility enhancement
20
1.5 Conclusion
Germanium is a promising performance booster for future technology nodes because of its
high electron/hole mobility, process compatibility to Si and low temperature process. There has
been substantial progress in Ge high-k/metal gate MOS gate stack. Superior performances have
been demonstrated in scaled Ge PFETs integrating high-k metal gate with strained Si/Ge/Si
hetero-structure MOSFETs. Issues on ultra shallow source/drain doping and activation need to
be addressed. Substrate preparation techniques on carrier Si wafer in terms of selective epi
growth and GeOI look promising. Future technology nodes would rely more on GAA structures
for improved SCE. However benchmark sub 22-nm Ge devices are still elusive due to various
process and device problems.
1.6 Layout of the thesis
This thesis focuses on two significant issues impacting future technologies of 3D devices and
high mobility Ge substrate. Chapter 2 and 3 discuss the surface passivation using radical
oxidation of vertical MOSFET and Ge n-MOSFETs respectively. Chapter 4 delves into ultra-
shallow junctions and high n-type dopant activation for Ge n-MOSFETs using laser annealing.
The last chapter presents conclusions and future work.
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CHAPTER 2 – Surface passivation of 3D vertical MOSFET using radical oxidation
2.1 Introduction:
In a sustained effort to increase drive current and better control over the short channel
effects, silicon MOSFETs in research have evolved from classical, planar single-gate devices
into three-dimensional devices with a multi-gate architecture (double-gate [1], triple-gate [2],
FINFET [3] or surround gate (SG) or gate all around (GAA) [4] devices). Out of these
structures, the structure that offers the best possible control of the channel region by the gate is
the SG-MOSFET. Both horizontal and Vertical (V) SG-MOSFET have been fabricated and
analyzed by many researchers [4, 5]. If the vertical silicon channel is defined by Reactive Ion
Etching (RIE), the channel is labeled as a silicon pillar [4]. In a VSG-MOSFET, channel for
the device is a vertical pillar of silicon, or other semiconducting material, surrounded by a gate
dielectric and a gate electrode material. The drain and source are the top and bottom of the
pillar, respectively. The height of the pillar is the channel length and the circumference of the
pillar is the width of the MOSFET. The vertical cross-section schematic for the n-type VSG
MOS is shown in Fig. 2.1
Fig. 2.1 Vertical cross-section schematic of the n-type vertical surround gate MOSFET
Despite the fabrication challenges and variability issues especially for the nanometer sized
vertical pillar (pillar height and/or pillar diameter), the VSG-MOS has the following
advantages
1. Higher packing density than planar MOSFETs due to smaller device foot print
2. Improved short channel characteristics due to higher gate control of the channel
region
27
3. Source and drain are self-aligned to the gate, reducing the overlap capacitance
4. Vertical integration of memory and logic is possible
5. Channel length (pillar height) is not limited by lithography. It can be defined by RIE
or epitaxy
6. Doping profile of the pillar (channel region) can be easily tailored using epitaxy or
implants.
With the thin pillar VSG-MOS, it is possible to attain steep sub-threshold slopes. This is due
to the ability to fully deplete the interior of the pillar. For thick pillars the sub-threshold slope
is less steep because the depletion regions of the two sides of the pillar do not interact and the
devices take on the characteristic of a planar transistor. As the pillar diameter decreases, the
depletion region of the pillar begin to overlap and the sub-threshold slope begins to increase.
The depletion capacitance decreases rapidly when the depletion regions overlap, this leads the
ratio of Cox / (Cdepl + Cox) to approach one and the s-factor, the reciprocal of sub-threshold
slope approaches the ideal 60 mV/dec. Just as the planar MOSFET, the channel length (height
of the pillar) also has an impact on the sub-threshold slope due to punch through at short
channel lengths. In this work, thick pillar devices (pillar diameter ~ 4 micrometer) and long
channel devices (pillar height ~ 1 micrometer) were fabricated.
2.2 Surface passivation of VSG-MOSFET
Irrespective of the particular multi-gate architecture, one of the significant challenges is the
passivation of the multiple oriented silicon channel faces.
Thermal Oxidation Growth Rate data (800C)
0.02.04.06.08.0
10.012.014.0
0 100 200 300 400Process Time (sec)
Oxi
de T
hick
ness
(nm
) (100)(110)(111)
Fig. 2.2 Growth rate data for thermal oxidation and the associated dependence on substrate
orientation
28
This challenge is exacerbated for small diameter silicon pillar devices [5] and the thinner
interface layers [6] required for super scaled MOS technologies. Conventional thermal
oxidation [7, 8] has been known to have substrate orientation dependent growth rates for SiO2
and a higher interface state/charge density for (111) and (110) substrate orientations. This has
been attributed to the larger silicon surface dangling bond density as compared to (100)
substrates. The oxide thickness vs. time plots for thermal oxidation is shown in Fig. 2.2.
Previous work [9] has shown the effect of substrate orientation towards Dit for thermal oxide
and substrate orientation independent Dit for radical (O*) oxidation (Fig. 2.3). This implies
that thermal oxidation may not be the preferred route for the passivation of vertical pillar or
FINFET devices both from a Dit and growth rate perspective. Alternative oxidation schemes
are required to overcome this challenge. However, thermal annealing/oxidation may be a
better option to remove RIE induced defects in silicon [10].
Fig. 2.3 Effect of substrate orientation on Dit for thermal oxidation and radical oxidation of
silicon [9]
One of the most promising alternatives to thermal oxidation is radical oxidation (RO), which
was performed using the slot plane antenna (SPA) plasma oxidation tool which utilizes Radial
Line Slot Antenna (RLSA™) plasma system developed by Tokyo Electron [9].
The equipment provides microwave (2.45 GHz) excited plasma with, high electron density
which is useful to realize high oxidation rates, low ion energy which suppresses ion
bombardment damage and low electron temperature (1 eV for Argon gas). The cross-sectional
schematic of the equipment is shown in Fig. 2.4 (a). The spatial uniformity of the high density
plasma is provided using the ceramic shower plate (Fig. 2.4 (b)). As the frequency of the
29
microwave is lower than the plasma frequency (Neq2/meεo), the microwave does not penetrate
into the plasma excitation region. The generated plasma then travels to the plasma diffusion
region where the substrate/wafer resides and oxidation / nitridation is carried out, depending
on the carrier gas (O2 / N2). The generation reactions for oxidation are as follows.
Ar (chamber gas) + e- Ar* + e-
Ar* + O2 (chamber gas) Ar + 2 O*
Ge (substrate) + O* GeO2 or Si (substrate) + O* SiO2
(a)
(b) Ceramic shower plate
Fig. 2.4 Schematic of the slot plane antenna (SPA) radical oxidation equipment
The high reactivity of radicals (O*) enables oxidation at low process temperatures as
compared to thermal oxidation, which is driven by thermally assisted reaction and diffusion of
molecular O2. Various studies [9, 11, 12, 13] of SPA-RO have confirmed the presence of high
density oxygen radicals (O*) which result in planarization, atomic flatness and reduced
surface roughness of SiO2/Si interface. It is proposed that, the highly reactive O* species can
repair the defects such as Si-Si bonds, silicon dangling bonds, strained Si-O bonds and oxidize
Si atoms at the SiO2/Si interface (Fig 2.5 - left). The density of O* oxides (2.28 g/cc) is
slightly larger than thermal oxides (2.27 g/cc) [11]. These densities are calculated using
grazing angle X-Ray Reflection (XRR) and are correlated to the defect repairing mechanism
enabled using radical oxidation. The substrate orientation independent characteristics of
radical oxidation can been explained in terms of reduced and similar surface roughness for
(100) and (111) SiO2/Si interface as compared to thermal oxidation (Fig 2.5 - right).
30
Radical Ox (O*)
Thermal Ox (O2)
Fig. 2.5 (Left) Proposed mechanism of radical oxidation using O* species [11] (Right)
Surface roughness of SiO2/Si interface vs. substrate orientation for radical and thermal
oxidation.
Photoelectron spectroscopic studies have also been performed for thermal oxides and
various plasma/radical oxides [14]. Fig. 2.6 shows Si 2p3/2 photoelectron spectra measured for
plasma oxidation and reference thermal oxidation on Si (100) and Si (111) surfaces. The sub-
stoichiometric peaks corresponding to Si1+, Si2+ and Si3+ are also shown. The de-convoluted
intensity ratio is very different for thermal oxide in the case of Si (100) and (111) surfaces. In
particular, Si1+ increased and Si2+ decreased at the same time for thermal oxide on Si(111). In
contrast, only slight changes were observed for plasma oxides. This demonstrates that
oxidation reaction with oxygen radicals is independent of the substrate orientation.
Fig. 2.6 Si 2p3/2 photoelectron spectra measured for silicon dioxide films (thermal oxide and
three flavors of plasma oxide). The thickness of SiO2 was fixed to 1.4nm. (Left) Si (100)
surface; (Right) Si (111) surface [14]
31
In addition to the photoemission studies, the kinetics of radical oxidation was also discussed in
[14] and compared to thermal oxidation [7].
Fig. 2.7 Parabolic rate constant of oxidation as a function of substrate temperature by radical
oxidation (o) with reference thermal oxidation () [14]
The parabolic rate constants (B values) of radical oxidation were evaluated at various
temperatures. Fig. 2.7 shows the arrhenius plots of B values. The activation energy of the B
value was estimated to be 0.08 eV in the case of radical oxides, which was significantly lower
than those of thermal oxides (Ea = 1.24 eV). The smaller activation energy in radical oxidation
facilitates Si-O bond formation and amorphization of the layer and thus realizes orientation
independent growth rate. The substrate orientation independent growth rate of SiO2 was
confirmed on bare silicon wafers using (100), (111) and (110) substrate orientations. The
oxide thickness data are shown in Fig. 2.8
0 200 400 6000
5
10
15
20
25
100 110 111
Oxi
de T
hick
ness
(nm
)
Oxidation Time (sec)
Fig. 2.8 Growth rate data for radical oxidation on different substrate orientations of silicon.
32
The TEM micrographs from [11] also demonstrate atomically flat SiO2/Si interface achieved
by radical oxidation as compared to thermal oxidation. This is shown in Fig. 2.9
(a) (b)
Fig. 2.9 TEM images of Si (100) surfaces after removal of the (a) O* and (b) dry thermal
oxides (nominal oxide thickness of 10nm). Atomically flat interface is achieved by radical
oxidation [11].
Fundamental understanding of the difference between thermal oxidation and radical
oxidation has been achieved by using grazing XRD experiments performed on films of both
oxides [15]. Thermal oxidation is reasonably well described by the Deal-Grove model [7],
which postulates that oxygen diffuses in molecular form without reacting with the SiO2
network. This picture is supported by,
1. 18O tagged oxygen diffusion experiments where no oxygen exchange was observed in
the bulk SiO2 between oxygen molecules and network oxygen atoms [16, 17]
2. Detection of interstitial oxygen molecules [18]
3. Linear dependence of diffusion on the partial pressure of gaseous O2 [7]
4. Similar diffusion properties of argon (an atom of approximately the same size as O2)
[19]
5. Molecular O2 in the spin-triplet state is energetically the most stable state in SiO2 [20,
21]
In the case of radical oxidation, the diffusing species is O* or atomic radical oxygen. O*
species react with SiO2 network near the surface and diffuse towards the interface with
changing bond connections. Since over coordinated and under coordinated atoms are
considered to promote switching of bond connections [22], the diffusion process of atomic
oxygen, as well as their incorporation into the SiO2 network, induces its modification. This
network modification property of O* species is useful in relieving the intense stress near the
33
Si-SiO2 interface or for amorphizing unfavorable micro-crystalline region in amorphous oxide
films [23].
In this research, we apply radical oxidation technique to a vertical surround gate MOSFET
and demonstrate superior electrical characteristics over thermal oxidation. The electrical
properties are explained in terms of drive current, sub-threshold slope, gate leakage and gate
dielectric breakdown voltage
2.3 Device Fabrication
The vertical surround gate MOSFET is fabricated using a top-down MOSFET process. Cl2 /
HBr Reactive Ion Etching (RIE) chemistry is used to etch and define one micron high silicon
pillars. A 900ºC, 60min sacrificial dry oxidation is used to remove the RIE etch damage. After
stripping the sacrificial oxidation, the gate oxidation was performed by the SPA radical
oxidation (2.45 GHz microwave supply, 4kW power, 1 Torr ambient pressure, Ar: O2 =
1200:400 sccm flow ratio, 400ºC resistive heated susceptor temperature). A reference dry
thermal oxidation was performed at 800ºC. Both oxidation techniques were calibrated to
provide a nominal thickness of 6nm on the (100) silicon surface. Oxide thickness was
confirmed using ellipsometry and TEM analysis. Doped poly-silicon at 580ºC was used for
the gate of the MOSFET. The source/drain (S/D) region of the MOSFET was defined by self-
alignment to the poly-silicon RIE etched gate. The source/drain doping is at 30keV, 5x1015
cm-2 implant dose with a subsequent anneal. A dielectric layer was deposited by chemical
vapor deposition. After patterning the contact holes, 1% Al/Si was sputtered and patterned as
the contact metal for the S/D with a subsequent forming gas anneal at 400ºC for 30min.
2.4 Results and discussion
The substrate orientation independent growth rate for SiO2 grown using SPA radical
oxidation provides conformal oxidation of the silicon pillar. This is demonstrated using a
vertical cross-section TEM of the silicon pillar edge as shown in Fig. 2.10. The dark region is
the vertical cross-section of the silicon pillar. The horizontal surface is (100) and the side wall
surface is (110). Uniform thickness of SiO2 is observed on the top and side-wall of the pillar
for the case of SPA-RO in Fig. 2.10 (b).
34
Fig. 2.10 Vertical XSTEM images of Si pillar. Conformal oxidation of the silicon pillar is
observed for (b) SPA radical oxidation as compared to (a) thermal oxidation
In case of radical oxidation, the thickness uniformity of the oxide was good even at the edge
where the substrate orientation changed drastically from [001] to [111] to [110]. Thermal
oxidation clearly shows the thickness variation in the top and side wall of the pillar in Fig.
2.10 (a) – thicker on the vertical side wall. The orientation of the vertical surface of a pillar
structure on a (100) silicon wafer varies periodically from <100> to <110> along its periphery.
Experimental results concerning the orientation dependence of the thermal oxidation rate
were reported in [24], where it was observed that (110) surface tends to oxidize faster than
(100) surface. Additional TEM pictures were obtained during the process optimization of
silicon pillar profile and oxidation conditions. Conformal silicon edge coverage with oxide is
seen for the case of radical oxidation (Fig. 2.11), where as thermal oxidation shows oxide
thinning at edges (Fig. 2.12)
a b
10 nm
[110]
[ 0 01] [111]
Fig. 2.11 Vertical XSTEM images of silicon pillar edge. Radical oxidation provides conformal
silicon edge coverage
35
Fig. 2.12 Vertical XSTEM images of silicon pillar edge. Thermal oxidation (1100C, 2min)
does not provide conformal silicon edge coverage
2.5 Electrical characterization of VSG-MOSFET
Id-Vg characteristics for the vertical surround gate FET are shown in Fig. 2.13 for thermal
and radical (SPA-RO) oxidation. Slight difference is observed in the sub-threshold behavior of
the MOSFET depending on the surface passivation scheme. The sub-threshold slopes are
steeper for SPA radical oxidation (RO) as compared to thermal oxidation.
-1 0 1 2 3
10-13
10-11
10-9
10-7
10-5
10-3
Thermal Oxidation SPA-RO
Dra
in C
urre
nt (A
)
Gate Voltage (V)
Vds = 100mV
Fig. 2.13 Idrain-Vgate (Id-Vg) characteristics of the vertical surround gate MOSFET oxidized
using thermal oxidation or radical oxidation (SPA-RO)
This can be explained [9] by the higher average Dit and oxide thickness across different
planar surfaces of silicon after thermal oxidation. In the case of thermal oxidation, the value of
36
Dit [9] spans from sub-1x1010 cm-2ev-1 to 1x1011 cm-2ev-1 as substrate orientation varies from
(100) to (111) after forming gas anneal. However for SPA-RO, the Dit is similar in value to
sub-1x1010 for various substrate orientations of the silicon substrate after forming gas anneal.
This has been correlated to atomically flat Si/SiO2 surfaces after SPA-RO verified using AFM
and TEM in [11], which were discussed before.
SPA-RO also provides higher drive current as compared to thermal oxidation. In the
subsequent plot (Fig. 2.14), the drain current is plotted as a function of drain voltage and gate
voltage. This higher drain current is due to a combination of conformal oxide thickness and
better SiO2/Si interface quality in the case of radical oxidation [9]
0 1 2 3 4 50.0
2.0m
4.0m
6.0m
8.0m Thermal Oxidation SPA-RO
Dra
in C
urre
nt (A
)
Drain Voltage (V)
Vg = 0.5V to 3V
Fig. 2.14 Output characteristics (Id-Vd) for VSG-MOSFET comparing radical oxidation (SPA-
RO) and thermal oxidation.
The non-conformal growth properties of SiO2 using thermal oxidation show up as higher
gate leakage for the VSG-FET and results are plotted in Fig. 2.15. As seen in the TEM
micrographs in Fig. 2.10, local thinning of thermal oxide is observed around the pillar edge.
This is considered to be the reason for higher gate leakage for thermal oxidation.
Corroborating the lower gate leakage for VSG-FET with SPA-RO, higher gate dielectric
breakdown voltage with tighter control as compared to thermal oxidation is observed, as
shown in Fig. 2.16. The higher breakdown voltage of SPA-RO is due to conformal oxide
thickness around the pillar geometry which provides uniform electric field and low gate
leakage current.
37
-3 0 3 6 9 1210-1410-1310-1210-1110-1010-910-810-710-610-5
Thermal Oxidation SPA-RO
Gat
e C
urre
nt (I
g) (A
)
Gate Voltage (V)
Fig. 2.15 Gate leakage characteristics (Igate-Vgate) for VSG-MOSFET comparing radical
oxidation (SPA-RO) and thermal oxidation.
3 6 9 120
20
40
60
80
100 Thermal Oxidation SPA-RO
Dis
trib
utio
n (%
)
Breakdown Voltage (V)
Tnom = 6nm
Fig. 2.16 Gate dielectric breakdown characteristics for VSG-MOSFET comparing radical
oxidation (SPA-RO) and thermal oxidation
This is in contrast to thermal oxide which shows variable oxide thickness around the pillar
geometry which means varying breakdown electric field and hence higher gate leakage
current. Regions with lower oxide thickness (especially around pillar corners) would have
higher electric field and enhanced gate dielectric breakdown. A further advantage with radical
oxide is the lower interface state density across all substrate orientations. The lower average
Dit [10] could also account for better breakdown characteristics.
38
2.6 Conclusion
SPA radical oxidation is compared to thermal oxidation for gate dielectric in vertical gate-
all-around (GAA) MOSFET devices. The substrate orientation independent properties of
growth rate and interface state density for SPA radical oxidation are shown to provide superior
electrical properties (higher drive current, steeper sub-threshold slopes, reduced gate leakage
and enhanced gate dielectric breakdown voltage) for vertical MOSFET. The effect is also
confirmed using XSTEM and growth rate data on silicon substrates with various orientations.
All these results are a consequence of superior passivation of 3D MOSFETs using SPA radical
oxidation (conformal oxide thickness and smooth SiO2/Si interface).
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[13] Y. Saito, K. Sekine, N. Ueda, M. Hirayama, S. Sugawa, and T. Ohmi, “Advantage of
Radical Oxidation for Improving Reliability of Ultra-thin gate oxide”, IEEE Elec. Dev.
Meeting, p. 176-177, 2000.
[14] K.Hirose, H. Nohira, K. Azuma, and T. Hattori, “Review: Photoelectron spectroscopy
studies of SiO2/Si interfaces”, Progress in surface science, 82, 1, 2007
[15] K. Tatsumura, T. Shimura, E. Mishima, K. Kawamura, D. Yamasaki, H. Yamamoto,
T. Watanabe, M. Umeno, and I. Ohdomari, ”Reactions and diffusion of atomic and
molecular oxygen in the SiO2 network”, Phys. Review B, 72, 045205, 2005
[16] M. A. Lamkin, F. L. Riley, and R. J. Fordham, “Oxygen mobility in silicon dioxide
and silicate glasses: a review”, J.Eur. Ceram. Soc. 10, 347, 1992
[17] H. C. Lu, T. Gustafsson, E. P. Gusev, and E. Garfunkel, Appl. Phys. Lett. 67, 1742,
1995
[18] L. Skuja and B. Güttler, Phys. Rev. Lett. 77, 2093, 1996
[19] W. G. Perkins and D. R. Begal, J. Chem. Phys. 54, 1683, 1971.
[20] W. Orellana, A. J. R. da Silva, and A. Fazzio, Phys. Rev. Lett. 87,155901, 2001
[21] A. Bongiorno and A. Pasquarello, Phys. Rev. Lett. 88, 125901, 2002
[22] A. Pasquarello, M. S. Hybertsen, and R. Car, “Interface structure between silicon and
its oxide by first principles molecular dynamics”, Nature, 396, 58, 1998.
[23] P.H. Fuoss, L.J. Norton, S. Brennan, and A.F. Colbrie, “X-Ray scattering studies of
the Si-SiO2 interface”, Phy. Rev. Letters, 60, 7, 1988.
40
41
[24] D-B.Kao, J.P. McVittie, W. Nix, and K.C. Saraswat, “Two-Dimensional Thermal
Oxidation of Silicon – II. Modeling Stress Effects in Wet Oxides”, IEEE Trans. Elec Dev.,
p. 25-37, 1988.
CHAPTER 3 – Surface passivation of planar germanium MOS using radical oxidation
3.1 Introduction:
Germanium (Ge) is now viewed as one of the most promising channel materials [1] due to
its
1. High bulk electron and hole mobility at low drift field
2. Process compatibility with Si MOS technologies
3. Lower temperature processing capability due to lower melting point than Si
4. Possible voltage scaling due to a narrower band gap than Si
In chapter 1 of this thesis, we have discussed the various research works on surface
passivation of Ge. Using these passivation techniques, scaled Ge pMOSFETs [1] have already
been demonstrated to have higher carrier mobility than Si pMOSFETs. Even for Ge
nMOSFETs which tend to suffer from high density of interface states near the conduction
band edge, recent progress for Ge dielectrics formation [2] demonstrated high electron
mobility for long channel Ge n-MOSFETs. However there is a serious lack in EOT scalability
of such dielectrics with thermal GeO2 interfacial layer (IL) thickness as high as 2 - 3nm. Also,
thermally grown GeO2 has substrate orientation dependent characteristics [3] and hence
unsuitable for future three dimensional MOSFET devices [4], [5].
This work explores radical oxidation (RO) of Ge [6] and was done by using the Slot Plane
Antenna (SPA) plasma oxidation equipment in Stanford Nanofabrication Facility (SNF) which
utilizes the Radial Line Slot Antenna (RLSA™) technology developed by TEL [7]. The
details of the equipment and process are discussed in chapter 2 of this thesis. The interaction
of O* radicals with Ge and GeO2 is illustrated in Fig. 3.1
GeO2
Ge
Ge Ge
GeO O O Ge
Ge
GeO2
Ge
Ge Ge
GeO O O Ge
Ge
Fig. 3.1 Schematic illustration showing possible mechanisms of formation and evolution of
GeO2 on Ge substrate using O* species.
42
As discussed in the previous chapter of this thesis, where radical oxidation was used for 3D
device passivation on silicon, the O* radicals serve as network formers for GeO2, repair
defects at the Ge surface and within the GeO2 dielectric.
The highlights of GeO2 grown using the SPA-RO equipment are -
1. Stoichiometric GeO2 – This is confirmed using XPS. Fig. 3.2 shows the detail of the
Ge 3d core level spectra for radical oxidation and thermal oxidation at the same
physical GeO2 thickness (~3.7 nm). Almost identical Ge-O peak intensity for (100)
and (111) substrate were observed for radical oxidation, where there is a finite
difference in the Ge-O peak intensities on (100) and (111) substrates for thermal
oxidation. This corresponds to substrate orientation dependent thickness for thermal
oxidation.
Fig. 3.2 Ge 3d core level spectra of XPS for thermal and radical oxidation.
2. Low temperature processing – The temperature of oxidation can be controlled to sub-
400ºC, which is lower than the decomposition/evaporation/desorption temperature of
GeO2. This is very important for low Dit and reliability of Ge dielectric [8]
3. Interaction of high density/reactivity oxygen (3P2) radical species (O*) with Ge which
results in planarization and atomic flatness of GeO2/Ge interface. The optical emission
spectrum shown in Fig. 3.3 due to the spontaneous transition from excited 3p3P to
3s3S was observed with high intensity at 845nm, while almost no molecular oxygen
peaks were observed [9].
43
5 0 0 5 5 0 6 0 0 6 5 0 7 0 0 7 5 0 8 0 0 8 5 0 9 0 0
O ( 3 p 5 P → 3 s 5 S ) 7 7 7 n m
O2+ (6
35nm
)
O2+ (5
97nm
)
O2+ (5
59nm
)
Opt
ical
Em
issi
on In
tens
ity (a
rb.u
nit)
W a v e le n g th (n m )
A r
A r
A r
4 k W 5 T o r r A r :O 2 = 1 2 0 0 :4 0 0
A rA r
A r
A rA r
A r A rA r
O ( 3 p 3 P → 3 s 3 S ) 8 4 5 n m
O2+ (5
25nm
)
Fig. 3.3 Optical emission spectrum for SPA radical oxidation [9]
4. Orientation independent growth rate oxidation kinetics – This has been explained in
chapter 2 of this thesis. For the case of Ge, this attribute has been verified using
growth rate measurements. This is shown in Fig. 3.4. Thermal oxidation shows higher
growth rate on (100) Ge as compared to (111) Ge. The growth rate is highly
temperature dependent and variation of temperature from 450ºC to 550ºC causes
significant change in the thickness of the oxide. On the other hand, radical oxidation
growth rate does not vary considerably with temperature [9].
Fig. 3.4 Growth rate of GeO2 and its dependence on substrate orientation
5. Sufficiently high band offsets - ΔEc > 1eV and ΔEv > 3.5 eV to Ge and the bandgap of
around 5.5 eV estimated using Electron Energy Loss Spectroscopy (EELS) and
0 10 20 30 40 50 600
5
10
15
20
25
30
35
40 (b)
(100) Ge (111) Ge
Oxi
de th
ickn
ess
(nm
)
Oxidation tim e (m in)
SPA radical oxidation 4kW 5Torr Ar:O 2=1200:400
450o C
400o C
350o C
0 10 20 30 40 50 600
5
10
15
20
25
30
35
40
550oC
500oC
Thermal oxidation Atmospheric (760Torr)
Oxi
de th
ickn
ess
(nm
)
Oxidation time (min)
(100) Ge (111) Ge
450oC
(a)
44
Synchrotron Radiation Photoemission Spectroscopy (SRPES) and the dielectric
constant of 5.86. This is very encouraging from the perspective of gate leakage
reduction for future high-k dielectrics on Ge. The ITRS benchmark for high-k/Si is a
band offset (both for conduction and valence band) of ~ 1eV for gate leakage
tolerance. The dielectric constant was measured by extracting the slope of EOT vs.
physical thickness of GeO2 [9]. The EOT was obtained from MOSCAP C-V
measurements of the gate dielectric stack, where the Al2O3 high-k cap thickness was
fixed to 5nm (confirmed using ellipsometry) and the GeO2 thickness was varied from
sub-1nm to 3nm. The same gate dielectric stacks were also used for EOT scaling
studies, which are discussed later in this chapter.
Ge
0.66eV
3.6±0.2eV
1.2±0.3eV
GeO2
5.5±0.1eV
Ec
Ev
Fig.3.5 Bandgap and band offsets reconstruction using EELS, SRPES [9]
6. Low interface state density using conductance method ~ 2x1011 cm-2eV-1 – The gate
stack analyzed by MOSCAP and MOSFET evaluation is shown in Fig. 3.6. The gate
stack consists of aluminum metal gate (100nm), ALD high-k Al2O3 (5nm) and
interfacial layers of GeO2 or GeON (thickness 1nm – 2nm) on top of Ge substrate.
The minimum Dit is comparable to state of the art high-k/Si interfaces.
45
Fig. 3.6 Dit measurement using conductance method for the gate stack shown on the right.
The thermal stability of the gate dielectric stack (Al2O3/GeO2/Ge) is compared with
GeO2/Ge using XPS. Significant desorption of GeO2 is observed without Al2O3 capping. The
results are shown in Fig. 3.7. Even with Al2O3 capping, the gate stacks become unstable at
600°C, which is evident from a small shoulder in XPS peaks indicating an appearance of
suboxide of germanium.
Fig. 3.7 Thermal stability of the GeO2/Ge dielectric stack as compared to Al2O3/GeO2/Ge
dielectric stack.
After analyzing the materials aspects and Dit of GeO2 obtained using radical oxidation, we
now apply the SPA-RO to grow ultra-thin interfacial layers on Ge MOSFETs. We confirm
substrate orientation independent growth rate and low interface state density of GeO2 on (100),
(110) and (111) Ge interfaces using electrical C-V measurements on MOSCAP structures.
36 34 32 30 28
S m all increase o f su boxid e
Inte
nsity
(arb
. uni
t)
B inding energy (eV)
As depositedAl2O 3cap /G eO 2/G e
N o s ign ifican t d eso rp tion
500oC 1m in 550oC 1m in 600oC 1m in
36 34 32 30 28
Inte
nsity
(arb
. uni
t)
Binding energy (eV)
As grownGeO2/Ge w/o cap
SignificantGeO2 desorption
500oC 1min 550oC 1min 600oC 1min
0.0 0.1 0.2 0.31011
1012
1013
Al/Al2O 3/G eO N or G eO 2/G e
Inte
rfac
e st
ate
dens
ity (c
m-2eV
-1)
Energy from m idgap (eV)
G eO N
1nm G eO 22nm G eO 2
D it im provem ent
E c
ALD – high-k
Bulk Ge GeO2 or GeON
Aluminum (M)
46
EOT scalability and electron mobility enhancement leading to drive current and trans-
conductance enhancement are also discussed.
3.2 Experiment
Bulk p-type Czochralski (CZ) grown Ge substrates, 500μ thick were obtained from Umicore,
with the following substrate orientation/resistivity (100)/0.014 Ω-cm, (111)/0.025 Ω-cm,
(110)/0.44 Ω-cm for MOS fabrication. Subsequent to active area patterning of 500nm SiO2
field oxide (LTO) and HF/ HCl last cleaning process (described later), gate dielectric was
formed using the SPA-RO engineered GeO2 Interfacial Layer (IL) [4 kW power, 5 Torr
process pressure, Ar:O2 = 1200:400 flow ratio, 400°C substrate temperature] capped with 5nm
350°C ALD Al2O3 (TMA + O3). After lithographic patterning of 100nm Al metal gate and
source/drain implant of P (40keV, 4x1015 cm-2), 30 min forming gas anneal (FGA) at 400°C
was performed. Ti (5nm)/Al (95nm) lift-off process provided contacts for source/drain regions.
The FGA anneal is used to passivate the interface states, remove the metal gate sputter
damage and activate the n-type dopants to active concentration levels of 8x1018 cm-3 [11] The
poor n-type dopant activation is a well known problem for Ge and is addressed in Chapter 4 of
this thesis.
Modified pre-diffusion clean for Ge surface [12] – This includes surface organics removal in
addition to oxide removal by cyclic HF clean. The removal of organics was performed by
washing the wafers in PRS-1000 at 45ºC for 5 min, followed by DI water dump rinse and spin
dry. The native oxides of Ge were removed by dipping the wafers in DI water. The sub-oxides
which can not be removed in DI water etching were etched by dipping the wafers in 2% HF
solution for 60 s. A cyclic clean involving DI water and 2% HF treatments was employed
three times to remove most of the oxides on the surface. Following the cylic HF clean, the
wafers were dipped in HCl:H2O (1:1) for 1 min to obtain an oxide-free surface followed by a
1min DI water rinse and then spin dry.
3.3 Results and Discussion
High Frequency (HF) 1 MHz and low frequency quasi-static (QS) or U-shaped CV
characteristics are shown in Fig. 3.8. The minimum capacitance for the CVs varies because of
difference in the substrate doping for different orientations of germanium substrates. All CV
47
measurements were performed at -40ºC substrate temperature (substrate doping density was
computed accurately from the minimum capacitance), in order to suppress the minority carrier
generation response due to the low band gap of Ge.
-2 -1 0 1
0.0
0.2
0.4
0.6
0.8
Cap
acita
nce
(μF/
cm2 )
Gate Voltage (V)
Orientation / Resistivity Ge(100)/0.014 Ge(110)/0.44 Ge(111)/0.025
Similar EOTGeO2 IL + High-k
-3 -2 -1 0 1 2
0.4
0.5
0.6
0.7
0.8
Orientation / Resistivity Ge(100)/0.014 Ge(110)/0.44 Ge(111)/0.025C
apac
itanc
e (μ
F/cm
2 )
Gate Voltage (V)
Fig. 3.8 High frequency (1MHz) and Low frequency (QSCV) for Ge MOS
We observe an order of magnitude reduction in Dit with insertion of GeO2 Interfacial Layer
(IL) as shown in Fig. 3.9. This is consistent with Dit values reported for high-k directly on Ge
by other groups [13]. As per the C-V characteristics in Fig. 3.8, GeO2 layer on Ge (100), (110),
(111) substrate orientation provide similar EOT values. This is noted from the similar value of
accumulation capacitance. This confirms the substrate orientation independent growth rate for
SPA-RO engineered GeO2 IL. Fig. 3.9 shows the mid gap Dit values [14]. We obtain similar
Dit values (2–3 x 1011cm-2eV-1) for different substrate orientations.
1010
1011
1012
1013
Substrate Orientation
D
it at
mid
gap
(cm
-2/e
V) no IL
GeO2 IL + High-k
Ge(111)Ge(110) Ge(100)Ge(100)
Fig. 3.9 Mid-gap Dit for the Ge MOS structures.
This is attributed to the physical interaction of highly active O* radical species with Ge
substrate. The very small size of O* species [15] enable it to penetrate any surface orientation.
48
The oxidation front can be immediately amorphized [7] with formation of Ge-O bonding by a
highly reactive oxygen radical with a small activation energy for the Ge-O bonding creation.
Hence, surface orientation with different number of bonds and bond density on the oxidation
front does not determine the oxide thickness or interface state density. This has also been
correlated to atomically flat Ge/GeO2 surface after SPA-RO [9] verified using AFM and
Si/SiO2 surface [15] verified using AFM/TEM.
This result encourages the usage of SPA-RO for a three dimensional device structure, such
as gate all around structures for both Si and Ge devices. These devices are discussed in
Chapter 2 and Chapter 1 of this thesis respectively, where electrical data is presented along
with TEM pictures. Keeping the Al2O3 thickness fixed at 5nm, the GeO2 thickness was varied
from 5nm to 0.6nm, as per the SPA-RO growth kinetics discussed before [9]. The gate leakage
is measured for the gate stacks with GeO2 interfacial layer (IL) (Fig. 3.10). In another
experiment, MOSCAPs without GeO2 IL were fabricated with varying Al2O3 thickness. Those
are labeled as No IL samples. The gate leakage is higher for MOSCAPs without GeO2 IL.
This can be explained by the higher values of Dit [13] reported for high-k directly on Ge (no
IL samples). The EOT scalability is limited to ~ 3nm due to Al2O3 (k~8) capping layer on top
of GeO2. Further scalability of EOT can be achieved by using higher-k dielectrics (like HfO2
etc.) as capping layers for GeO2.
0 1 2 3 4 5 6 7 8 910-9
10-8
10-7
No IL GeO2 IL
Gat
e Le
akag
e @
VFB
+ 1
(A
/cm
2 )
EOT (nm)
0.6nm GeO2
Fig. 3.10 Gate leakage vs. EOT for the Ge MOS
After analyzing the MOSCAPs and EOT scalability for GeO2, this process is applied to an n-
type Ge MOSFET structure. The fabrication scheme is discussed in the experiments section
(section 3.2) of this chapter. The benefits of GeO2 IL are evident in Fig. 3.11 where MOSFET
49
devices are electrically analyzed. An enhancement in drive current with the presence of GeO2
IL in the gate stack is shown, despite an increase in EOT due to the IL. If we compare
MOSFETs with and without IL on Ge (100), we observe ~ 2X increase in drive current.
Further enhancement of drive current is also observed for Ge (111) interface with IL. This is
due to the preferential population of electrons in the L valley, which has the smallest
conductivity mass [16] Corresponding enhancements in trans-conductance are also observed
for the MOSFETs (Fig. 3.11 (b)). For MOSFET I-V measurements, Vds is fixed at 10mV and
Vgs is varied from -0.5V to 2V.
0 1 210-9
10-8
10-7
Dra
in C
urre
nt (A
/μm
)
Gate Voltage (V)
Ge (100) no IL Ge(100) Ge(111)
W/L = 100μ/ 20μ
0 1 2
0.03.0µ6.0µ9.0µ
12.0µ15.0µ18.0µ Vds = 10 mV, W/L = 100μm/ 20μm
GeO2 IL; Ge (100) no IL Ge(100) GeO2 IL; Ge(111)
(a) (b)
Fig. 3.11 (a) Drive current and (b) Transconductance enhancements for MOSFETs with GeO2
IL.
0.1 1
0200400600800
1000 GeO2 IL; Ge (100) no IL Ge(100) GeO2 IL; Ge(111)
Effective Field (MV/cm)
Fig. 3.12 Electron mobility enhancement for high-k/Ge gate stacks with GeO2 IL and substrate
orientation
50
This drive current and transconductance enhancement due to GeO2 IL can be understood in
terms of mobility enhancement, which can be correlated to Dit reduction due to GeO2 for high-
k/Ge gate stacks.
The electron mobility is estimated using the split CV analysis (no series resistance
correction is performed for poor n-type dopant activation) in Fig. 3.12 [11]. The electron
mobility values for (100) Ge are lower than universal Si. This is due to two reasons (1) poor
donor activation (less than 1x1019 cm-3 at reduced activation temperature of 400°C) in
source/drain and (2) charge trapping in GeO2 IL due to fast traps and slow traps in the over-
lying high-k dielectric layer [11] This can be alleviated by the use of high n-type dopant
activation techniques for Ge as discussed in [17] and engineering robust GeO2 IL [2]
combined with low defects in high-k films.
3.4 Conclusion
Ultra-thin interfacial layers with low interface state density are demonstrated for long
channel Ge MOSFETs on (111) and (100) substrates. The GeO2 interfacial layer obtained
using radical oxidation provides substrate orientation independent properties – physical
thickness and interface state density. These characteristics of interfacial layer are important for
passivation of three dimensional MOSFET structures and planar MOSFETs with different
substrate orientations. EOT scalability of GeO2, electron mobility and drive current
enhancement for MOSFETs on Ge (100) and (111) substrates are observed in the presence of
the GeO2 IL.
References [1] G. Hellings, J. Mitard, G. Eneman, B. De. Jaeger, D.P Brunco, D. Shamiryan, T.
Vandeweyer, M. Meuris, M. M. Heynes, and K. De Meyer, “High Performance 70nm
Germanium pMOSFETs with Boron LDD Implants,” IEEE Electron Device Letters, vol.
30, p. 88, 2009.
[2] C.H. Lee, T. Nishimura, T. Tabata, K. Nagashio, K. Kita, and A. Toriumi , “High electron
mobility Ge n-channel MOSFETs with GeO2 grown by high pressure oxidation,” Int.
Conf. Solid State Devices and Materials Tech. Dig., p. 1000-1001, 2009.
51
[3] M. Kobayashi, G. Thareja, M. Ishibashi, Y. Sun, P. Griffin, J. McVittie, P.Pianetta, K.
Saraswat, Y. Nishi, “Radical Oxidation of germanium for interface gate dielectric GeO2
formation in metal-insulator-semiconductor gate stack,” J. Appl. Phys., vol. 106, p.
104117, 2009.
[4] J. Feng, G. Thareja, M. Kobayashi, S. Chen, A. Poon, Y. Bai, P. Griffin, S. Wong, Y.
Nishi, and J. Plummer, “High-Performance Gate-All-Around GeOI p-MOSFETs
Fabricated by Rapid Melt Growth Using Plasma Nitridation and ALD Al2O3 Gate
Dielectric and Self-Aligned NiGe contacts,” Electron Device Letters, vol. 29,7, p. 805-
807, 2008.
[5] G. Thareja, J. Park, Y. Hirota, P. Griffin, and Y. Nishi, “Surface Passivation of 3D
Vertical MOSFET Using Low Temperature Radical Oxidation,” IEEE. Electron Device
Letters (unpublished).
[6] T. Ohmi, M. Hirayama, and A. Teramoto, “New Era of Silicon Technologies due to
radical reaction based semiconductor manufacturing”, J. Physics D: App. Phy, 39, R1-R17,
2006
[7] T. Ohmi, S. Sugawa, K. Kotani, M. Hirayama, and A. Morimoto, “New Paradigm of
Silicon Technology” Proceedings of the IEEE, p. 394-412, vol. 89, 3, 2001.
[8] K. Kita, S. Suzuki, H. Nomura, T. Takahashi, T. Nishimura and A. Toriumi, “Direct
Evidence of GeO Volatilization from GeO2/Ge and Impact of Its Suppression on GeO2/Ge
Metal-Insulator-Semiconductor Characteristics”, Jpn. J. Appl. Phys., 47 2349 (2008)
[9] M. Kobayashi, G. Thareja, M. Ishibashi, Y. Sun, P. Griffin, J. McVittie, P. Pianetta, K.
Saraswat, and Y. Nishi “Radical Oxidation of germanium for Interface Gate Dielectric
GeO2 formation in metal-insulator-semiconductor gate stack”, Journal of Applied Physics,
106, 104117, 2009
[10] G. Thareja, M. Kobayashi, Y. Oshima, J. McVittie, P. Griffin, and Y. Nishi, “Low Dit
optimized interfacial layer using high density plasma oxidation and nitridation in
Germanium High-k gate stacks”, Dev. Res. Conf., p. 87-88, 2008
[11] D.Kuzum, T. Krishnamohan, A. Nainani, Y. Sun, P.A. Pianetta, H.S- P. Wong, and
K.C. Saraswat, “Experimental demonstration of High mobility Ge NMOS,” in IEDM
Tech. Dig., 2009, p. 453-457.
[12] J.-Y. Kim, PhD Thesis, Material Science and Engineering, Stanford University.
[13] C-C. Cheng, C-H. Chien, G-L. Luo, C-L. Lin, H-S. Chen, J-C. Liu, C-C. Kei, C-N.
Hsiao, and C-Y. Chang, “Junction and Device Characteristics of Gate-Last Ge p- and n-
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53
MOSFETs with ALD-Al2O3 Gate Dielectric,” IEEE Trans. Electron Devices, vol. 56, no.
8, p. 1681, 2009.
[14] D. Schroder, “Semiconductor Material and Device Characterization,” Wiley, 2006
[15] M. Nagamine, H. Itoh, H. Satake, and A. Toriumi, “Radical oxygen process for highly
reliable SiO2 with higher film-density and smoother SiO2/Si interface ” , Elec. Dev.
Meeting, p. 593-596, 1998
[16] Y. –J. Yang, W.S. Ho, C.-F. Huang, S.T. Chang, C.W. Liu, “Electron mobility
enhancement in strained-germanium n-channel metal-oxide-semiconductor field-effect-
transistors” Applied Physics Letters, 91, 102103, 2007
[17] G. Thareja, J. Liang, S. Chopra, B. Adams, N. Patil, S.-L. Cheng, A. Nainani, E.
Tasyurek, Y. Kim, S. Moffatt. R. Brennan, J. McVittie, T. Kamins, K. Saraswat, Y. Nishi,
“High Performance Germanium NMOSFET with Antimony Dopant Activation Beyond
1x1020 cm-3” IEDM Tech Dig. , p. 245-248, 2010.
CHAPTER 4 – Source/Drain junction engineering in Ge nMOSFET
4.1 Introduction:
Source/Drain engineering for MOSFET needs to meet two requirements which may often be
constrained to each other
1. Junction resistance
2. Junction depth
The on-resistance (Fig. 4.1) of the MOSFET consists of two components,
1. Channel resistance (Rch)
2. Series resistance (Rseries = 2R)
As device dimension scales down, the channel resistance decreases but the series resistance
does not scale.
Fig. 4.1.Schematic of the on-resistance for the MOSFET consisting of Rch and Rseries = 2R.
However, for performance enhancement Rseries should remain at a small percentage of Ron as
historically Rseries has been around 10% of Ron [1] While device performance has increased in
each technology node (more recently by reducing Ron using Idsat enhancement techniques such
as strain engineering, high-k dielectrics and Vdd scaling down), it would be very challenging to
reduce Rseries especially for sub-22nm ITRS technology nodes.
The series resistance can be divided into the following four components (Fig. 4.2)-
54
1. Extension to gate overlap resistance (Rov) – This is a strong function of doping
concentration in the gate overlap region and the lateral abruptness of the overlap
doping profile. Higher doping concentration and steeper doping profile are required
for improved SCE and reduced series resistance.
2. S/D extension resistance (Rex)
3. Deep S/D resistance (Rdp)
4. Contact resistance at the metal-semiconductor interface (Rcsd) – This is an exponential
function of active doping concentration (N) and metal-semiconductor barrier height
(φm). Rcsd is proportional to exp (φm / N).
Fig. 4.2 Schematic representation of various components of S/D series resistance.
Out of all these components of series resistance the toughest scaling problem is the contact
resistance [2] reduction which has not been successful as shown in Fig. 4.3, in the past 4
technology nodes.
Fig. 4.3 Series resistance vs. physical gate length as channel length scaling proceeds.
55
Reduction of resistive components other than Rcsd, has been achieved using design solutions
of raised source/drain structures [3] and selective epi-SiGe in S/D [4], however contact
resistance reduction has been a recurrent problem across different technology nodes.
Other than the resistance problem which mandates a source/drain junction engineering, the
other issue stems from device scaling. The continued reduction of device dimension causes
short channel effects (SCE). These effects arise from channel depletion charge sharing
between source and drain as the distance between them is reduced. Since the gate loses control
over the channel depletion charge, the threshold voltage reduces and the off-current for the
MOSFET increases as the device dimension reduces. This is illustrated in Fig. 4.4.
VTH ↓ Ioff ↑
Scaling
Fig. 4.4 Threshold voltage reduction as the device dimension is scaled.
The SCE are further exacerbated under the influence of a drain bias. This is referred as the
drain induced barrier lowering (DIBL). The SCE can be relieved by the following approaches,
as depicted in Fig. 4.5:
1. Reduction of oxide thickness (Tox) or the equivalent oxide thickness (EOT) – This
provides higher control of gate over the channel region of MOSFET. This is realized
using high-k gate dielectrics, which provide higher gate capacitance.
2. Reduction of depletion width (Wdep) – Higher doping in the channel region reduces
the depletion region width. However, the trade-off is the associated reduction in
carrier mobility due to higher doping. This problem is solved using specialized
pocket/angled implants near the source/drain to channel edge regions.
56
Fig. 4.5 Techniques to reduce the short channel effects (SCE)
3. Reduction of junction depth (Xj) - The requirement for scaling a junction depth is
becoming more stringent with decreasing device dimension as shown in Fig. 4.6.
Super scaled technologies need junction depth less than 10nm.
Fig. 4.6 Requirement of sub-10nm junction depth for scaled technologies
Considering the above mentioned issues of resistance and SCE arising from source/drain
junctions, the requirements in the future are to develop junction technologies with shallow
junction depth (which reduces the SCE) and high dopant activation (which provides reduced
series resistance). This research provides solutions for both these problems in case of n-type
germanium by using low energy antimony beam-line implantation or plasma immersion ion
implantation and combining it with laser annealing.
57
4.2 State of the art junction technology
Formation of shallow junctions is accompanied with advanced process design, cost
consideration of added process complexity to conventional schemes of dopant incorporation
(ion implantation) and implanted dopant activation (rapid thermal annealing, flash annealing).
Shallower junctions are obtained by,
1. Reducing the ion implantation energy
2. Dopant profile tailoring using pre-amorphized implants (PAI) which minimize dopant
ion channeling
However, the demand for low-energy implantation will be increasingly difficult to meet for
sub-22nm technology nodes because throughput is limited by low beam current from the ion
source to wafers. To address the issue of decreased productivity at low energy beam-line ion
implantation, the deceleration mode is used, in which ions are extracted at higher energies to
draw high beam current and decelerated before they reach the wafer targets. However some of
the dopant ions are neutralized by charge exchange with the background gas prior to
deceleration. These neutrals are not decelerated and therefore reach the wafer at higher than
desired energies. This effect is known as energy contamination and leads to a deeper than
desired dopant depth profile. In the decel mode operation, beam spreading becomes a problem
because of increased coulomb repulsion due to decreased ion velocities for low energy
implants. This is illustrated in Fig. 4.7
Fig. 4.7 Energy contaminations in decel mode ion implanter. The implanted profile is deeper
than desired.
58
Various doping techniques such as molecular implant [5], infusion doping [6] and plasma
doping [7] have been proposed to counter the limitations of beam-line implantation.
Molecular implants such as B10H14 and B18H22 are well suited for direct replacement of
mono-atomic ion species for low-energy implantation providing improved throughput, while
retaining the precision of ion dose, repeatability, uniformity and angle control of ion
implantation. This is the approach currently being pursued by industry.
Infusion doping utilizes gas cluster ion beam (GCIB) for shallow doping applications. GCIB
processing uses clusters (>5000 atoms) consisting of Ar or He or B containing molecules such
as B2H6 and BF3. After adiabatic expansion that causes cluster formation, clusters are ionized
and accelerated to the substrate. Upon impact the cluster energy is transferred to the substrate
surface causing rapid heating and dissociation of molecules into atoms. The gas atoms leave
the surface and the solid species intermix or are infused in the substrate. Although the clusters
have higher total energy, the energy per atom is very low (10 eV / atom) and hence this
intermixing occurs in very shallow depths. Extreme abruptness and lack of ion channeling or
energy contamination are the main features of the infusion doping. However issues remain in
terms of surface modification, etching and strain in the substrate.
Fig. 4.8 Gas cluster ion beam (GCIB) infusion doping
In plasma doping or plasma immersion ion implantation technique, the wafer is placed in a
vacuum chamber filled with process gas (BF3, AsH3, and PH3). Application of negative
voltage to the wafer ionizes the gas and attracts these ions toward the wafer, resulting in ion
implantation. The ionized species present in the plasma will be implanted into the wafer,
causing the risk of contamination and etching. To minimize these effects, a series of voltage
pulses is applied to the wafer such that plasma is present only during the implant time. Within-
wafer and wafer-to-wafer uniformity are important issues for plasma doping because
implanted ions have a broad range of energies rather than a specific energy. Fig. 4.9 shows a
schematic of the chamber used for plasma doping enabled using a toroidal plasma source.
59
Fig. 4.9 Schematic of plasma doping chamber
Subsequent to dopant incorporation, the next step is dopant activation and damage annealing.
The temperature-time ranges of various conventional and advanced annealing techniques are
summarized in Fig. 4.10. The conventional annealing approaches of furnace and RTP are
unsuitable for ultra shallow junctions. Milli-second flash annealing is the current standard in
the industry. However the thrust is towards low diffusion (nanosecond pulsed annealing) with
higher activation (higher anneal temperature). These can be realized with more advanced laser
anneals, which would be discussed in subsequent sections.
Fig. 4.10 Temperatue-time ranges of various conventional and advanced annealing techniques
60
Rapid thermal processing (RTP) is also facing conflicting challenges of dopant diffusion
during annealing vs. electrical activation because of solid solubility limits. Though higher
anneal temperatures are desirable with current RTP tools, the annealing time at these elevated
temperatures are too long to suppress significant dopant diffusion, resulting in deeper
junctions.
Spike annealing [8] with a very high ramp rate has been used to meet 45 nm CMOS
technology requirements for shallow junctions. But in order to meet the requirements for sub-
45 nm technologies, spike annealing will not be adequate; especially transient enhanced
diffusion will still pose great challenges for ultra-shallow junction formation.
Flash annealing and laser annealing are often regarded as “diffusion-less” annealing
techniques. Flash annealing uses an array of flash lamps ignited by high voltage pulses to
achieve annealing times in the range of milli-seconds [9].
Laser annealing is a metastable process lasting for a few microseconds to nanosceconds in
which dopants can be frozen in the substitutional sites well above the solid solubility limit
[10], but equipment maturity at this moment could be the main challenge for its adoption.
Both annealing techniques are capable of heating the surface of substrate to very high
temperatures often near melt temperatures for the substrate.
4.3 Junction metrology
1. TEM microscopy is used to observe the as-implanted and annealed junction defects.
2. Micro Four Point Probe (M4PP) by Capres is used for accurate sheet resistance
measurement of ultra-shallow junctions. It involves soft landing of tapered SiO2
cantilevers with Cr/Au tips arranged in the form of a four point probe. Fig. 4.11
provides a top view for the M4PP.
Fig. 4.11 Top view of a M4PP.
61
3. Chemical concentration of dopants in Ge is measured using SIMS ( Quad-SIMS
ADEPT 1010, Physical Electronics - Cs beam, 500eV and O2+ beam, 500eV)
4. Active dopant concentration in Ge is measured using Spreading Resistance Profiling
(SRP). This technique works well for deep junctions (> 80nm in junction depth)
because of the challenging sample preparation in terms of a beveled sample edge. For
ultra shallow junctions, a combination of SIMS, M4PP sheet resistance (ρs) with
published values of mobility [11] has been used. The correlation between these
quantities can be dialed into the following equation to estimate the active dopant
concentration.
dxxnNxnejX
B
s
∫ −
=
0
)(*])([*
1
μ
ρ (4.1)
Other techniques for measurement of dopant activation such as Hall [12] and Raman
spectroscopy [13, 14] exist in the literature, but have not been used in this research.
5. Electrical characterization is performed using low temperature diode I-V
measurements
6. Crystallinity of the junctions is assessed using Raman microscopy
4.4 Ultra shallow junction (USJ) in Ge
Plasma Immersion Ion Implantation (P-III or P3I) equipment from Applied Materials is used
for fabrication of USJ in Ge. Both n-type (using PH3 gas) and p-type (using BF3 gas) USJ are
demonstrated. The P3I energy is of the order of 1.2kV. Sub-10nm junction depths (@5x1018
cm-3) are obtained. Further scaling of junction depths is possible using lower energies (0.6 kV)
as shown in the graph or by using bigger sized dopants e.g arsenic based implants with AsH3
gas. The as-implanted dopant profiles are profiles using SIMS (Fig. 4.12).
Other alternative for n-type dopant is antimony (Sb), which has also been used in this
research. Antimony is a heavier atom than Ge; hence it can form shallow junctions in Ge at
reasonable implant energies using conventional beam line ion implantation. The next step is to
anneal these implanted junctions with special emphasis on n-type dopant activation.
62
0 50 100 150 2001017
1018
1019
1020
1021
1022
SIMSPIII (Boron)
1.2 kV, 1x1015 cm-2
0.6 kV, 1x1015 cm-2
Depth (A°)
0 50 100 150 2001017
1018
1019
1020
1021
1022 1.2 kV, 1x1015 cm-2
0.6 kV, 1X1015 cm-2
Con
cent
ratio
n (c
m-3
)
Depth (A°)
P-III (Phosphorus)SIMS
Fig. 4.12 SIMS profiles for p-type and n-type dopants in Ge
4.5 Activation of n-type dopants in Ge
Many research efforts have failed to provide high n+ electrical activation for Ge in the past.
The first set of experiments using rapid thermal annealing (RTA) of P, As and Sb implanted
in Ge resulted in electrically active concentrations of 2 x 1019, 1 x 1019 and 2 x 1018 cm-3
respectively, while significant diffusion of dopants took place at elevated temperatures (600-
700°C). These results are shown in Fig. 4.13 [15].
Fig. 4.13 P-type and n-type dopant activation using ion implantation and rapid thermal
annealing (RTA) [15]
Note that the high acceptor dopant activation with boron is possible through beam line ion
implantation and RTA. The poor activation of n-type dopants [16] is ascribed to the point
defects in Ge, such as vacancy-interstitial pairs, which act as acceptor states in the band gap of
Ge [17]. This compensates the total active donor concentration, thereby reducing the net active
63
n-type dopant concentration. This is depicted in Fig. 4.14
EV
Negatively charged acceptor state-AV-
EFEc
Fig. 4.14 Acceptor states causing donor concentration compensation in n-type Ge
Furnace annealing [18] has also resulted in highly resistive source/drain regions indicating
poor electrical activation of n-type dopants. Millisecond flash annealing [19] of phosphorus
doped shallow junctions in Ge, provided negligible dopant diffusion and dopant activation up
to 6 x 1019 cm-3 .In-situ doping [20] of phosphorus during hetero-epitaxial growth of Ge on Si
resulted in electrically active concentration of 1 x 1019 cm-3 and the significant amount of
remaining defects in the n+ grown layers. These results are benchmarked (Table 4.1) with our
results in subsequent sections.
Annealing Dopant Electrical Activation (cm-3)
Furnace Anneal P 8 x 1018
Rapid Thermal Anneal P / As / Sb / B 2 x 1019 / 8x1018 / 8x 1018/ 1x1020
Flash Anneal P 6x1019
In-situ doping P 1x1019
This Work (LTP) P/ As / Sb / B > 1 x 1020
Table 4.1 Benchmark of annealing, dopant type and electrical activation across literature
Fig. 4.15 provides a theoretical plot for contact resistance vs. active dopant concentration for
n-type dopants in Ge. As can be seen from this plot, significant reduction in contact resistance
(the most dominant component of series resistance) can be obtained as the active dopant
concentration increases. The conduction mechanism of carriers at the metal-n+ Ge contacts
can be changed from Schottky thermionic emission at low dopant concentration to tunneling
64
field emission at high n-type dopant concentrations [21]. Most of the prior research work for
n-type dopant activation is ~ 2x1019 cm-3 or below. Our research work provides the highest
dopant activation of > 2x1020 cm-3. Very few reports [22] exist for high n+ dopant activation
(> 1020 cm-3). Using laser annealing [23], high activation was demonstrated for ultra shallow
plasma doped phosphorus junctions in Ge. Laser annealing is very efficient for re-
crystrallization of ion implanted Ge substrates at lower energy fluences as compared to Si
[24]. It is especially useful for annealing of ion implantation of Sb in Ge. When such heavier
ions are introduced in Ge crystal using ion implantation at high doses, severe damages
consisting of craters and surface voids [25] have been observed, similar to those in earlier
reports for In, Bi and Sn implanted in Ge at high doses [26]. RTA (600°C – 700°C) [27] has
proven inefficient in annealing of such defects, resulting in poor electrical activation and
significant dopant diffusion at elevated temperatures
1018 1019 1020 102110-1210-1010-810-610-410-2100102104
0eV
0.1eV
0.2eV
0.3eV
0.4eV
0.5eV
Con
tact
resi
stan
ce (Ω
-cm
2 )
Doping concentration (cm-3)
ΦB = 0.6eVMetal/Ge contact
Fig. 4.15 Contact resistance vs. active n-type dopant concentration in Ge
The laser annealing set-up is shown in Fig. 4.16, courtesy Applied Materials [28]. The laser
thermal processing setup consists of a pulsed laser of 532 nm as the primary laser for
annealing. The other laser, HeNe (633nm) is used for reflectivity measurements to detect the
melt initiation/duration during/after annealing. The substrate (in this case Ge) is mounted on
an X-Y table. The optics and stage are controlled by the computer, oscilloscope and CCD
paraphernalia.
65
Fig. 4.16 Laser annealing setup
The system-level scheme of this laser annealing is to integrate it in optical lithography stepper
equipment and enable die-by-die laser annealing. The laser spot size can be matched to the die
size. The laser annealing integration is shown in Fig. 4.17.
4.6 Device Fabrication
Czochralski (CZ) grown Ge wafers, 500μ thick, (100)-oriented, Ga-doped were obtained
from Umicore. After depositing CVD SiO2 as field oxide, active area was patterned and ion
implantation of Sb ions was carried out at energy of 10keV and a dose of 5x1015 cm-2 at room
temperature, with a tilting angle of 7°. Laser annealing was performed using a pulsed 532 nm
laser with the energy fluence of 0.15-0.7 J/cm2 at single pulse. The metal electrode consisting
of Al (95nm)/Ti (5nm) was evaporated in an electron beam chamber. The electrically active
concentrations of dopants were determined using Spreading Resistance Profiling (SRP) [29].
The chemical concentration of Sb dopants was determined using Quad-SIMS (ADEPT 1010,
Physical Electronics, Cs beam, 500eV).
HeNe Laser
Monitor
CCD
Fast Oscilloscope633nm
Computer
Optics
X-Y Laser
66
X-Y
Homogenous Laser
Probe Laser Beam
Fig. 4.17 Die by Die laser annealing performed on a wafer
4.7 Thermo-optical constants of Ge
S.No Parameter c-Ge a-Ge
1. Melting Point - Tm (K) 1232 850
2. Enthalpy of Melting – ΔHm (J/g) 411 300
3. Reflectivity – R (532nm laser) 0.4 0.4
4. Absorption Coefficient- α (cm-1) 5 x 105 5 x 105
5. Specific Heat – Cp (J/g/K) (Average between R.T and Tm)
0.33 0.33
6. Thermal Conductivity – κ (W/cm/K) (Average between R.T and Tm)
0.3 0.3
Table 4.2 Thermo-optical constants for Ge for a 532nm laser [30]
67
Order of magnitude calculations are performed for the laser annealing scenario for Ge, using
the themo-optical constants for Ge in Table 2. The schematic is provided in Fig. 4.18.
Fig. 4.18 Laser annealing scenario
The various parameters are
D = Diffusivity = κ / ρ Cp ~ 0.2 cm2/s
t = pulse width
α = absorption coefficient (cm-1)
R= Reflection coeffecient
L = characteristic heat diffusion length ~ 1 μ
d1 = laser absorption depth = α-1 ~ 20nm << L
d2 = a/c boundary depth (of the order of junction depth) <<L Single laser pulse of 532nm is
sufficient to melt the amorphous region
Annealing threshold is the minimum laser fluence required to melt the amorphous region,
which is given by the heat equation, Cp * ρ * d2 * ΔT = (1 – R) * I I = 0.2 J/cm2
(considering ΔT = Tm), higher laser fluence would drive the melt deeper in the substrate.
Note, shallower junctions (smaller d2) have lower annealing threshold
Recrystallization velocity (Vrec) is the velocity of the melt front, which can be obtained from
another set of heat equations. Refer Fig. 4.19.
Temperature
Absorption Depth ~ α-1
Incident Laser Energy (I)
L
a/c boundary depth
Reflected Laser Energy (R)
68
The latent heat liberated at the advancing interface = ΔHm * ρ * Vrec
This heat must be balanced by the heat flow into the substrate = κ * Tm / L Vrec ~ 7 cm/sec
Heat Flow
liq-Ge c-Ge
Fig. 4.19 Schematic illustrating the velocity of the liquid-solid interface
As the laser fluence is enhanced, the melt penetrates deeper into the substrate. This is
confirmed using SIMS and sheet resistance measurements for all dopings (P, A, Sb). The
SIMS profiles are shown in Fig. 4.20. Careful control of laser fluence is required. The laser
fluence is to be adjusted such that the as-implanted profile matches the annealed profile. For
the case of Sb implants this was achieved. The blue curve corresponding to 0.2 J/cm2 overlaps
the black curve (as implanted) in Fig. 4.20 (c).
Fig. 4.20 SIMS profiles for (a) P3I P (b) P3I As and (c) Ion Implanted Sb
If we re-plot the results of Sb dopants/anneals from Fig. 4.21 in Fig. 4.22, including sheet
resistance measurements data at lower fluence, we can get a much clear understanding for the
operation of laser annealing.
0 20 40 60 80 101017
1018
1019
1020
1021
1022
0
Dopant Diffusion
as implanted LTP 0.3 LTP:0.4 Jcm-2
P3I- As - 3kV, 1x1015 cm-2
Depth (nm)
0 20 40 60 80 1001017
1018
1019
1020
1021
1022
Vrec
0 500 1000 1500 20001018
1019
1020
1021
1022P3I - P - 1.2kV, 1x1015cm-2
as implanted LTP 0.3 LTP:0.4 Jcm-2
Depth (nm)
Dopant Diffusion
Con
cent
ratio
n (c
m-3
)
Con
cent
ratio
n (c
m-3
)
Depth (A)
SIMS - as implanted SIMS - 0.4 J/cm2 SIMS - 0.2 J/cm2
SIMS - 0.7 J/cm2
SRP - 0.7 J/cm2
Sb - 10keV, 5 x 1015 cm-2
69
0.2 0.3 0.4 0.5 0.6 0.7101
102
Shee
t Res
ista
nce
(Ω /
)
Fluence (J-cm-2)
B Sb P As
Fig. 4.21 Sheet resistance of laser annealed junctions. Higher fluence provides lower sheet
resistance.
0.00 0.15 0.30 0.45 0.60 0.75
0
100
200
300
400
500
recrystallization without defects
recrystallization with defects
Sh
eet R
o (Ω
/ )
Laser Fluence (J-cm-2)
as implanted
Fig. 4.22 Sheet Resistance as a function of laser fluence.
This significant reduction in sheet resistance can be explained by the melt-regrowth model
[31]. When the melt front extends to the crystalline Ge substrate underneath, epitaxial
regrowth of the molten region takes place, which enables high activation of Sb dopants.
Increase of the laser fluence from 0.15 J/cm2 to 0.7 J/cm2 caused a reduction in sheet
resistance from 500 Ω/ to 17 Ω/. The laser fluences are higher than the threshold for
melting Ge surface [32], as verified by reflectivity measurements (not shown). Fig. 4.20 (c)
shows the concentration-depth profiles of antimony ion implantation at 10keV, 5 x 1015 cm-2,
which provides an as-implanted junction depth (@ 5 x 1018 cm-3, from SIMS profile) of
~20nm as confirmed by SIMS. The fluence of the laser has to be carefully adjusted to anneal
70
just the implanted region. This value of laser fluence is > 0.2 J/cm2 for our experiment which
was in consistence with the one estimated from calculations. Higher laser fluence drives the
melt deeper into the substrate, well beyond the implanted region. SRP profiling confirms high
electrical activation of 2x1020 cm-3 for laser fluence of 0.7 Jcm-2, which provides a junction
depth of ~120nm.
B A C
Fig. 4.23 TEM micrographs for (A) as-implanted samples (B) laser annealed with 0.2 J/cm2
(C) laser annealed with 0.4 J/cm2
From the TEM analysis, the as-implanted Sb in Ge clearly shows craters and surface voids
as shown in Fig. 4. 23. (A). When the laser fluence is at 0.2 J/cm2 (Fig. 4.23 (B)), the re-
crystallized film has defects. Higher laser fluence as in Fig. 4.23 (C) provides re-crystallized
film without defects.
-0.5 0.0 0.5 1.010-4
10-1
102
I diod
e (A/c
m2 )
Voltage (V)
Laser Fluence 0.15 J/cm2
0.2 J/cm2
0.4 J/cm2
0.7 J/cm2
Fig. 4.24 I-V Characteristics of n+/p Ge junction diode, measured from -0.5V to 1V.
Fig. 4.24 illustrates the n+/p Ge junction I-V characteristics for different laser fluence.
Reduction in the off-current for the diode is observed as the laser fluence increases. This can
be attributed to the annealing of implanted defects. At high laser fluences of 0.4 and 0.7 J/cm2,
the off-current for the n+/p diode stays at the similar level and dopants travel deeper into the
substrate, as shown by SIMS data. This means that the laser fluence has to be carefully
71
optimized to penetrate all the way to the implanted region.
Considering the sheet resistance (ρs) values, junction depth from Fig. 4.20 and background
p-type doping (NB) of 1x1015 cm-3, theoretical estimation of dopant activation was made by
using the equation (4.1). Using the mobility (μ) values [11], we obtained electrically active
dopant activation beyond 1020 cm-3 for laser fluence >0.2 J/cm2.
The crystallinity of the laser annealed junctions was confirmed using Raman analysis [33].
The as-implanted junctions show very low Raman signal with truncated peaks and smeared
out features corresponding to a-Ge. After laser annealing at 0.4 J/cm2, a sharp peak
corresponding to c-Ge is obtained at 300 cm-1. This confirms the crystallinity restoration
subsequent to laser thermal processing corroborating the TEM and electrical diode I-V curves.
Fig. 4.25 Raman analysis for as-implanted Ge and laser annealed Ge
SIMS analysis for as implanted and laser annealing of plasma doped junctions is discussed
in Fig. 4.20 (a), (b). Spreading Resistance profiling (SRP) was performed for various n-type
dopants in Ge, all of which exhibited dopant activation beyond 1020 cm-3. One thing to note is
the high laser flounce used in this experiment because of the limitation of SRP, which works
well only for junction depths beyond 80nm.
For Sb ion implanted and laser annealed junctions, Fig. 4.27 shows the n+/p junction I-V
characteristics with Ion/Ioff > 105. The leakage current density (JR) is 7x10-4 A/cm2 at -0.5 V
and the ideality factor (η) of the diode is 1.15. This demonstrates low defect density in the n+/p
100 200 300 400 500Wavenumber (cm-1)
Inte
nsity
(arb
. uni
ts)
a-Gec-Ge Sb - Ion
Implanted
c-Ge
After LTP
72
junction. The value of JR is close to the theoretically calculated [34] value of 3x10-4 A/cm2.
0 50 1001016
1017
1018
1019
1020
Depth (nm)
Con
cent
ratio
n (c
m-3
)
P:P3I As:P3I
Sb B:P3I
SRP profiles
Post LTP0.7 Jcm-2
Fig. 4.26 Spreading resistance profiling (SRP) for estimating active dopant concentration
The low JR and ideality factor corroborate the Raman crystallinity analysis and TEM
analysis discussed before.
-0.3 0.0 0.3 0.6 0.910-6
10-4
10-2
100
102
Junction Voltage (V)Junc
tion
Cur
rent
(A/c
m2 )
η = 1.18
>105
n+/ p Diode
Substrate doping ~ 0.1Ω - cm
Fig. 4.27 n+ (Sb doped)/p diode I-V characteristic for the laser annealed diode.
73
-0.3 0.0 0.3 0.6 0.910-11
10-8
10-5
10-2
101
233K
185K
258K273K293K323K
Junction Voltage (V)
Junc
tion
Cur
rent
(A/c
m2 ) Measurement
Temperature
Fig. 4.28 Measurement temperature dependent n+/p diode I-V characteristics.
In order to investigate the carrier conduction mechanism, the temperature dependence of the
diode I-V characteristics are measured as shown in Fig. 4.28. As the measurement temperature
is reduced, the leakage current density decreases. From the reverse leakage current vs.
measurement temperature, the activation energy (Ea) is estimated from the slope of the graph
(Fig. 4.29). This value (~0.36 eV) corresponds to half the band gap of Ge, suggesting that
recombination-generation (R-G) current is dominant for the diodes. Defect assisted tunneling
has been suggested as a possible conduction mechanism for n+/p Ge diodes fabricated using
conventional mono-ion-implantation combined with RTA [35], where Ea value was 0.15 –
0.26 eV, which is smaller than half the band gap of Ge.
0.003 0.004 0.005-20
-16
-12
-8
-4
ln (J
R)
1/T (K-1)
Ea ~ 0.36 eV
Fig. 4.29 Temperature variation of Leakage current density for n+/p diodes biased at -0.5 V
74
Subsequent to the n+/p diode analysis, the contact resistance for the metal-n+ junction was
evaluated using the linear transfer length method (TLM) structures [36] depicted in Fig. 4.30.
Fig. 4.30. Linear transfer length method (TLM) structure for computation of contact
resistivity.
The resistance of the structures depends on the size of the metal pads (brown in color) and
the distance between the individual metal pads (5, 10, 20, 40 micrometer). The green region is
oxide passivated n+ germanium layer. The metal pads were Ti/Al in our case. The resistance
measured (using I-V analysis) between two adjacent pads is plotted against the distance
between the pads. The y-intercept provides the contact resistance (ρc) and the slope of the line
provides the sheet resistance (ρs). The symmetric linearity of the contact I-V plots confirms
the ohmic behavior of the metal-n+ contact [37]. The contact resistance estimated using the
TLM method is ~7 X 10-7 Ω-cm2. These values are significantly lower than the contact
resistance values ~ 10-4 Ω-cm2 reported in [38] where the dopant activation was less than 1 x
1019 cm-3. Other reports with dopant activation of ~5x1019 cm-3 [39] provided contact
resistance on the order of 10-6 Ω-cm2. The gradual reduction of contact resistance for metal-n+
Ge contacts is attributed to the enhancement of active n+ dopant concentration.
Fig. 4.31 Circular transfer length method (TLM) structure for computation of contact
resistivity.
75
Further reduction of contact resistance may be possible by tighter process control during
metal deposition, engineering the metal layers, and/or using a germanide inter-layer between
metal and semiconductor. The contact resistance values were also verified using a self
isolating circular transfer length method (c-TLM) structure as shown in Fig. 4.31 [40]. The
contact resistance values are plotted and benchmarked with literature in Fig. 4.32.
0 10 20 30 400
50
100
150
200
250
This work, ρc ~ 7x10- 7Ω-cm2
Res
ista
nce
(Ω)
Contact Spacing (μm)
Ref [38]
TLM Contact Structure
with isolation
10-6
10-5
10-4
10-3
2.5 ordersreduction in ρc
This workCon
tact
Res
istiv
ity (Ω
- cm
2 )Ref [38]
Fig. 4.32. Contact resistance measurement results using TLM structure.
After confirming the diode and contact resistivity for the laser annealed n+ Ge, the next step
is to integrate it in a MOSFET process flow. The goal is to anneal or “melt” the source/drain
region without affecting the gate dielectric region. To achieve this goal, aluminum metal gate
is used as a reflector material on the gate. The reflectance properties for different metals are
shown in Fig. 4.33 [41]. Aluminum provides us with the highest reflectance for the laser
wavelength at 532 nm. In addition to the reflectance properties, Al has a low work function
which works very well for an n-MOSFET with low Vt design requirement.
Fig. 4.33 Reflectance properties of various metals. Al provides high reflectance across
different wavelengths.
76
Using bright field imaging, the impact of laser on the aluminum pad was observed. The
100nm aluminum pad was able to withstand single pulse laser energy. No visible degradation
is observed. This is shown in Fig. 4.34
Al
Gate
D S
Fig. 4.34 Al gate pad with a 5u wide Al line running over the gate dielectric on a MOSFET
structure. The source (S) and drain (D) are labeled.
The design scheme for laser thermal processing for a long channel MOSFET is illustrated in
Fig. 4.35
Fig. 4.35 Design scheme of integration of laser annealing with MOSFET process.
Laser thermal processing was carried out for a MOSFET. I-V characteristics are measured.
The implant energy for Sb ion implantation for source/drain was 40 keV, hence the annealing
threshold is at 0.4 J-cm-2. Differences in I-V characteristics are seen for low laser fluence of
Al Gate
Oxide
Germanium Substrate
Source Drain
77
0.3 J-cm-2 and 0.5 J-cm-2. The un-optimized low laser fluence shows a discrepancy between
the drain and source currents in the off-state of the transistor. This is due to the defects
remaining in the implanted region which contribute to high diode leakage as shown in the
TEM and diode I-V characteristics before. The optimized laser fluence provides overlapping
drain and source current characteristics.
-0.5 0.0 0.5 1.0
10-9
10-8
Vgate (V)
Nsub> 30 ohm-cm, L = 100μ
Laser Fluence = 0.3 J/cm2
Drain Current Source Current
Vds = 10mV
I drai
n, I so
urce
(A/μ
m)
Idoff > Isoff
Fig. 4.36 MOSFET I-V characteristics with an optimized laser fluence of 0.3 J-cm-2
-0.5 0.0 0.5 1.0 1.5 2.010-9
10-8
10-7
10-6
10-5
I drai
n, I so
urce
(A/μ
m)
Vgate (V)
Drain Current Source Current
Nsub> 30 ohm-cm, L = 20μ m
Laser Fluence = 0.5 J/cm2
Vds = 1V
Fig. 4.37 MOSFET I-V characteristics with an optimized laser fluence of 0.5 J-cm-2
78
Performance projections for the sub-22nm ITRS technology node was done based on the
contact resistance numbers computed for n+ Ge. Ballistic transport was assumed along with
design parameters from the ITRS latest guidelines. We observe more than two orders of
improvement in Idsat when we transition from contact resistivity of ~10-4 to ~10-7 as shown in
Fig. 4.38. Further improvement in drive current is expected by reduction of contact resistance.
I-V curves for 0 contact resistance are plotted for reference.
0.0 0.2 0.4 0.6 0.8
10-6
10-3
100
Vgate (V)
I drai
n (A
/μm
)
Ge NFET - Tox = 0.5nm
Vdd = 0.8 V, Na = 1018 cm-3
ρC = 3x10- 4 Ω-cm2 ρC = 7x10- 7 Ω-cm2
ρC = 0
> 102 enhancement
Fig. 4.38 Performance projections for ITRS HP 22nm technology node
4.8 Conclusion
Junction engineering for Ge NMOSFET source/drain is discussed. Ultra shallow n-type
junctions are demonstrated using plasma immersion ion implantation. High dopant activation
and defect annealing of plasma doped junctions and antimony ion implanted junctions are
discussed using laser annealing. Theoretical calculations are performed using the thermo-
optical heat constants of Ge. Material analysis is performed using SIMS, SRP, Raman and
TEM. Electrical analysis and defect characterization is performed using electrical diode I-V
analysis. Laser annealing integration based process integration in a MOSFET process flow is
discussed along with effect of laser fluence on the MOSFET I-V characteristics.
79
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CHAPTER 5: Conclusion & future work
5.1 Conclusion
This work contributes to addressing issues related to surface passivation of devices which
would be used in the future technology node (3D or high mobility substrates) and the
source/drain junction engineering.
In the first part, radical oxidation is introduced as a technique for surface passivation of 3D
vertical gate all around (GAA) MOSFET structure. Radical oxidation provides substrate
orientation independent growth rate of low Dit oxides. This technique is used to provide
conformal and high quality oxidation for GAA MOSFET structure. Using TEM micrographs,
conformal oxidation of silicon pillar structures using O* radicals is demonstrated as compared
to thermal oxidation which is driven by molecular oxygen species. Superior electrical
characteristics, consisting of higher drive current, lower gate leakage and higher gate dielectric
breakdown voltage compared to thermal oxidation is observed for radical oxidation on GAA
MOSFET structures.
In the second part, radical oxidation is applied to n-type planar germanium MOS devices to
grow low Dit (~ 2 x 1011 cm-2eV-1) GeO2 for Ge (111), (110) and Ge (100) substrates. Mobility
and drive current enhancement are observed with ultra-thin (~1nm) GeO2 for high-k/Ge MOS
gate stacks.
In the last part, junction engineering for Ge N-MOSFETs is discussed. Ultra shallow junctions
are demonstrated using plasma immersion ion implantation and ion implantation of Sb
dopants. Laser annealing is used for high n-type dopant activation and annihilation of
extensive damage during Sb ion implantation in Ge. Other than analyzing the junctions using
Raman, TEM, SIMS and SRP, high performance diodes along with MOSFET integration with
laser annealing is also discussed. Finally, the performance enhancement in ITRS 22nm HP is
predicted and sufficiently high drive current is achievable in Ge NMOSFETs with reduced
contact resistance
84
5.2 Possible future work
Through this work basic break-through concepts were proposed and demonstrated, however
there is significant room for pursuing fundamental physics in detail and optimize each
technology.
5.2.1 Surface passivation of three dimensional and planar Ge susbtrates
1. The advantage of radical oxidation must be shown for ultra-thin fully depleted
structures (fins or pillars). Stress effects of radical oxidation and thermal oxidation
need to be clearly understood and correlated to electrical properties of MOS devices.
2. Fundamental experiments and ab-intio modeling of radical oxidation is required.
Isotope studies and electron spin resonance are needed for clearer understanding of
the role of O* in radical oxidation and its passivation of SiO2/Si and GeO2/Ge
interface.
3. EOT scaling studies of high-k (k > 15) directly on Ge or using an ultra-thin GeO2
interfacial layer needs to be analyzed in further detail.
4. Correlation of GeO2 interfacial layer thickness with carrier mobility and Dit in Ge
MOSFETs is required.
5. Correlation of N incorporation in GeO2 to produce GeOxNy and its effect on BTI is
required
6. Understanding the effect of anneals (FGA, O2, N2, D2, Fluorine) is required for
improving the Ge MOS interface
5.2.2 Source/Drain junction engineering of Ge MOS devices
1. Further reduction of contact resistance is required in order to meet the contact
resistance benchmark (less than 10-8 ohm-cm2) for sub-22nm HP ITRS technology
node. With regards to this, following techniques may be required,
a. Higher dopant activation (using high implant dose combined with laser anneal
or other techniques)
b. Germanides
c. Alternate low work function metal contacts
85
86
2. Efficacy of sub-melt laser anneal needs to be explored in annealing implant damage
and providing high dopant activation
3. Thermal stability of high dopant activation in germanium needs to be assessed.
