ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES
Consulting Editor: Mohammed Ismail. Ohio State University Titles in Series: IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANCEIVERS
Chen, Sao-Jie, Hsieh, Yong-Hsiang ISBN-10: 1-4020-5082-8
LOW-FREQUENCY NOISE IN ADVANCED MOS DEVICES Haartman, Martin v., Östling, Mikael ISBN-10: 1-4020-5909-4
THE GM/ID DESIGN METHODOLOGY FOR CMOS ANALOG LOW POWER INTEGRATED CIRCUITS Jespers, Paul G.A. ISBN-10: 0-387-47100-6
PRECISION TEMPERATURE SENSORS IN CMOS TECHNOLOGY Pertijs, Michiel A.P., Huijsing, Johan H. ISBN-10: 1-4020-5257-X
CMOS CURRENT-MODE CIRCUITS FOR DATA COMMUNICATIONS Yuan, Fei ISBN: 0-387-29758-8
RF POWER AMPLIFIERS FOR MOBILE COMMUNICATIONS Reynaert, Patrick, Steyaert, Michiel ISBN: 1-4020-5116-6 IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANCEIVERS Chen, Sao-Jie, Hsieh, Yong-Hsiang ISBN: 1-4020-5082-8 ADVANCED DESIGN TECHNIQUES FOR RF POWER AMPLIFIERS Rudiakova, A.N., Krizhanovski, V. ISBN 1-4020-4638-3 CMOS CASCADE SIGMA-DELTA MODULATORS FOR SENSORS AND TELECOM
del Río, R., Medeiro, F., Pérez-Verdú, B., de la Rosa, J.M., Rodríguez-Vázquez, A. ISBN 1-4020-4775-4
Philips, K., van Roermund, A.H.M. Vol. 874, ISBN 1-4020-4679-0
CALIBRATION TECHNIQUES IN NYQUIST A/D CONVERTERS van der Ploeg, H., Nauta, B. Vol. 873, ISBN 1-4020-4634-0
ADAPTIVE TECHNIQUES FOR MIXED SIGNAL SYSTEM ON CHIP Fayed, A., Ismail, M. Vol. 872, ISBN 0-387-32154-3
WIDE-BANDWIDTH HIGH-DYNAMIC RANGE D/A CONVERTERS Doris, Konstantinos, van Roermund, Arthur, Leenaerts, Domine Vol. 871 ISBN: 0-387-30415-0
METHODOLOGY FOR THE DIGITAL CALIBRATION OF ANALOG CIRCUITS AND SYSTEMS: WITH CASE STUDIES
Pastre, Marc, Kayal, Maher Vol. 870, ISBN: 1-4020-4252-3
HIGH-SPEED PHOTODIODES IN STANDARD CMOS TECHNOLOGY Radovanovic, Sasa, Annema, Anne-Johan, Nauta, Bram Vol. 869, ISBN: 0-387-28591-1
LOW-POWER LOW-VOLTAGE SIGMA-DELTA MODULATORS IN NANOMETER CMOS Yao, Libin, Steyaert, Michiel, Sansen, Willy Vol. 868, ISBN: 1-4020-4139-X
DESIGN OF VERY HIGH-FREQUENCY MULTIRATE SWITCHED-CAPACITOR CIRCUITS U, Seng Pan, Martins, Rui Paulo, Epifânio da Franca, José Vol. 867, ISBN: 0-387-26121-4
DYNAMIC CHARACTERISATION OF ANALOGUE-TO-DIGITAL CONVERTERS Dallet, Dominique; Machado da Silva, José (Eds.) Vol. 860, ISBN: 0-387-25902-3
ANALOG DESIGN ESSENTIALS Sansen, Willy Vol. 859, ISBN: 0-387-25746-2
SIGMA DELTA A/D CONVERSION FOR SIGNAL CONDITIONING
Q QPatrick J. uinn, Arthur H.M. van Roermund ISBN: 978-1-4020-6257-5
SWITCHED-CAPACITOR TECHNIQUES FOR HIGH-ACCURACY FILTER AND ADC DESIGN
and
By
PATRICK J. QUINN
ARTHUR H.M. VAN ROERMUNDTechnical University of Eindhoven,The Netherlands
Switched-Capacitor Techniques forHigh-Accuracy Filter and ADC Design
Xilinx, Dublin, Ireland
A C.I.P. Catalogue record for this book is available from the Library of Congress.
Published by Springer,
P.O. Box 17, 3300 AA Dordrecht, The Netherlands.
www.springer.com
Printed on acid-free paper
All Rights Reserved
No part of this work may be reproduced, stored in a retrieval system, or transmitted
in any form or by any means, electronic, mechanical, photocopying, microfilming, recording
or otherwise, without written permission from the Publisher, with the exception
of any material supplied specifically for the purpose of being entered
and executed on a computer system, for exclusive use by the purchaser of the work.
© 2007 Springer
ISBN 978-1-4020-6257-5 (HB)
ISBN 978-1-4020-6258-2 (e-book)
ABSTRACTAbstract
In this book, switched-capacitor (SC) techniques are proposed which allow the attainment of
higher intrinsic analogue accuracies than previously possible in such application areas as
analogue filter and analogue-to-digital converter (ADC) design. The design philosophy is to
create the required functionality without relying on trimming or digital calibration means but
instead to develop methods which have reduced dependence on both component matching
(especially capacitor matching) and parasitic effects (especially parasitic capacitance).
At a system level, orthogonal design procedures are employed which ensure that
artefacts due to expected circuit imperfections are avoided in the system transfer function. For
instance, in SC filter design, orthogonal-hardware-modulation helps alleviate the effects of N-
path mismatch through the introduction of an extra degree of freedom, where the number of
hardware paths N (hardware modulation) is decoupled from the functional modulation factor
n, as introduced by the transformation . In algorithmic ADC design, both cyclic and
pipelined, conventional techniques make use of multiplying digital-to-analogue converters (or
MDACs) which require SC circuits with accurate capacitor ratios to implement accurate signal
multiplication. On the other hand, in this book, the ADC function is decomposed into the
simple sub-functions of signal addition and level shifting which can be implemented using SC
techniques which don’t rely on accurate capacitor ratios.
At circuit level, delta-charge flow techniques are employed to realize SC circuits
with more accurate transfers than their conventional charge-transfer (QT) counterparts. Unlike
QT SC circuits, SC circuits do not require signal charge transfer from capacitor to capaci-
tor via the amplifier virtual earth node. Instead, only a delta charge flows in the virtual
earth node due to the presence of parasitic capacitors at the amplifier input terminals. In SC fil-
ter design, delta-charge-redistribution is a means for the accurate implementation of
filter transfer functions using passive charge redistribution between capacitors in the feedback
path of an amplifier, instead of active charge transfer between capacitors through the active
intervention of an amplifier in QT SC filters. In ADC design, a highly accurate method (C+C)
for the stacking of capacitor voltages is proposed which uses a floating-hold-buffer for imple-
mentation. The accuracy of signal addition is practically insensitive to the matching and linear-
ity of the signal capacitors as well as the presence of parasitic terminal capacitance.
A number of other innovative circuit techniques have been included in the book, such as:
a versatile accurate track-and-hold (T&H) which is re-programmable for unipolar, bipolar and
nz zÆ
( )-Qd
-QdQd
( )-QRd
vii
Abstract
differential modes; clock-skew insensitive sampling; a common-mode-feedback circuit which
significantly boosts the common-mode rejection ratio of single-ended amplifiers; high-effi-
ciency dual-input transconductance amplifiers which make use of the level shift properties of
switched capacitors; a low-reference dynamic comparator.
The validity of the concepts developed and analyzed in the book has been demonstrated
in practice with the design of CMOS SC bandpass filters and algorithmic ADC stages (both
cyclic and pipelined). The intrinsic accuracies achieved go beyond those achieved with previ-
ous state-of-the-art solutions with a consequent reduction in power consumption for the same
speed applications. For example, a 10.7MHz radio IF selectivity filter integrated in standard
CMOS, employing the proposed methods, achieves an accuracy greater than ceramic filters.
Another example is an ADC with better than 12-bit intrinsic performance, albeit capacitors
with only 9-bits matching accuracy were used in the realization. The ADC architecture is also
very robust and has proven itself in an embedded digital VLSI application in the very newest
65nm CMOS. The power consumptions and silicon areas of the solutions proposed here are
lower than other known solutions from the literature.
viii
CONTENTSContents
1Abstract
3Symbols and Abbreviations
1Chapter 1: Introduction 11.1 Cost-Performance Trade-offs in IC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Modern IC Design Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.1 Digital IC Design Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.2 Analogue IC Design Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.3 Test Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.4 Process and Design Work-Arounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Switched Capacitors for Analogue Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Key Points for High Performance SC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Scope of Book. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6 Book Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2Chapter 2: Key Concepts for Accurate SC Design 9
2.1 Orthogonal Design Procedures in Filter and ADC Realizations . . . . . . . . . . . . . . . 10
2.2 Delta Charge Flow SC Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 The Sample-And-Hold Stage: Voltage Buffer . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2 The Delta-Charge-Redistribution Stage: Voltage Down-Scaler . . . . . . . . . . 13
2.2.3 C+C Concept: Voltage Up-Scaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 The Floating-Hold-Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3Chapter 3: SC Amplifier Design at Black-Box Level 17
3.1 Amplifier Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ix
vii
xv
Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvAbbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x vii
Contents
3.2 The Settling Error Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1 Static Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.2 Dynamic Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Design Procedure for Optimized Settling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.1 Single-Ended or Fully-Differential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.2 Capacitor Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.3 OTA Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.4 Choice of Von . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.4.1 OTA Transconductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.4.2 Matching Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.4.3 Influence of Channel Mobility Factor . . . . . . . . . . . . . . . . . . . . . . . 28
3.3.4.4 Choice of Gate Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.5 Minimum Settling Time Constant and Bias Current . . . . . . . . . . . . . . . . . . 29
3.4 OTA Slewing Requirement in SC Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4.1 The Slew Rate Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4.2 Minimum OTA Tail Current for No Slewing . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.3 Calculation of Slew Time, tslew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4.4 Dynamic Settling Error including OTA Slewing . . . . . . . . . . . . . . . . . . . . . 35
3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4Chapter 4: Amplifier Architectures for SC Applications 37
4.1 Review of Amplifier Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.1 Primary OTA Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.1.1 Telescopic OTA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.1.2 Current Mirror OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.1.3 Folded OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.1.4 General Conclusions for the Three Primary OTA Stages . . . . . . . . 42
4.1.2 OTA Cascade Stages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1.2.1 Pre-buffer Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1.2.2 Pre-gain Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.1.2.3 Miller Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1.2.4 Ahuja Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2 The Dual-Input Telescopic OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2.1 The SC Single-Input Telescopic OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2.2 SC DITO Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2.3 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2.4 Amplifier Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2.5 Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.3 Cascode Frequency Response Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3.1 The Effect of Cascoding on the Closed-Loop Settling Response. . . . . . . . . 55
4.3.2 Low Frequency Miller Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.3.3 Neutralization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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Contents
4.4 Boosting the gm of a Cascode Stage using Active Feedback . . . . . . . . . . . . . . . . . . 60
4.4.1 The RGC with High Frequency Design Considerations . . . . . . . . . . . . . . 60
4.4.2 Reducing Low Frequency Miller Multiplication . . . . . . . . . . . . . . . . . . . . . 63
4.5 Low Voltage High Frequency RGC Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.5.1 Suitability of RGCs for Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.5.2 LV RGC using Level Shift Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.5.3 LV RGC using Folded Cascode Voltage Sensing. . . . . . . . . . . . . . . . . . . . . 65
4.5.4 LV RGC using Dynamic Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.6 OTA DC Gain Improvement using Partial Positive Feedback . . . . . . . . . . . . . . . . . 67
4.6.1 OTA Design Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.6.2 Circuit Implementation of Partial Positive Feedback . . . . . . . . . . . . . . . . . 69
4.7 Optimization of SC Settling Response with Inclusion of Feedback Loop Switches 70
4.7.1 Effect on Settling of Switch Resistance in OTA Feedback Loop . . . . . . . . . 71
4.7.2 Switch Design Strategy for Speed-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.8 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5Chapter 5: Low-Sensitivity SC BPF Concepts 77
5.1 Sensitivity comparison of SC and CT Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.2 BPF Function Including Hardware Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.3 SC BPF Based on Modified N-Path Design Technique . . . . . . . . . . . . . . . . . . . . . . 81
5.3.1 High-Q BPF Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.2 N-Path Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.3 Modified N-Path Technique using Orthogonal Hardware Modulation. . . . . 82
5.4 Delta Charge Redistribution (δ-QR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.4.1 δ-QR for Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.4.2 δ-QR vs. QT SC Integrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.5 δ-QR N-path SC BPFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.5.1 QT SC BPF Via State-Of-The-Art Biquad . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.5.2 Hybrid N-Path SC BPF (QT/δ-QR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.5.5 Performance Comparison of N-path SC BPF Stages . . . . . . . . . . . . . . . . . 102
5.6 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6Chapter 6: High-Accuracy δ-QR SC BPF Design and Measurements 107
6.1 SC Video BPF - the TV Cloche Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.1.1 System Level Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.1.2 Design of SC Cloche Filter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.1.2.1 Filter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.1.2.2 SC BPF Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.1.2.3 Common-Mode Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.1.2.4 Chip Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
xi
5.5.3 δ-QR Type I N-path SC BPF (δ-QR-I) . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.5.4 δ-QR Type II N-path SC BPF (δ-QR-II) . . . . . . . . . . . . . . . . . . . . . . . . . 99. .
.
Contents
6.1.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.2 10.7MHz SC Radio IF BPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.2.1 System Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.2.2 Design of Radio IF Filter Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.2.2.1 SC Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.2.2.2 Selectable Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.2.2.3 Track-and-Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.2.2.4 Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.2.2.5 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.2.2.6 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.2.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.4 Appendix: Bandwidth Shrinkage of Cascaded Filter Stages . . . . . . . . . . . . . . . . . 133
7Chapter 7: ADC Design at Black-Box Level 1357.1 ADC Black Box Representation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.2 Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.2.1 Static Error Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.2.1.1 Offset and Gain Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.2.1.2 Differential Non-linearity (DNL) . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.2.1.3 Integral Non-linearity (INL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.2.2 Dynamic Error Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.2.2.1 Signal-to-Noise Ratio (SNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.2.2.2 Effective Number of Bits (ENOB). . . . . . . . . . . . . . . . . . . . . . . . . 140
7.2.2.3 Total Harmonic Distortion (THD) . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.2.2.4 Spurious Free Dynamic Range (SFDR). . . . . . . . . . . . . . . . . . . . . 140
7.2.2.5 Intermodulation Distortion (IMD) . . . . . . . . . . . . . . . . . . . . . . . . . 141
7.3 Anti-Aliasing Pre-Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
7.4 Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
7.4.1 Sampling Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7.4.2 Sample Clock Phase Noise Related to Allowable Sampling Jitter . . . . . . . 146
7.4.3 Sample Clock Noise Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.5 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.5.1 Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.5.1.1 Uniform coding model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.5.1.2 Long and short coding model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
7.5.1.3 Signal-to-Quantization Noise Ratios . . . . . . . . . . . . . . . . . . . . . . . 152
7.5.2 Quantizer Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
7.6 Effective Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7.7 ADC Conversion Efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
7.7.1 Minimum SNR Limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
7.7.2 Minimum Power Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
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7.7.2.1 Minimum Theoretical Power Limit . . . . . . . . . . . . . . . . . . . . . . . . 162
7.7.2.2 Minimum Practical Power Limit for Class A Operation . . . . . . . . 162
7.7.3 ADC Figures of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
7.8 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
8Chapter 8: Design Criteria for Cyclic and Pipelined ADCs 1658.1 Operation of Cyclic and Pipelined ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
8.1.1 The ADC Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
8.1.2 Digital Output Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.2 Accuracy Limitations of Cyclic/Pipelined ADCs. . . . . . . . . . . . . . . . . . . . . . . . . . 170
8.2.1 Lumped Error Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
8.2.2 Limitations on Static Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
8.2.2.1 Offset Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
8.2.2.2 Capacitor Mismatch Gain Errors . . . . . . . . . . . . . . . . . . . . . . . . . . 173
8.2.2.3 Amplifier Gain Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
8.2.3 Limitations on Dynamic Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
8.2.3.1 Linear and Non-linear Settling Constraints . . . . . . . . . . . . . . . . . . 179
8.2.3.2 Thermal Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
8.3 Pipelined ADC Specific Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
8.3.1 Design Optimization of Multi-bit Input Stage . . . . . . . . . . . . . . . . . . . . . . 185
8.3.2 Design Optimization of Scaled Pipelined ADCs . . . . . . . . . . . . . . . . . . . . 188
8.3.3 Estimation of Static Power Consumption of Pipelined ADCs . . . . . . . . . . 190
8.4 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
9Chapter 9: Capacitor Matching Insensitive High-Resolution Low-Power
ADC Concept 193
9.1 The ADC Algorithm Re-visited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
9.2 Review of SC Concepts for Analogue Addition. . . . . . . . . . . . . . . . . . . . . . . . . . . 194
9.3 The Floating-Hold-Buffer for Accurate Analogue Addition . . . . . . . . . . . . . . . . . 195
9.4 Implementation of C+C ADC Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
9.5 Practical Performance Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
9.6 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
10Chapter 10: High-Accuracy ADC Design and Measurements 20310.1 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
10.1.1 Application Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
10.1.2 ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
10.1.3 Flexible ADC Sampling Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
10.1.3.1 Unipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
10.1.3.2 Bipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
10.1.3.3 Fully differential mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
10.2 Proposed Reconfigurable Track-and-Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
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10.2.1 The T&H in Unipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
10.2.2 The T&H in Bipolar and Differential Modes . . . . . . . . . . . . . . . . . . . . . . 210
10.2.3 T&H Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
10.3 Proposed Cyclic ADC based on New Concept . . . . . . . . . . . . . . . . . . . . . . . . . 211
10.4 Proposed Single-ended OTA with High CMRR . . . . . . . . . . . . . . . . . . . . . . . . . 214
10.4.1 The CMFB Requirement in Single-ended OTAs . . . . . . . . . . . . . . . . . . . 214
10.4.2 A New Current CMFB for the Single-ended Current Mirror OTA . . . . . 216
10.4.3 Influence of Differential Transistor Mismatch on the OTA CMRR . . . . 219
10.4.4 Experimental Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
10.5 Low-Reference Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
10.6 Cyclic ADC Fabrication and Measurement Results . . . . . . . . . . . . . . . . . . . . . 222
10.7 Pipelined ADC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
10.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
11Main Conclusions 231
12Bibliography 233
13Index 241
xiv
SYMBOLS AND ABBREVIATIONSSymbols and Abbreviations
Symbols
A0 Amplifier DC gain
Bx Spectral bandwidth of x, where x is RF, IF, or ch (channel)
Cfb OTA external feedback capacitance
Cin OTA external input capacitance
CL OTA external load capacitance
Permanently connected amplifier external load capacitance including parasitics
Switching amplifier load capacitance
CLeff Effective load capacitance the amplifier sees at its output
Cox Gate capacitance per unit gate area
fs Sampling frequency
fsig Signal frequency
gm The small signal transconductance defined at the bias current
L Effective gate length of MOST
m Discrete time variable
Q Quality factor
QT Charge transfer (SC circuit), where signal charge is transferred completely from
one capacitor to the other through the active intervention of an amplifier
r Pole radius in z-domain
s Laplace frequency variable
S Scaling factor
T Sampling period
tslew Slewing time
VREF Reference voltage
VDD Supply voltage
Von The MOST “on” voltage, or gate over-drive voltage, defined as VGS - VT, required
to keep the MOST biased at the edge of saturation with all voltages and currents
fixed at their DC bias levels
Vds(sat) Defined as Vgs - VT, it is the minimum instantaneous drain-source voltage required
fixLC
swLC
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Symbols and Abbreviations
to ensure the MOST stays in saturation
Vmargin Extra voltage safety margin above Von to ensure MOST stays biased in saturation -
generally,
vsat Maximum charge carrier velocity in silicon ( m s-1)
Threshold voltages for PMOSTs(NMOSTs) - note is assumed to be positive
W Effective gate width of MOST
XY DC bias value of x, with y the descriptor - x is generally a current, i, or a voltage, v
xy AC value of x with y a descriptor
Xy Total instantaneous value of x, where Xy = XY + xy
z z-domain frequency variable
βfb Closed loop amplifier feedback factor
δ-Q Delta charge flow technique referring to a new class of SC circuit
δ-QR Delta charge redistribution
∆ Quantization step size of a data converter (analogue equivalent of 1 LSB)
εs Static settling error resulting mainly from finite amplifier DC gain
εd Dynamic settling error resulting mainly from finite amplifier bandwidth
ε Total combined settling error of a SC circuit at the end of a clock period
ϕx Defines a clock phase x
γ Attenuation factor due to capacitive division from the signal input of a SC circuit
to the differential input of the OTA
κ Ratio of OTA output parasitic capacitance to its input parasitic capacitance
µeff Effective inversion layer charge carrier mobility, including the effect of vertical
field mobility degradation
µ0 Inversion layer charge carrier mobility, when low vertical field (typically, 5x1010
µm2V-1s-1)
θ Process dependent factor inversely proportional to the oxide thickness (typically,
24 /dox V-1)
σ(∆X) Standard deviation of ∆X
τ Time constant of linear step response
ωcl Closed loop bandwidth in radians/s
ωol Open loop bandwidth in radians/s
ωT Radial transition frequency
ωu Unity gain radial frequency, where the gain of the amplifier is reduced to 1
In parallel with (used for parallel combinations of resistors or capacitors)
( ) on marg inds satV V V< +1.1 10
5×
( )p nT TV VPTV
Ao
||
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Symbols and Abbreviations
Abbreviations
ADC Analogue-to-digital converter
ASD Analogue sampled data
ASIC Application specific integrated circuit
ATE Automatic test equipment
BIST Built-in-self-test
BPF Bandpass filter
CAD Computer aided design
CMFB Common mode feedback
CMOS Complementary metal oxide semiconductor
CMRR Common mode rejection ratio
DAC Digital-to-analogue converter
DEC Digital error correction
DITO Dual-input telescopic OTA
DNL Differential non-linearity
DS Double sampling
ENOB Effective number of bits
FD Fully differential
FOM Figure of merit
FPGA Field programmable gate array
FS Full scale (of ADC)
GBW Gain-bandwidth (defined in radians per second)
HF High frequency
HPF Highpass filter
IC Integrated circuit
IF Intermediate frequency
IMD Intermodulation distortion
I/O Input/output interface
INL Integral non-linearity
IP Intellectual property (block)
ITRS International Roadmap for Semiconductors
LF Low frequency
LHP Left half s-plane
LHS Left hand side
LPF Lowpass filter
LSB Least significant bit
MDAC Multiplying DAC
MOST MOS transistor
MSB Most significant bit
OHM Orthogonal hardware modulation
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Symbols and Abbreviations
OSR Oversampling ratio, fs/fsig
OTA Operational transconductance amplifier
PM Phase margin (in degrees)
PSRR Power supply rejection ratio
PVT Process, voltage supply and temperature variations
RF Radio frequency
RGC Regulated cascode - this term is used interchangeably with the term active feed-
back cascode
RHP Right half s-plane
RHS Right hand side
RMS Root mean square
S&H Sample-and-hold
SNR Signal-to-noise ratio
SC Switched-capacitor
SE Single-ended
SEM Scanning electron microscope
SiP System in package
SITO Single-input telescopic OTA
SoC System-on-a-chip
SR Slew rate
SS Single sampling
T&H Track-and-hold
VHF Very high frequencies
VLSI Very large scale integration
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