81 S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) (i) (48 BA) 16 (48 BA) 16 (01001000 1011 1010) 2 Q.1(a) (ii) Function of following IC's IC74138 o 1:8 Demux. IC74139 o Dual 1:4 Demux IC74154 o 1:16 Demux IC74155 o Dual 1:4 Demux Q.1(a) (iii) Fanin Fanin is defined as the number of inputs a gate has propagation delay is defined as time delay between the instant of application of an input pulse and the instant of occurrence of the corresponding output pulse. Q.1(a) (iv) Propagation delay (or speed of operation) The delay times are measured between the 50 % voltage levels of input and output waveforms. There are two delay times t PHL o when output goes from High to Low t PLH o when output goes from Low to High Propagation delay is average of above two delay times. Fanout : This is number of similar gates which can be driven by a gate. High fanout is advantageous because it reduces the need for additional drivers to drive more gates. 4 0100 1000 1011 1010 8 B A Input Output 50 % 50 % t PHL t PLH Vidyalankar mber of inputs a gate has propag of inputs a gate ween the instant of application of an e instant of applicat e of the corresponding output puls of the corresponding out y (or speed of operation) d of operation) The delay times are meas The delay times are meas output waveforms. output waveform There are two dela There a t PHL o o when ou w t PLH o when Propagatio P Fanou This a ala a al dy y yal Output Output % 50 % 50 % t PHL HL ya a
Transcript
81
S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU]
Principles of Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100
Q.1(a) (ii) Function of following IC's IC74138 1:8 Demux. IC74139 Dual 1:4 Demux IC74154 1:16 Demux IC74155 Dual 1:4 Demux
Q.1(a) (iii) Fan in Fan in is defined as the number of inputs a gate has propagation delay is
defined as time delay between the instant of application of an input pulse and the instant of occurrence of the corresponding output pulse.
Q.1(a) (iv) Propagation delay (or speed of operation)
The delay times are measured between the 50 % voltage levels of input and output waveforms.
There are two delay times tPHL when output goes from High to Low tPLH when output goes from Low to High Propagation delay is average of above two delay times. Fanout : This is number of similar gates which can be driven by a gate. High fanout is
advantageous because it reduces the need for additional drivers to drive more gates.
4
0100 1000 1011 1010
8 B A
Input
Output
50 %
50 %
tPHL tPLH
Vidy
alank
armber of inputs a gate has propag of inputs a gate
ween the instant of application of ane instant of applicate of the corresponding output puls of the corresponding out
y (or speed of operation) d of operation)
The delay times are meas The delay times are measoutput waveforms. output waveform
There are two dela There a t PHL when ou w t PLH when Propagatio P
Fanou This
a
alaaaldyyy
alOutputOutput
%
50 % 50 %
tPHL HL yaya
Vidyalankar : S.Y. Diploma PDT
82
Q.1(a) (v) Minterm :
A minterm is a special case product (AND) term. A minterm is a product term that contains all of the input variables (each literal no more than once) make up a Boolean expression.
Maxterm : A maxterm is a special case sum (OR) term. A maxterm is a sum term that
contains all of the input variables (each literal no more than once) that makes a Boolean expression.
Q.1(a) (vi) Circuit diagram of D flip-flop using logic gate
Q.1(a) (vii) The BCD addition discussed so far can be summarized as follows:
Q.1(a) (viii) Difference between EPROM and EEPROM Parameter EPROM EEPROM
1) Technique used for erasing
Exposure to ultraviolet light
A voltage of 20 to 25 volts is applied
2) Selective erasing Not possible. All the locations get erased.
Possible. A particular location only can be erased.
3) Time required for erasing.
Long 10 to 15 min. Short 10 ms.
4) Need to remove PROM from circuit
It is necessary to remove the PROM
Not necessary to remove PROM.
5) Cost Less expensive Very expensive.
i/ps fanout = 3
Q
Q
S
R
D
Clk
Add two BCD Numbers A and B
Answer is correct.No correction
required.
Sum 9, carry = 0 Sum 9, carry = 1 Sum > 9, carry = 0
Add 6 to the sum to get correct answer
Add 6 to the sum to get the correct
answer
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alank
ar
s a product term uct te han once) make up ake up
maxterm is a sum term that m is a sum term tha o more than once) that makes o more than once) that ma
gic gateate
tion discussed so far can be suiscussed so far
Q.1(a) (viii) Difference between 1(a) (viii) Difference be Param
Vid
Vidid1) Techniq) T
erasinViVii2) SelVV3VV
Q
laQQ lllAdd two BCD Numbers A and Bd two BCD Numbers
Answer is correct.Answer is correct.No correction correct
required. red.
yayayaSum Su 99,, carr c y = 0 Sum = 0 9, carr
dyAdd 6 toAdc
Prelim Question Paper Solution
83
Q.1(b) (i) D-Flip Flop from a R-S Flip Flop
Q.1(b) (ii) Consider B2, B1, B0 are binary inputs. D0 D7 are Decimal outputs.
0100 0100y 0110 0110 1011 1011 dy + 110 + 110 0001 dy 0010 001d 0100 0111 Vi
yy00 dd1
9’s c
Prelim Question Paper Solution
85
This situation is known as Race around condition. The Best method to avoid the possibility of Race around condition is to
isolate the outputs and inputs of flip flop. Race around condition can be avoided by providing the clock pulse lasts for
a time inte less than the propagation delay.
Q.2(b) ABC + ABD + ABC + CD + BD
= ABC + ABC + CD + B (D + AD) ( A + A B = A + B)
= ABC + ABC + CD + B (D + A)
= ABC + ABC + CD + BD + BA
= AB (C + 1) + ABC + CD + BD ( 1 + A = 1)
= AB + ABC + CD + BD
= B (A + A C ) + CD + BD ( A + AB = A + B)
= B (A + C ) + CD + BD
= AB + B C + CD + BD
Now consider CD + B is of form AB + AC also we have identify
AB + A C + BC = AB + AC . Thus in above equation A = D, B = C and C = B. Thus value CD + BD remains unchanged if BC is added to it. i.e. CD + BD + BC = CD + BD = AB + B C + CD + BD + BC
= AB + B (C + C ) + CD + BD ( A + A = 1)
= AB + B + CD + BD = B (1 + A) + CD + BD ( 1 + A = 1) = B + CD + BD = B (1 + D ) + CD ( 1 + A = 1) = B + CD ABC + ABD + ABC + CD + BD = B + CD
Q.2(c) Half Subtractor using logic gates
For difference output For the borrow output
For D output For B output Difference D = A B + AB Borrow Bo = AB D = A B
Half Subtractor
A B
D B0 Vidy
alank
ar
B = A + B)
1 + A = 1) A = 1)
( A + A kaABAB = A + B) = A + B)
AB + ACC also we have identify also we have ida
AC . D, B = C and C = B. C and C = B.
mains unchanged if BC is added to mains unchanged if BC is ad CD + + lBDBD
D + BC
+ CD + +
alBDBD (
+ B aD + CD + B B aDD
+ B yD + + D ) + CD + CD
+ CD CD C + ABD + BD +
dydy
ABCA + CD + B + CD + yD = B
) Half Subtractor using logic ga) Half Subtractor using logic g
VVid
Vid
alf VididV
A B
D
Vidyalankar : S.Y. Diploma PDT
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Truth table for Half subtractor
Inputs Outputs A B Difference D
(A B) Borrow B0
0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0
Logic diagram
Q.2(d)
Working :
If Clk = 0 then the flip-flop is disabled. Hence there is no change in output
If Clk = 1 and D = 0 then S= 0 and R = 1. Hence irrespective of the present state the next state is Qn+1= 0 and n 1Q = 1. This is the reset condition.
If Clk = 1 and D = 1 then S= 1 and R = 0. Hence irrespective of the present state the next state is Qn+1= 1 and Qn+1 = 0. This is the set condition.
Vidy
a
Working : Working :
If Clk = 0If C then th
If Clk = 1If Clk anthe next s
nkarararkar
kakakakakak
If Clk
Prelim Question Paper Solution
87
Q.2(e) Subtract using is 1's & 2’s complement (i) 25 17 using 1's complement (25)10 = (11001)2 (17)10 = (10001)2
Step 1: Take is complement of 17. 1001 01110
Step 2: Add 25 to is complement of 17. 1 1 0 0 1 + 0 1 1 1 0 final cy 0 0 1 1 1 As the final cary is ‘I’ add to the final cary and it indicates the result is
Take 2’s complement of 17. s complement of 17 10001 1000 01111 01111
ep 2: Add 25 with 2’s complement p 2: Add 25 with 2’ 1 1 1 1 1 1 + 1 1 0 0 1 1 1 0 0y 1 0 1 0 0 0 1 0 1 0 0
As the final carry As the final carry form. form.
10(25)( 10
(ii) 17 (ii) Vi25 5 i using Step 1: Take
Step
dy0
1
aaar
Vidyalankar : S.Y. Diploma PDT
88
Step 3: Take 1’s complement of result.
10111 1'sComplement
(01000)2 = (8)10
(17)10 (25)10 = (8)10 17 25 using 2’s complement. Step 1 : Take 2’s complement of 25
(25)0 = (11001)2 2's
Complment(00111)2
Step 2 : Add 17 to 2’s complement of 25 1 1 1 1 0 0 0 1 + 0 0 1 1 1 1 1 0 0 0 As the final carry is zero it indicates the result is negative and in its
5) Clock is not used in combinational Logic Circuits
Clock is the main feature of sequential Circuits.
6) INPUTS OUTPUTS
INPUT
The memory element referred to in the sequential circuit is the flip-flop or latch, which are capable of storing binary information. The latch is the basic element of any sequential circuit.
Q.3(b) 3 bit Twisted ring counter
Table represents the mode of operation for 3 bit Johnson counter
TTL) 10) Switching speed Less than TTL Faster than CMOS 11) Power dissipation per
gate PD = 0.1 Mw. Hence used for battery backup applications.
10 mW
12) Speed power product 10.5pJ 100 pJ 13) Dependence of PD on
frequency PD increases with increase in frequency.
PD does not depend on frequency.
14) Fan out Typically 50. 10 15) Unconnected inputs Unused inputs should be
returned to GND or VDD. They should never be left floating.
Inputs can remain floating. The floating inputs are treated as logic 1s.
16) Component density More than TTL since MOSFETs need smaller space while fabricating an IC.
Less than CMOS since BJT needs more space.
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can be RS, T and D Flip D Fliprrkout. arrd serial counting is ounting is
kar
ng time is less. time is lesskaso called as Parallel Counter. d as Parallel CounkankaaanS and TTL families S and TTL families CMOS CMlaln-channel MOSFET and hannel MOSFET
dydy9) Propagation delay 105nropagation delay dyiidy10) Switching speed 0) Switching speed idyViVidy11) Power dissipation per 11) Power dissipa
gate gate
Vidy
ViVid12) Speed power proSpeed
Vid
ViVid
13) Dependence o13) Depenfrequency ViViVi14) Fan out 14) VVVV15) Uncon15) VVV
Prelim Question Paper Solution
91
Parameter CMOS TTL 17) Operating areas MOSFETs are operated as
switches. i.e. in the ohmic region or cut off region.
Transistors are operated in saturation or cut off regions.
18) Power supply voltage Flexible from 3V to 15V. Fixed equal to 5V.
Q.3(e) 1:64 demultiplexer tree using only 1:16 demux
Q.3(f) Master Slave JK Flip Flop, using NAND gates
A B C D
1 : 16
demux
A B C D
A B C D
1 : 16
demux
A B C D
A B C D
1 : 16
demux
A B C D 1 : 16
demux
0
1
15
16 17
31
32
33
47
48
49
63
1 : 4
demux
I/P
Logic O
Enable
Enable
Enable
Enable
input
Enable
Vidy
ala
Master Slave JK Flip Flop, using Slave JK Flip Flop, u
alanaanka
rual to 5V. 5V. rararkar
kakakakanknknknknnkaka
A B C D
16
mux
nka
nkaA B C D
A
1
demnnkkakakanaraaaraakakakakkk
annknknknkanankkkkknkkkka
0
16 kkknknknknknknknnnkanalaEnab
Enable Enab
able ar
Vidyalankar : S.Y. Diploma PDT
92
Master is positive level triggered. But due to the presence of the inverter in the clock line, the slave will respond to the negative level. Hence when the clock = I (positive level) the master is active and the slave is inactive, whereas when clock = 0 (low level) the slave is active and the master is inactive.
Therefore, outputs of master will toggle. So S and R also will be inverted. Clock = 0 : Master inactive, slave active.
Therefore, outputs of the slave will toggle. These changed output are returned back to the master inputs. But since clock = 0, the master is still inactive. So it does not respond to
these changed outputs. This avoids the multiple toggling which leads to the race around condition.
Thus the master slave flip flop will avoid the race around condition.
Q.4(a) Circuit diagram
A B Y = AB 0 0 1
0 1 1
1 0 1
1 1 0 Operation : Case 1: A = 0, B = 0 For this case Q1 works in normal mode and transistors Q2 and Q3 both will be OFF and voltage at Vx point will be VCC and this is sufficient to turn ON Q4 and D1 (because to turn ON Q4 and D1 voltage Vx = VB4 = VBE4 + VD1 = 0.7 + 0.7 = 1.4 V) so Q4 and D1 both will be ON when output V0.
A
B Y = AB
Multi emitter i/p stage Phase Splitter
Totem pole o/p stage
AB
RB1
VB1
VB2
VBC1
VBE2
VBE3
VBE4Q1 Q2
Q3
Q4
D1
RE2
RC2 RC3
IC3
Vx
o/p
VD
VCC
VB4
Vidy
alank
ar
l be inverted. rted.
er inputs. s. So it does not respond to oes not respond to
s to the race around condition. to the race around condi race around condition. around condition.
A dd0 dd
Operation Case 1: For thnd
dydyyyydydyAA
Bdydydyyy
Multi emitter emi/p stage i/p stage Phase SplitterPh
Case 4: A = 1, B = 1 For this case, transistor Q1 works in inverse mode due to this Q2 and Q3 both will be ON and voltage at Vx = VCE2 + VCE2 (sat) + VBE3 = 0.2 + 0.7 = 0.9 V This voltage is not sufficient to turn ON Q4 and D1 because it is less than 1.4 V. So Q4 and D1 both will be OFF and output V0 = VCE3 (sat) = 0.2 V = logic 0.
Transfer Characteristics of TTL NAND gate : Transfer characteristics gives relationship between input given and output appeared. It shows valid region for operating TTL gate. (i) VI < Va : If VI at one or more of the input is less than Va, then Q1 works in
normal mode and transistor Q2 and Q3 both will be turn off and voltage at Vx = VCC due to this transistor Q4 and diode D1 is conduct and output V0 will be
Vo = VCC VBE4 (ON) VD1 = 5 0.7 0.7 Vo = 3.6 V = logic 1
(ii) VI > VC : When VI of all inputs is greater than VC, transistor Q2 and Q3 conduct because Q1 works in inverse mode and voltage at Vx = 0.9 V. This is not sufficient to turn on Q4 and D1, so both will be off and output Vo = VCE3 (sat)
= 0.2 V = logic 0
(iii) Va < VI < VC : This range is the transition range where translation occurs from a logic 1 to logic 0 output.
same as case (I)
V0
VIN
a
b
c
Va 0.7 V
VIL
Vb Vc 1.4 VVIH
0 V
logic 1 VOH = 3.6 V
logic 0 VOL 0.2 V
slope = 1.4
slope = 6.2
Vidy
alank
ar to this Q2 and Q and Q33 both will both will
and D D11 because it is less than 1. because it isut V0 = V VCE3 (sat)CE3 (sat) = 0.2 V = logic 0. = 0.2 V = lo
AND gate : relationship between input givennship between
n for operating TTL gate. perating TTL gate.
or more of the input is less than more of the input is les ransistor Q Q22 and Q and Q33 both will be both
is transistor Qsisto 4 and diode D and diode D1 is con
VCC V VBE4 (ON) (ON) VD1
= 5 0.7 0.7 0.7 0.7 Vo = 3.6 V = logic 1 3.6 V = logic 1
(ii) V) I > Vcondis
yayVV0 0
aogic 1 V 1 VOHO = 3.6 V = 3.6 V
logic 0 Vlogic 0 VOL 0.2 V
Vidyalankar : S.Y. Diploma PDT
94
Assume that all inputs are tied together and VI is increased from 0, then Q1 base current is gradually diverted from the emitter of Q1 to the collector of Q1 due to this Q2 will be conduct. This conduction occurs at VI 0.7 V. i.e. point a on characteristics Q2 is now operating in active region with a gain. From input to collector determined by the ratio RE2 / RC2. Since Q4 remains ON, the output follows the gain characteristics of Q2 and therefore decreases at a slope of 1.6 [point a to b on transfer characteristics]. At point b, the input is high enough to cause Q3 to conduct this conduction effectively reduces the emitter impedance of Q2 and hence increases the gain. So will get steep slope region between points b and c. Q4 turns OFF at point c and output is at logic 0 state.
Parameters :
i) Propagation delay = HL LHP Pt t
2 = 10 nsec.
ii) Power dissipation = 10 mW iii) Fanout :
This is the number of similar gates which can be driven by a gate.
Fanout = min OH OL
1H 1L
I I,
I I =
400 16min ,
40 1.6
= min (10, 10) = 10
iv) Noise Margin High state noise margin
NMH = V0H V1H = 2.4 2.0 = 0.4 V
Low state noise margin NML = V1L V0L = 0.8 0.4 = 0.4 V
Q.4(d) Minimize using K map (i) F = m (0, 3, 5, 6, 9, 10, 12, 15) = A B C D A B C D A B C D A B C D A B C D A B CD A B C D A B C D = A B ( C D C D) A B (C D C D) + AB ( CD CD) A B C D +C D)
re arranging the term = A B ( C D) AB ( C D)
= A B (C D) + (C D)
= C D C D A B A B
take C D X & A B Y
= C D A C D B
= X Y XY
= X Y putting value of X & Y = C D A B
rearranging the term Y = A B C D (ii) F = m ( 0, 1, 2, 3, 11, 12, 14, 15)
00 1 1 1 1
01
11 1 1 1
10 1
CDAB
00 01 11 10
group 1 : Quad AB
group 3 : ABD
group 2 : Quad ACD
00 1 0 1 0
01 0 1 0 1
11 1 0 1 0 10 0 1 0 1
CDAB 00 01 11 10
m0 m1 m2 m3
m4 m5 m7 m6
m12 m13 m15 m14
m8 m9 m11 m10
C D)+C
D)
(C D)C DCC
C D A B A BD A B AC D A B AD A B AC D A B A BD A B A BA BAC D A B AD A B AC D A B AD A B AD A B
A B YYA B
Y XY
yX YXtting value of X & Y ting value of X & Y
=
dy
C D A BC D A BD AD AD A
rearranging the term arranging the Y = Y = dyA B C DCB CCC
(ii) F = (ii) F = m ( 0, 1, 2, 3, 11m ( 0, 1, 2
00
01
Vi
CD CDAB
00 D
nk0 0
1 kknknnnkm6
m m14
mm111 m 10 0
Prelim Question Paper Solution
97
Q.4(e) Truth Table
Q.4(f) Block diagram of 7490 as Decade Counter Operation of IC 7490 Decade Counter
Y = A.B B (ii) The fastest logic family will be the one with the lowest propagation delay. For TTL propagation delay = 10 ns For CMOS propagation delay = 105 ns For ECL propagation delay = 1 ns Thus ECL is the fastest logic family.
Q.5(c)
0123456789
101112131415
1:16 Demux 5 V
f
A B C D
A
BY = (A B) B
A B A B
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alank
araaakakanknknkanananlan will be the one with the lowelay = 10 n
alay = 105 ns
alalay = 1 ns
alaest logic family.
aa
yayaaayayayayaaya
0
34567dyayayayayaaa
Vid1:16 1
Demux D5 V 5 V
nnananaaananaY Y nB))n
Prelim Question Paper Solution
99
Q.5(d) (i) 9 1001 + 4 0100 13 1101 0110 0011
1 (ii) (16)10 (8)10
16 16 8 + 92
+8 108
Neglecting the carry we get, (08)10.
Q.5(e) (i) Differences between Multiplexer and Demultiplexer Multiplexer Demultiplexer
1) It has several inputs in only one output.
It has 1 input and several outputs.
2) In combinational logic design using multiplexers, additional gates are not required.
In combinational logic design using demultiplexer gates are required.
3) They are costly when used for designing multiple output expressions of the same input variables because
They are economical when multiple output expressions of the same input variables are required.
(ii) CMOS invertor :
(10’scomplement of 8)
+VCC
S2
T2 (p-channel)
D2
D1
ID
VO D G Vi
S1
T1 (n-channel)Vidy
alank
arrrarkaka Demultiplexer tiplexer Demultiplexer Demultiplenkne It has 1 input and several ot has 1 input and senka
esign using sing al gates are s are
In combinational logic In combinademultiplexer gates demultiplexeana when used for n used for
iple output ut of the same input same input
because se
They are econoey aremultiple outpmultisame inpusamlaalaya
:
yayadya
dydyidyidyVidy
Vid
Vid
Vid
ViVVVVVement of 8) 8)
yyyyyayayayyayayaya
+VCC
S2ydVVi i dd
Vidyalankar : S.Y. Diploma PDT
100
Q.5(f) Half Adder Half adder is a combinational logic circuit with two inputs and two outputs. It
is the basic buildings block for addition of two “single” bit numbers. This circuit has two outputs namely “carry” and “sum”. The block diagram of half adder is as shown in figure 1(a).
The half adder circuit is designed to add two single bit binary numbers A and B. Hence the truth table of a half adder is shown in figure 1(b)
Karnaugh maps and simplified expressions for outputs: K map for carry and sum outputs are as shown in figures 2(a) and (b)
(a) K-map for sum output (b) K-map for carry output
Fig. 2 Boolean expressions for the sum (S) and carry (C) output are obtained from
the k maps as follows:
S AB AB A B
C AB … (1)
Q.6(a) Comparison TTL, CMOS and ECL logic families
Inputs Outputs A B Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
(b) Truth table (a) Block diagramFig. 1
Vidy
alank
ar
mbers A a A a
essions for outputs: s for outputs: s are as shown in figures 2(a) and hown in figures 2
or sum output (b output Fig. 2 Fig. 2
n expressions for the sum (S) and sions for the sum maps as follows: low
ddy
AB AB A BAB AB A B
C ABB
AB AB AAB AB AAB A
Q.6(a) Comparison (a) Com ParaVVV1) PrVVV
2)
Outputs uts rrr Sum Carry um Carry
araar0 0 0 0 0arkakar
1 1 0 1 0
kakkaka
0 1 0 0 1 0
kakkaka1 1 0 1 1 1 0 1kakkkakakakaka(b) Truth table (b) Truth tabl
Prelim Question Paper Solution
101
Fig. : A 5 bit shift register (7496)
Q.6(b) Features, merits and demerits of ECL family Transistors operate in either cut off or regions. They are not allowed to
operate in saturation. They can switch at very fast speeds. In fact ECL is the fastest logic family. Typically the propagation delay is 1 ns per gate. The logic voltage levels are adjusted to be very close to each other so as to
avoid the transistor saturation. Noise margin is low because the logic levels are close to each other. So ECL
gates are susceptible to noise. Transistor in active region consume more power. So ECL gates consume
more power.
Q.6(c) 5-bit Shift Register
A 5-bit shift register using five master-slave S-R (or J-K) flip-flops is shown in figure. This circuit can be used in any of the four modes.
The operation of this circuit is explained by assuming the 5-bit data 10110. For any other 5-bit data, the operation will be similar to the one explained. Serial Input The data word in the serial form is applied at the serial input after clearing the
flip-flops using the clear line. The preset enable is to be held at 0 so that Pr for every flip-flop is 1. The input and output waveforms are illustrated in above figure (a).
The process of entering the digital word starts with the data input corresponding to the least significant bit (0) at the serial input and first clock pulse.
At the falling edge (T1) of the first clock pulse the output of FF4 (Q4) will be 0 and the outputs of all other flip-flops are 0 since their inputs are 0.
Next, the input corresponding to next bit is applied and, at the falling edge (T2) of the second clock pulse, the flip-flop outputs will be
Q4 = 1 Q3 = Q2 = Q1 = Q0 = 0 Similarly, the input corresponding to each bit is applied till the MSB and the bits
go on shifting from left to right at the falling edge of each clock pulse as illustrated in figure (a). At the end of fifth clock pulse, the outputs of flip-flops are
Vidy
alank
arFig. : A 5 A 55 bit shift register (7496) bit shift registebit hift i
her so as as
ch other. So ECL So EC
ECL gates consume gates consume ya
ter using five maste
ya
uit can be used in
ya this circuit is ex
dya any other 5-bit dat
dydy nput
idy
e data word in the seria
idyp-flops using the clear li
Vidyfor every flip-flop
Vidabove figure (a
Vidhe pro
Vie leaVi VaV NVV
Vidyalankar : S.Y. Diploma PDT
102
Q4 = 1 Q3 = 0 Q2 = 1 Q1 = 1 Q0 = 0 which is the same as the number to be stored.
The number of clock pulses required for entering the data, is the same as the
number of bits. The process of entering the data is also referred to as writing into the register.
The data stored can be retrieved (also referred to as reading) in two ways : serial-out and parallel-out. The data in the serial form is obtained at Q0 when clock pulses are applied.
The number of clock pulses required will be same as the number of bits (five in this case).
In the parallel form, the data is available at Q4 Q3 Q2 Q1 Q0 and clock is not required for reading. In the case of serial output, after the nth clock pulse, for an n-bit word, each flip-flop output is 0. This means that once the data is retrieved the register is empty.
On the other hand, in the case of parallel output, the contents of the register can be read any number of times until new data is stored in the register.
The clock rate may be different for the input data and the output data in case of the serial-in, serial-out shift register. Hence, this method can be used for changing the spacing in time of a binary code which is referred to as buffering.
Fig.(a) : Waveforms of shift register for serial input.
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ayadyae number of clock p
dy
ber of bits. The pro
dy the regist
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e data stored can be re
idyrial-out and parallel-out
Vidyclock pulses are applied
Vid The number of
Vidn this c
Vi In the paViVaVreVV
arrrrarararaaaaaFig.(a) :Fi ( ) WavefW f
Prelim Question Paper Solution
103
Q.6(d) Method of operation of a Single Slope ADC
i) Manual RESET, will reset ramp generator as well as counter. ii) The analog voltage VA has to be positive. Hence the RAMP begins at 0V. iii) Since VAX < VA , the output of the comparator Vc = 1 (HIGH). iv) This will enable CLOCK gate allowing the CLK input, to be applied to the
counter. v) The ramp generator may make use of counter type ADC or simple integrator. vi) As counter receives clock pulses, it will count up; and the RAMP continues
upward. RAMP voltage rises till it reaches to VA input voltage. vii) When the ramp voltage reaches the input analog voltage, the output Vc = 0
(LOW) and it will disable CLOCK gate and counter cease to advance. viii) The negative transition of Vc simultaneously generates a strobe signal in the
CONTROL box that shifts the contents of the three decade counters into the three 4 FF latch circuit.
ix) After the generation of STROBE signal, a reset pulse is generated by the CONTROL box that resets the RAMP and clears the decade counter to 0’s (ZEROS) and another conversion cycle begins.
x) During this time the contents of the previous conversion, are contained in the latches and are displayed on the seven segment display.
Q.6(e) EX-NOR Gate
Symbol Truth Table
Boolean Equations Y A B
=
Output is 1 when even number of inputs are
high or when all the inputs
are low.
Input Output A B Y 0 0 1 0 1 0 1 0 0 1 1 1
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ar ramp generator as well as counte ramp generator as well as
has to be positive. Hence the RAMas to be positive. Hence t output of the comparator Vt of the comparator c = 1 (
CLOCK gate allowing the CLK inpe allowing the C
nerator may make use of counter t may make use of c receives clock pulses, it will cou clock pulses, it
RAMP voltage rises till it reaches voltage rises till it re the ramp voltage reaches the inp voltage reaches
W) and it will disable CLOCK gate W) and it will disable CLOC he negative transition of Vc simulte negative transition CONTROL box that shifts the coTROL box that shifthree 4 FF latch circuit. ee 4 FF latch circuit.
ix) After the generation of STRix) After the generation of SCONTROL box that reseONTROL box that rese(ZEROS) and another c(ZEROS) and a
x) During this time the c During this timlatches and are disches a
Q.6(e) EX-NOR Gate Q.6(e) EX- Symbol Symb
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Vidyalankar : S.Y. Diploma PDT
104
Q.6(f) Two Input TTL NAND Gate A two input TTL NAND gate is shown in figure 1. A and B are the two inputs
while Y is the output terminal of this NAND gate.
Operation In order to understand the operation of this circuit, let us replace transistor Q1
by its equivalent circuit as shown in figure 1. A and B are the input terminals. The input voltages A and B can be either
LOW (zero volts ideally) or HIGH (+ VCC ideally). A and B both LOW If A and B both are connected to ground, then both the B E junctions of
transistor Q1 are forward biased. Hence diodes D1 and D2 in figure 2 will conduct to force the voltage at point
C in figure 2 to 0.7 V. This voltage is insufficient to forward bias base emitter junction of Q2. Hence
Q2 will remain OFF. Therefore its collector voltage VX rises to VCC.
Fig. 2 : Transistor Q1 is replaced by its equivalent.
Fig. 1 : Two input TTL NAND gate.
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and the operation of this circuit, let peration of this cir circuit as shown in figure 1. as shown in figure 1.
he input terminals. The input voltut terminals. The i volts ideally) or HIGH (+ Vally) or HIGH (+ VCC ideall
th LOW and B both are connected to gr and B both are connected
ansistor Qnsistor Q11 are forward biased. are forwaHence diodes De diodes D11 and D and D2 in figureC in figure 2 to 0.7 V. n figure 2 to 0.7 V.
This voltage is insufficient to is voltage is insufficient Q2 will remain OFF. will remain OFF
Therefore its collector v Therefore its co
ar Two input TTL NAND gate. Two input TTL NAND gate.
Prelim Question Paper Solution
105
AS transistor Q3 is operating in the emitter follower mode, output Y will be pulled up to high voltage.
Y = 1 (HIGH) … For A = B = 0 (LOW) The equivalent circuit for this input condition is shown in figure 3(a).
(a) Equivalent circuit for A = B = 0 (b) Equivalent circuit for A = 1, B = 0.
(c) equivalent circuit for A = B = 1.
Fig. 3 Either A or B LOW If any one input (A or B) is connected to ground with the other terminal left
open or connected to + VCC then the corresponding diode (D1 or D2 ) will conduct.
This will pull down the voltage at “C” to 0.7 V.
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ar (b) Equivalent circuit for A =(b) Equivalent
Either I
Vidyalankar : S.Y. Diploma PDT
106
This voltage is insufficient to turn ON Q2. So it remains OFF. So collector voltage VX of Q2 will equal to VCC. This voltage acts as base
voltage for Q3. As Q3 acts as an emitter follower, output Y will be pulled to VCC.
Y 1
if A = andB
if A =1andB
The equivalent circuit for this mode is shown in figure 3(b) A and B both HIGH If A and B are connected to + VCC, then both the diodes D1 and D2 will be
reverse biased and do not conduct. Therefore diode D3 is forward biased and base current is supplied to
transistor Q2 via R1 and D3. As Q2 conducts, the voltage at X will drop down and Q3 will be OFF, whereas
voltage at Z (across R3) will increase to turn ON Q4. As Q4 goes into saturation, the output voltage Y will be pulled down to a low
voltage. The equivalent circuit for this mode of operation is shown in figure 3(c) This discussion reveals that the circuit operates as a NAND gate.
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arodes D11 and D and D22 will be will be
ase current is supplied to ase current is supplied t
own and Q and Q33 will be OFF, whereas will be OFF, whurn ON Q4.
voltage Y will be pulled down to ae Y will be pulle
e of operation is shown in figure 3eration is shown ine circuit operates as a NAND gate. operates as a NAN
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