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MAHA S M. T A ATMA GANDHI UNIVERSITY SCHEME AND SYLLABI FOR Tech. DEGREE PROGRAMME IN APPLIED ELECTRONICS (2011ADMISSION ONWARDS) Y
MAHATMA GANDHI UNIVERSITY
SCHEME AND SYLLABI
M. Tech. DEGREE PROGRAMME
APPLIED ELECTRONICS
MAHATMA GANDHI UNIVERSITY
SCHEME AND SYLLABI
FOR
M. Tech. DEGREE PROGRAMME
IN
APPLIED ELECTRONICS
(2011ADMISSION ONWARDS)
MAHATMA GANDHI UNIVERSITY
1
SCHEME AND SYLLABI FOR M. Tech. DEGREE
PROGRAMME IN APPLIED ELECTRONICS
SEMESTER - I
Sl.
No.
Course
No. Subject
Hrs / Week Evaluation Scheme (Marks)
Credits
(C) L T P
Sessional
ESE Total
TA CT Sub
Total
1 MECAE 101 Electronic System Modelling and
Design 3 1 0 25 25 50 100 150 4
2 MECAE 102 Analog Integrated Circuit Design 3 1 0 25 25 50 100 150 4
3 MECAE 103 Digital Integrated Circuit Design 3 1 0 25 25 50 100 150 4
4 MECAE 104 RF System Design 3 1 0 25 25 50 100 150 4
5 MECAE 105 Elective – I 3 0 0 25 25 50 100 150 3
6 MECAE 106 Elective – II 3 0 0 25 25 50 100 150 3
7 MECAE 107 Electronic System Design Lab-I 0 0 3 25 25 50 100 150 2
8 MECAE 108 Seminar – I 0 0 2 50 0 50 0 50 1
Total 18 4 5 225 175 400 700 1100 25
Elective – I (MECAE 105) Elective – II (MECAE 106)
MECAE 105 - 1 Digital Communication System Design MEC AE 106 - 1 Communication System Modelling and
Design
MECAE 105 - 2 RF Components and Circuit Design MEC AE 106 - 2 RF Antenna Design
MECAE 105 - 3 Image and Video Processing System Design MEC AE 106 - 3 Speech and Audio Processing System
Design
MECAE 105 - 4 VLSI System Design MEC AE 106 - 4 Embedded System Design
L – Lecture, T – Tutorial, P – Practical
TA – Teacher’s Assessment (Assignments, attendance, group discussion, Quiz, tutorials,
seminars, etc.)
CT – Class Test (Minimum of two tests to be conducted by the Institute)
ESE – End Semester Examination to be conducted by the University
Electives: New Electives may be added by the department according to the needs of emerging
fields of technology. The name of the elective and its syllabus should be submitted to
the University before the course is offered.
2
SEMESTER - II
Sl.
No.
Course
No. Subject
Hrs / Week Evaluation Scheme (Marks)
Credits
(C) L T P
Sessional
ESE Total
TA CT Sub
Total
1 MECAE 201 Electronic Product Design 3 1 0 25 25 50 100 150 4
2 MECAE 202 Analog and Data Conversion System
Design 3 1 0 25 25 50 100 150 4
3 MECAE 203 High Speed Digital System design 3 1 0 25 25 50 100 150 4
4 MECAE 204 DSP Algorithm and Architecture
Design 3 1 0 25 25 50 100 150 4
5 MECAE 205 Elective – III 3 0 0 25 25 50 100 150 3
6 MECAE 206 Elective – IV 3 0 0 25 25 50 100 150 3
7 MECAE 207 Electronic System Design Lab-II 0 0 3 25 25 50 100 150 2
8 MECAE 208 Seminar – II 0 0 2 50 0 50 0 50 1
Total 18 4 5 225 175 400 700 1100 25
Elective – III (MECAE 205) Elective – IV (MECAE 206)
MECAE 205 - 1 Wireless Communication System Design MECAE 206 - 1 Optical Communication System Design
MECAE 205 - 2 RF Integrated Circuit Design MECAE 206 - 2 RF and Microwave Network Design
MECAE 205 - 3 DSP System Design MECAE 206 - 3 Detection and Tracking System Design
MECAE 205 - 4 ASIC Design MECAE 206 - 4 Embedded Network Design
L – Lecture, T – Tutorial, P – Practical
TA – Teacher’s Assessment (Assignments, attendance, group discussion, Quiz, tutorials,
seminars, etc.)
CT – Class Test (Minimum of two tests to be conducted by the Institute)
ESE – End Semester Examination to be conducted by the University
Electives: New Electives may be added by the department according to the needs of emerging
fields of technology. The name of the elective and its syllabus should be submitted to
the University before the course is offered.
3
SEMESTER - III
Sl.
No. Course No. Subject
Hrs / Week Evaluation Scheme (Marks)
Credits
(C) L T P
Sessional ESE**
(Oral) Total
TA* CT Sub
Total
1 MECAE 301
Industrial Training or
Industrial Training and Mini
Project
0 0 20 50 0 50 100 150 10
2 MECAE 302 Master’s Thesis Phase - I 0 0 10 100*** 0 100 0 100 5
Total 0 0 30 150 0 150 100 250 15
* TA based on a Technical Report submitted together with presentation at the end of the
Industrial Training and Mini Project
** Evaluation of the Industrial Training and Mini Project will be conducted at the end of the third
semester by a panel of examiners, with at least one external examiner, constituted by the
University.
*** The marks will be awarded by a panel of examiners constituted by the concerned institute
SEMESTER - IV
Sl.
No. Course No. Subject
Hrs / Week Evaluation Scheme (Marks)
Credits
(C) L T P
Sessional ESE**
(Oral
&
Viva)
Total
TA* CT Sub
Total
1 MECAE 401 Master’s Thesis 0 0 30 100 0 100 100 200 15
2 MECAE 402 Master’s Comprehensive Viva 100 100
Total 30 100 0 100 200 300 15
Grand Total of all Semesters 2750 80
* 50% of the marks to be awarded by the Project Guide and the remaining 50% to be awarded
by a panel of examiners, including the Project Guide, constituted by the Department
** Thesis evaluation and Viva-voce will be conducted at the end of the fourth semester by a panel
of examiners, with at least one external examiner, constituted by the University.
4
MECAE 101 ELECTRONIC SYSTEM MODELLING AND
DESIGN L T P C
3 1 0 4
Module 1: Representation of Systems
Electrical / Mechanical / Hydraulic / Acoustic Systems: Transfer Function Vs. State Space
Representation, Numerical Methods and Discretization. Linear Systems: Methods of
Model Order Determination, Impulse and Frequency Response Methods. Time Varying
(Linear) Systems: Stability Concepts, Fractal Behaviour. Nonlinear Models: Introduction
to Stable Oscillations, Chaotic Behaviour, Jump Phenomena.
Module 2: Modelling, Identification and Simulation
Linear Modelling, Identification and Simulation: Least Squares Identification Methods;
Off-Line and On-Line, Applications of LS and ARMA Methods, Regression Methods.
Introduction to Non Linear Modelling, Identification and Simulation: Examples of
Non Linear Models and Methods of Nonlinear Identification.
Module 3: Analog and Digital Circuit Simulator Algorithms
Basic flow of the Circuit Simulators: Inputs and Outputs. Simulation Algorithms:
Modified Nodal Analysis, LU Decomposition, Sparse Matrix Algorithms, Newton-
Raphson Iterative Techniques, and Numerical Integration. Convergence Issues and
Simulation Accuracy. Basics of Logic Simulation: Event Queues and Event-Driven
Simulation Techniques.
Module 4: Modelling With Hardware Description Languages
Semantics of representing Mixed-Signal Circuit behaviour, Modelling Conservation Laws,
Implicit Relationships, Multi-Dimensional Observed Phenomena, and Multiple
Technology Domains (Thermal, Electrical, Mechanical, etc.). Operations for Moving from
Analog to Digital and vice-versa: Thresholding to obtain an event from an Analog
Quantity, Ramping to convert an event into an Analog Quantity. Analysis of Mixed-
Signal Circuits and Systems: Basic and Advanced Analysis Capabilities in the State-of-
the-Art Simulators: AC, DC, Transient, Noise, Distortion Analysis and Stress, Sensitivity,
and Failure Modes and effects
5
References:
1. Najm F. N., “Circuit Simulation”, John Wiley & Sons, 2010.
2. Frank L. Severance, “System Modelling and Simulation: An Introduction”, Wiley,
2001.
3. Ashenden P., Peterson, G. & Teegarden D., “The System Designer’s Guide to VHDL-
AMS”, Morgan-Kaufman, 2003.
4. Vlach J. & Singhal K., “Computer Methods for Circuit Analysis and Design”,
2nd
Ed., Kluwer Academic Publishers, 2003.
5. Pillage L. T., Rohrer R. A. & Visweswariah C., “Electronic Circuit and System
Simulation Methods”, McGraw Hill, 1995.
6
MECAE 102 ANALOG INTEGRATED CIRCUIT DESIGN L T P C
3 1 0 4
Module 1: MOSFET Operation and Models for Analog Design
MOSFET Capacitance Overview / Review, Threshold Voltage, I-V Characteristics of
MOSFETs. Models for Analog Design: Long-Channel MOSFETs, Square-Law Equations,
Small Signal Models, Temperature Effects, Short-Channel MOSFETs, General Design,
MOSFET Noise Modeling.
Module 2: Current Mirrors and Single-Stage Amplifiers
Current Mirrors: Basic Current Mirror: Long-Channel Design, Matching Currents in the
Mirror, Biasing the Current Mirror, Short-Channel Design, Temperature Behaviour,
Biasing in the Subthreshold Region. Cascoding the Current Mirror: Simple Cascode,
Low-Voltage (Wide-Swing) Cascode; Wide-Swing, Short-Channel Design, Regulated
Drain Current Mirror. Biasing Circuits: Long-Channel Biasing Circuits, Short-Channel
Biasing Circuits.
Amplifiers: Gate-Drain Connected Loads: Common-Source Amplifiers, Source Follower,
Common-Gate Amplifier. Current Source Loads: Common-Source Amplifier, Cascode
Amplifier, Common-Gate Amplifier, Source Follower. Push-Pull Amplifier: DC
Operation and Biasing, Small-Signal Analysis, Distortion.
Module 3: Differential Amplifiers and Voltage References
Differential Amplifiers: Source-Coupled Pair: DC Operation, AC Operation, CMRR,
Matching Considerations, Noise Performance, Slew-Rate Limitations. Source Cross-
Coupled Pair: Operation of the Diff-Amp, Current Source Load, Cascode Loads.
Wide-Swing Differential Amplifiers: Current Differential Amplifier, Constant
Transconductance Diff-Amp.
Voltage References: MOSFET-Resistor Voltage References: Resistor-MOSFET Divider,
MOSFET-Only Voltage Divider, Self-Biased Voltage References. Parasitic Diode-Based
References: Long-Channel BGR Design, Short-Channel BGR Design.
Module 4: Operational Amplifiers
One-Stage and Two-Stage Op-Amps: Low-Frequency, Open Loop Gain, Input Common-
Mode Range, Power Dissipation, Output Swing and Current Source / Sinking Capability,
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Offsets. Compensating the Op-Amp: Gain and Phase Margins, Compensation for High-
Speed Operation, Slew-Rate Limitations. CMRR and PSRR. Op-Amp with Output Buffer;
Operational Transconductance Amplifier; OTA with Output Buffer, Folded-Cascode
OTA. Gain-Enhancement, Three-Stage Op-Amp Design.
References:
1. Jacob Baker R., “CMOS: Circuit Design, Layout, and Simulation”, Wiley, 2010.
2. Philip E. Allen & Douglas R. Holberg, “CMOS Analog Circuit Design”, 2nd
Ed.,
Oxford University Press, 2009.
3. Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, McGraw Hill Higher
Education, 2003.
4. David A. Johns & Ken Martin, “Analog Integrated Circuit Design”, Wiley India Pvt.
Ltd., 2008.
5. Paul R. Gray, Paul J. Hurst, Stephen H. Lewis & Robert G. Meryer, “Analysis and
Design of Analog Integrated Circuits”, 5th
Ed., Wiley 2009.
6. Richard C. Jaeger & Travis N. Blalock, “Microelectronic Circuit Design with CD-
ROM”, 2nd
Ed., McGraw Hill, 2003.
8
MECAE 103 DIGITAL INTEGRATED CIRCUIT DESIGN L T P C
3 1 0 4
Module 1: CMOS Inverter
Issues in Digital Integrated Circuit Design, Quality Metrics of a Digital Design, Cost of an
Integrated Circuit, Functionality and Robustness, Performance, Power and Energy
Consumption. Static CMOS Inverter: Static Behavior, Switching Threshold, Noise
Margins. Performance of CMOS Inverter: Dynamic Behavior, Computing the
Capacitances, Propagation Delay: First-Order Analysis, Propagation Delay from a Design
Perspective, Power, Energy, and Energy-Delay, Dynamic Power Consumption, Static
Consumption, Analyzing Power Consumption using SPICE, Perspective: Technology
Scaling And its Impact on the Inverter Metrics
Module 2: Designing Combinational Logic Gates in CMOS
Static CMOS Design, Complementary CMOS, Ratioed Logic, Pass-Transistor Logic,
Dynamic CMOS Design, Dynamic Logic: Basic Principles, Speed and Power Dissipation
of Dynamic Logic, Issues in Dynamic Design, Cascading Dynamic Gates, Perspectives:
How To Choose A Logic Style? Designing Logic for Reduced Supply Voltage.
Module 3: Designing Sequential Logic Circuits
Timing Metrics for Sequential Circuits, Classification of Memory Elements, Static
Latches and Registers, Bistability Principle, Multiplexer-Based Latches, Master-Slave
Edge-Triggered Register, Low-Voltage Static Latches, Static SR Flip-Flops, Dynamic
Latches and Registers, Dynamic Transmission-Gate Edge-Triggered Registers,
CMOS - Clock-Skew Insensitive Approach, True Single-Phase Clocked Register
(TSPCR), Alternative Register Styles, Pulse Registers, Sense-Amplifier Based Registers,
Pipelining: An Approach to Optimize Sequential Circuits, Latch Vs. Register-Based
Pipelines, NORA-CMOS - Logic Style for Pipelined Structures, Non-Bistable Sequential
Circuits, Schmitt Trigger, Monostable Sequential Circuits, Astable Circuits, Perspective:
Choosing a Clocking Strategy.
Module 4: Timing Issues in Digital Circuits
Timing Classification of Digital Systems, Synchronous Interconnect, Mesochronous
Interconnect, Plesiochronous Interconnect, Asynchronous Interconnect, Synchronous
Design: Synchronous Timing Basics, Sources of Skew and Jitter, Clock-Distribution
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Techniques, Latch-Based Clocking, Self-Timed Circuit Design, Self-Timed Logic -
Asynchronous Technique, Completion-Signal Generation, Self-Timed Signaling, Practical
Examples of Self-Timed Logic.
Synchronizers and Arbiters: Synchronizers - Concept and Implementation, Arbiters, Clock
Synthesis and Synchronization using A Phase-Locked Loop: Basic Concept, Building
Blocks of a PLL, Distributed Clocking using DLLs.
References:
1. Jan M. Rabaey, Anantha Chandrakasan & Borivoje Nikolic, “Digital Integrated
Circuits: A Design Perspective”, 2nd
Ed. Pearson Education Asia, 2007.
2. Jacob Baker R., “CMOS: Circuit Design, Layout, and Simulation”, Wiley, 2010.
3. Ken Martin, “Digital Integrated Circuit Design”, Oxford University Press, 1999.
4. Sung-Mo (Steve) Kang & Yusuf Leblebici, “CMOS Digital Integrated Circuits
Analysis and Design”, 3rd
Ed., McGraw Hill, 2002.
5. David Hodges, Horace Jackson & Resve Saleh, “Analysis and Design of Digital
Integrated Circuits”, 3rd
Ed., McGraw Hill, 2003.
6. Hubert Kaeslin & Eth Zürich, “Digital Integrated Circuit Design from VLSI
Architectures to CMOS Fabrication”, Cambridge University Press, 2008.
10
MECAE104 RF SYSTEM DESIGN L T P C
3 1 0 4
Module 1: Transmission Line Theory
Review of Transmission Line Theory: Lumped Element Model, Field Analysis of
Transmission Lines, Terminated Lossless Lines, SWR, and Impedance Mismatches.
Planar Transmission-Lines: Stripline, Microstrip, Coplanar-Line.
Smith Chart: Reflection Coefficient, Load Impedance, Impedance Transformation,
Admittance Transformation, Parallel and Series Connection. Revision of S-Parameters.
Module 2: RF Filter Design
Overview; Basic Resonator and Filter Configuration, Special Filter Realizations, Filter
Implementations, Coupled Filter.
Module 3: Impedance Matching Networks
Impedance Matching using Discrete Components, Microstripline Matching Networks,
Single Stub Matching Network , Double Stub Matching Network. Quarter-Wave
Transformers, Multi-Section and Tapered Transformers.
Module 4: RF Amplifiers, Oscillators and Mixers
Characteristics; Amplifier Power Relations, Stability Considerations, Constant Gain
Circles, Noise Figure Circles, Constant VSWR Circles, Low Noise Circuits; Broadband,
High Power and Multistage Amplifiers.
Basic Oscillator Model, High Frequency Oscillator Configurations, Basic Characteristics
of Mixers.
References:
1. Reinhold Ludwig & Powel Bretchko, “RF Circuit Design – Theory and Applications”,
1st Ed., Pearson Education Ltd., 2004.
2. David M. Pozzar , “ Microwave Engineering”, 3r Ed., Wiley India, 2007.
3. Mathew M. Radmanesh, “Radio Frequency and Microwave Electronics”, 2nd
Ed.
Pearson Education Asia, 2006.
4. Mathew M. Radmanesh, “Advanced RF & Microwave Circuit Design-The Ultimate
Guide to System Design”, Pearson Education Asia, 2009.
11
5. Ulrich L. Rohde & David P. NewKirk, “RF / Microwave Circuit Design”, John Wiley
& Sons, 2000.
6. Davis W. Alan, “Radio Frequency Circuit Design”, Wiley India, 2009.
7. Christopher Bowick, John Blyer & Cheryl Ajluni “ RF Circuit Design”, 2nd
Ed.,
Newnes, 2007.
8. Cotter W. Sayre, “Complete Wireless Design”, 2nd
Ed., McGraw-Hill, 2008.
9. Joseph J. Carr, “RF Components and Circuits”, Newnes, 2002.
12
MECAE 105 - 1 DIGITAL COMMUNICATION SYSTEM DESIGN L T P C
3 0 0 3
Module 1: Overview of Communication System
Overview of a Communication System: Channel, and Performance Issues; Review of
Signal Classification and Characteristics. Operations on Signals: Correlation,
Orthogonality.
Analysis and Transmission of Signals: Fourier Series, Fourier Transform; Signal
Transmission through a Linear System: Distortion, Energy and Power Spectral Density.
Sampling, Pulse-Amplitude Modulation, Time-Division Multiplexing, Quantization,
Pulse-Code Modulation, Matched Filter, Inter Symbol Interference, Channel Equalization,
Adaptive Equalizer.
Module 2: Signaling and Modulation
Communication System in AWGN Noise, Binary PSK and FSK Systems, M-ary Pulse
Amplitude Modulation, Signal Space Representation, Geometric Representation of
Signals. Two-Dimensional M-ary Signaling: M-PSK and M-QAM. M-dimensional M-Ary
Signaling: M-FSK and OFDM. Band Pass and Band Limited Digital Modulation. Effect of
Noise on Communication Systems, Properties and Representation of Noise.
Module 3: Channels
Wireless (Multipath) Channel Models, Classification of Wireless Channel Models.
Frequency Selectivity and Multipath Fading. Digital Modulations for Flat-Fading
Channels, Signaling for Flat-Fading Channels: Error Control Coding. Digital Modulations
for Frequency-Selective Channels. Signaling for Frequency-Selective Channels:
Equalization, OFDM.
Module 4: Diversity Techniques
Spatial Receive Diversity Techniques for Multipath Channels, Spatial Transmit Diversity
Techniques for Multipath Channels, MIMO Systems.
References:
1. John G. Proakis & Masoud Salehi, “Digital Communications," 5th
Ed., McGraw Hill,
2008.
2. Rice M., “Digital Communications: A Discrete-Time Approach”, Prentice-Hall, 2009.
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3. Barry J. R., Lee E. A. & Messerschmitt D. G., “Digital Communication,” 3rd
Ed.,
Kluwer Academic Publishers, 2004.
4. Ha H. Nguyen & Ed Shwedyk, “A First Course in Digital Communication”,
Cambridge University Press, 2009.
5. Tri T. Ha, “Theory and Design of Digital Communication Systems”, California
Cambridge University Press, 2010.
6. Simon M. K., Hinedi S. M. & Lindsey W. C., “Digital Communication Techniques-
Signal Design and Detection”, Prentice Hall, 1995.
7. John G. Proakis & Masoud Salehi, “Fundamentals of Communication Systems”,
Prentice Hall, 2005.
8. Anderson J. B. & Svensson A., “Coded Modulation Systems”, Kluwer Academic /
Plenum Publishers, 2003.
9. John B. Anderson, “Digital Transmission Engineering”, Wiley Inter-Science, 2005.
10. Stark H. & Woods J.W., “Probability and Random Processes with Applications to
Signal Processing”, 3rd
Ed., Prentice Hall, 2002.
11. Papoulis A. & Pillai S.U., “Probability, Random Variables and Stochastic Processes”,
McGraw Hill, 2002.
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MECAE 105 - 2 RF COMPONENTS AND CIRCUIT DESIGN L T P C
3 0 0 3
Module 1: RF Components
Introduction; Cascaded Linear Two-Port Networks, Signal Flow Graph, Noise in
Two-Port Network, Non-Linear Two-Port Networks. Importance of RF Design, RF
Behaviour of Passive Components, Chip Components and Circuit Board Considerations.
Active RF Components: RF Diodes - Schottky Diode, PIN Diode, Varactor Diode,
IMPATT, TRAPATT, BARRIT and Gunn Diodes, Tunnel Diode, Noise Diode, Snap
Diode. Microwave Transistor Issues: Silicon Vs. GaAs. Noise Sources, S-Parameters,
Noise Figure Parameters. RF Field Effect Transistors, High Mobility Transistors.
Module 2: Active RF Components Modelling
Diode Models: Non Linear Diode Model, Linear Diode Model. Transistor Models: Large
Signal BJT Models, Small Signal BJT Models, Large Signal FET Models, Small Signal
FET Models. Scattering Parameter Device Characterization.
Module 3: Microwave Control Components
Introduction; Switches: PIN Diode Switches, FET Switches, MEMS Switches, Alternative
Multi Port Switch Structure. Variable Attenuators, Phase Shifters: True Relay and Slow
Wave Phase Shifters, Reflection Phase Shifters, Stepped Phase Shifters, Binary Phase
Shifters.
Module 4: Microwave Circuit Technology
Introduction; Hybrid and Monolithic Integrated Circuits, High Frequency PCB, Hybrid
MICs, MMICs, Advanced Hybrid MICs, Parasitic elements associated with Physical
Devices. Basic MMIC Elements: Transmission Lines, Via Holes, Resistors, Inductors,
Capacitors, Semiconductor Devices. Simulation Models: Single Element Models, Scalable
Models, Non Linear Models, MMIC Statistical Models, Temperature Models. MMIC
Production Techniques: Lithography, On-Wafer Testing, Cut and Selection.
References:
1. Reinhold Ludwig & Powel Bretchko, “RF Circuit Design – Theory and Applications”,
2nd
Ed., Prentice Hall Ltd., 2008.
2. Sorrentino R. & Bianchi G., “Microwave and RF Engineering”, John Wiley, 2010.
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3. Cotter W. Sayre, “Complete Wireless Design”, 2nd
Ed., McGraw Hill, 2008.
4. Coleman C., “An introduction to Radio Frequency Engineering”, Cambridge, 2004.
5. Mathew M. Radmanesh, “Advanced RF & Microwave Circuit Design – The Ultimate
Guide to System Design”, Pearson Education Asia, 2009.
6. David M. Pozzar , “ Microwave Engineering”, 3rd
Ed., Wiley India, 2007.
7. Jia-Sheng Hong, Lancaster M. J. & Waun Ed. Hong, “Microstrip Filters for RF /
Microwave Applications”, Wiley Interscience, 2001.
8. Inder Bahl, “Lumped Elements for RF and Microwave Circuits”, Artech House, 2003.
9. Joseph J. Carr, “RF Components and Circuits”, Newnes, 2002.
10. Guillermo Gonzalez, “Microwave Transistor Amplifiers: Analysis and Design”,
Prentice Hall, 1997.
11. Inder Bahl, “Fundamentals of RF and Microwave Transistor Amplifiers”, John Wiley
& Sons, 2009.
16
MECAE 105 - 3 IMAGE AND VIDEO PROCESSING SYSTEM
DESIGN L T P C
3 0 0 3
Module 1: Image and Video Basics
Human System of Sight, Basic Laws of Perception, Colour and its Representation. Fourier
Transforms and their Applications in Image Processing. Sampling, Aliasing, Linear
Filters, Image Quantization, Image Equalization. Concepts of Probabilities applied to
Images. Mathematical Morphology: Basic Operations, Mathematical Morphology Filters.
Notions of the Theory of Information.
Analog Video and PAL / NTSC Systems, Space-Time Sampling, Video Processing
Applications. Conversion from Interlaced to Progressive, Conversion of Frame-Rate.
Video Filtering by Motion Compensation, Noise Reduction and Restoration in Videos.
Object Following, Error Resiliency, Video Digital Signature.
Module 2: Image and Video Enhancement
Spatial Domain Vs. Frequency Domain, Enhancement via Point Operations: Contrast
Stretching, Colormap Look-Up Tables, Clipping, Thresholding, Negation, Gray-Level
Slicing, Bit-Plane Slicing, Range Compression, Algebraic Operators. Enhancement via
Histogram Modeling: Histogram Modification, Histogram Equalization, Histogram
Specification. Processing via Algebraic Operations: Input And Output Histograms, Sums
and Differences of Images, Averaging Noisy Images, Background Removal, Change or
Motion Detection. Processing Via Spatial Operations: Weighted Local Area Smoothing or
Averaging, Derivative Filters, Sharpening Filters, Median Filtering, Gray Level
Interpolation, Spatial Transformations.
Module 3: Image and Video Encoding Systems
General Block Diagram of an Image and Video Encoding System, Human Sight System:
Application to Image and Video Encoding. Analysis of Images and Video, Discrete
Cosine Transform. Basic Principles of Wavelet Transform. Predictive Coding, Transform
Coding, Resolution Pyramids and Sub Band Coding, Interframe Coding.
2-D Motion Estimation: Optical Flow, Calculation of Optical Flow General
Methodologies, Pixel Based Motion Estimation, Block Matching Algorithm, Mesh-Based
Motion Estimation, Global Motion Estimation, Region Based Motion Estimation, Multi
Resolution Motion Estimation. Application of Motion Estimation in Video Coding. Still
17
Image Compression Standards: JPEG and JPEG 2000. Comparison with other Formats of
Still Image. Video Compression Standards: H.261, MPEG-1/2 and Others.
Module 4: Three Dimensional Vision
Affine and Metric Geometry, 2D and 3D Geometrical Transformations, Representation of
Perspective. Basic Concepts of Projective Geometry of Planes and Spaces. 2-D
Homography Estimations. Models of Cameras, Camera Calibration, Epipolar Geometry.
Calculation of the Fundamental Matrix, Image Rectification. Three-Dimensional
Reconstruction of a Scene. Scene Plans and Homographies. Trifocal Tensor. Geometry of
Three or More Views.
References:
1. Murat Tekalp A., “Digital Video Processing”, Prentice Hall, 1996.
2. Iain E. Richardson, “Video Codec Design: Developing Image and Video Compression
Systems”, Wiley Interscience, 2002.
3. Yao Wang, Jorn Ostermann & Ya-Qin Zhang, “Video Processing and
Communications”, Prentice Hall, 2002.
4. Richard Szeliski, “Computer Vision: Algorithms and Applications”, Springer, 2010.
5. Boguslaw Cyganek & Paul Siebert J., “An Introduction to 3D Computer Vision
Techniques and Algorithms”, Wiley Inter Science, 2009.
6. Yi Ma, Stefano Soatto, Jana Kosecka, & Shankar Sastry, “An Invitation to 3-D Vision
- From Images to Geometric Models”, Springer-Verlag, 2004.
7. Forsythe D. & Ponce J., “Computer Vision: A Modern Approach”, Prentice-Hall,
2003.
8. Richard Hartley & Andrew Zisserman, “Multiple View Geometry in Computer
Vision”, 6th
Ed., Cambridge University Press, 2008.
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MECAE 105 - 4 VLSI SYSTEM DESIGN L T P C
3 0 0 3
Module 1: Introduction to CMOS VLSI Design
Introduction to Digital IC Design: Custom and Semicustom Flow, MOSFET Models,
MOSFET Capacitances, Transistors and Layout. CMOS Inverter: Effect of Process
Variation, Supply Scaling, Inverter Design for a given VTC and Speed, Effect of Input
Rise Time and Fall Time, Static and Dynamic Power Dissipation, Energy and Power
Delay Product, Sizing Chain of Inverters, Latch Up Effect. Simulation of Static and
Dynamic Characteristics. CMOS Layout Elements: Parasitics, Wires and Vias, Design
Rules, Layout Design. SPICE Simulation of MOSFET I-V Characteristics and Parameter
Extraction Post Layout Simulation.
Module 2: Static and Dynamic CMOS Design
Static CMOS Design: Complementary CMOS, Static Properties, Propagation Delay,
Elmore Delay Model, Power Consumption, Low Power Design Techniques, Logical Effort
for Transistor Sizing, Ratioed Logic, Pseudo NMOS Inverter, DCVSL, PTL, DPTL &
Transmission Gate Logic. Dynamic CMOS Design: Speed and Power Considerations,
Domino Logic and Its Derivatives, C2MOS, TSPC Registers, NORA CMOS.
Combinational Logic Synthesis: Technology Independent and Technology Dependent
Optimization.
Module 3: Subsystem Design and Timing Issues
Subsystem Design Principles: Pipelining, Data Paths in Processor Architecture, Standard
Cell Layout, Logic Design Considerations of Adder, Multiplier, Shifter. Sequencing Static
Circuits, Circuit Design of Latches and Flip Flops, Static Sequencing Element
Methodology, Sequencing Dynamic Circuits, Synchronizers. CMOS Memory Design:
SRAM and DRAM. BiCMOS Logic: Static and Dynamic Behaviour, Delay and Power
Consumption in BiCMOS Logic. Timing: Slack Delay Model, Effect of Skew and Jitter on
Timing, Sources of Skew and Jitter, Clocking Disciplines, Wire Model, Technology
Scaling Effect on Interconnect and Noise in Interconnects.
Module 4: Routing, Scheduling and Allocation
Partitioning, Floor Planning and Pin Assignment, Slicing Tree, Channel Definition,
Channel Routing Order, Wind Mill Constraint, Placement, Special Routing, Clock
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Routing for Regular and Irregular Structures, Power Routing, Global Routing, Line Probe
Algorithm, Maze Routing, Detail Routing, Left Edge Algorithm, Vertical Constraint,
Switch Box Routing. Logic Synthesis, High Level Synthesis. Scheduling and Allocation:
ASAP and ALAP Scheduling, Register Allocation, Functional Unit Allocation,
Interconnect Path Allocation. Hardware Description Languages: Synthesis, Register
Transfer Design, Event Driven Simulation. FPGA Logic Element and Interconnect
Architecture, Logic Synthesis for FPGA, Physical Design for FPGA, I / O Circuits, ESD
Protection, Off Chip Connections.
References:
1. Weste & Harris “CMOS VLSI Design”, 3rd
Ed., Pearson Education, 2005.
2. Jan M. Rabae, “Digital Integrated Circuits - A Design Perspective”, 2nd
Ed., Prentice
Hall, 2005.
3. Uyemura J. P, “Introduction to VLSI Circuits and Systems”, Wiley, 2002.
4. Wayne Wolf, “FPGA-Based System Design”, Pearson, 2009.
5. James R. Armstrong & Gail Gray F., “VHDL Design Representation and Synthesis”,
Pearson Education, 2007.
6. Naveed A. Sherwani, “Algorithms for VLSI Physical Design Automation”, 3rd
Ed.,
Springer, 1999.
20
MECAE 106 - 1 COMMUNICATION SYSTEM MODELLING AND
DESIGN L T P C
3 0 0 3
Module 1: Modelling of Communication Systems
Model of Speech and Picture Signals, Pseudo Noise Sequences, Non-Linear Sequences,
Analog Channel Model, Noise and Fading, Digital Channel Model: Gilbert Model of
Bursty Channels, HF, Troposcatter and Satellite Channels, Switched Telephone Channels,
Analog and Digital Communication System Models, Light Wave System Models.
Module 2: Simulation of Random Variables and Random Process
Univariate and Multivariate Models, Transformation of Random Variables, Bounds and
Approximation, Random Process Models: Markov and ARMA Sequences, Sampling Rate
for Simulation, Computer Generation and Testing of Random Numbers.
Module 3: Estimation of Performance Measures
Quality of an Estimator, Estimator for SNR, Probability Density Functions of Analog
Communication System, BER of Digital Communication Systems, Monte Carlo Method
and Importance of Sampling Method, Estimation of Power Spectral Density
Module 4: Communication Networks
Queuing Models, M/M/I and M/M/I/N Queues, Little Formula, Burke's Theorem, M/G/I
Queue, Embedded Markov Chain Analysis of TDM Systems, Polling, Random Access
Systems.
Network of Queues: Queues in Tandem, Store and Forward Communication Networks,
Capacity Allocation, Congestion and Flow Chart, Routing Model, Network Layout and
Reliability.
References:
1. Jeruchim M. C., Philip Balaban & Sam Shanmugan K., "Simulation of
Communication Systems", 2nd
Ed., Kluwer Academic Publishers, 2002.
2. Law A. M., "Simulation, Modelling and Analysis", 3rd
Ed., Tata McGraw Hill, 2007.
3. Hayes J. F., “Modeling and Analysis of Computer Communication Networks”, Kluwer
Academic Publishers, 2002.
4. Jerry Banks, John S. Carson & Barry L Nelson, “Discrete-Event System Simulation”,
4th
Ed., Dorling Kindersley (India) Pvt. Ltd., 2007.
21
MECAE 106 - 2 RF ANTENNA DESIGN L T P C
3 0 0 3
Module 1: Microstrip Radiators
Introduction; Advantages and Limitations of Microstrip Antenna, Radiation Mechanism
of a Microstrip Antenna, Various Microstrip Antenna Configurations, Microstrip Patch
Antenna, Printed Dipole Antenna, Printed Slot Antenna, Feeding Techniques and
Modeling, Coaxial Feed / Probe Coupling, Microstrip (Coplanar) Feed, Proximity Coupled
Microstrip Feed, Aperture Coupled Microstrip Feed, Coplanar Waveguide Feed, Radiation
Fields.
Module 2: Rectangular Microstrip Antenna
Introduction; Models of Rectangular Patch Antenna, Transmission Line Model Analysis ,
Cavity Model Analysis, Design Considerations of Rectangular Patch Antenna, Substrate
Selection, Element Width and Length, Radiation Pattern and Radiation Resistance, Loss
Factor, Bandwidth, Radiation Efficiency, Feed Location and Polarization.
Module 3: Circular Microstrip Antenna
Introduction; Analysis of a Circular Disk Microstrip Antenna Using Cavity Model, Design
Considerations: Substrate Selection, Radiation Pattern, Quality Factor and Impedance
Bandwidth, Feed Point Location and Polarization.
Module 4: A. Broad Banding of Microstrip Antennas
Introduction; Effect of Substrate Parameters on Bandwidth, Selection of Suitable Patch
Shape, Selection of Suitable Feeding Technique, Aperture-Coupled Microstrip Antenna.
B. Compact Microstrip Antennas
Introduction; Use of a Shorted Patch with a Thin Dielectric Substrate, Use of a Meandered
Patch, Use of a Meandered Ground Plane, Use of a Planar Inverted-L Patch, Use of an
Inverted U-Shaped or Folded Patch.
References:
1. Bhartia P., Inder Bahl, Garg R. & Ittipiboon A., “Microstrip Antenna Design
Handbook”, Artech House Publishers, 2001.
2. Kin-Lu Wong, “Compact and Broadband Microstrip Antennas”, 1st Ed., Wiley-Inter
science, 2002.
22
3. Fang D.G., “Antenna Theory and Microstrip Antennas”, CRC Press, 2009.
4. Simon R. Saunders & Alejandro Aragon-Zavala, “Antennas and Propagation for
Wireless Communication System”, John Wiley & Sons, 2007.
23
MECAE 106 - 3 SPEECH AND AUDIO PROCESSING SYSTEM
DESIGN L T P C
3 0 0 3
Module 1: Review of Audio Sources and Propagation
Waves, Waveguides and Environmental Characteristics. Human Speech and Hearing:
Human Speech Generation Mechanism, Speech Signal Characteristics. Human Hearing
System: Ear, Auditory Physiology, Human Hearing Characteristics, Psychophysics,
Perceptual Issues, Auditory Scene Analysis.
Sound and Music Processing: Time Domain Methods - Time Domain Parameters of
Speech and Music Signal, Methods for Extracting the Parameters: Energy, Average
Magnitude, Zero Crossing Rate. Silence Discrimination using ZCR and Energy, Short
Time Auto Correlation Function, Pitch Period Estimation using Auto Correlation
Function.
Module 2: Frequency Domain Methods
Short Time Fourier Analysis: Fourier Transform and Linear Filtering Interpretations,
Sampling Rates, Spectrographic Displays, Pitch and Formant Extraction, Analysis by
Synthesis, Analysis-Synthesis Systems: Phase Vocoder, Channel Vocoder, Homomorphic
Speech Analysis: Cepstral Analysis of Speech, Formant and Pitch Estimation,
Homomorphic Vocoder, Spectral Modelling of Music Signals, Sinusoidal Plus Residual
Modelling of Music Signals, Extraction of Perceptual Attributes of Music Signals, Music
Applications Based on Audio Processing.
Module 3: Voice and Audio Encoding Systems
General Block Diagram of a Voice and Audio Encoding System; Human Auditory
System: Application to Voice and Audio Encoding. Analysis of Audio and of Music;
Predictive Encoding, Discrete Cosine Transform, Sub-Band Analysis, Bit Localization
Strategies, Rate / Distortion Techniques, Encoding in The Time Domain, PCM Encoding,
Predictive Encoding, Encoding in the Frequency Domain; MPEG-1 Audio, MPEG-2
Audio and MPEG-2 AAC, MPEG-4 Audio, Dolby AC-3 Audio; Applications: Voice over
IP.
24
Module 4: Real Time Audio Processing
Sampling, Time Resolution, Buffering, Latency and Jitter; Synchronous Vs.
Asynchronous Models in the Generation and Processing of Real Time Interactive Sound;
Aspects of Control and of Mapping; “Visual Data Flow"-Type Programming Languages
for Real Time Audio; Communication Protocols (MIDI, UDP Vs. TCP, OSC); Music
Analysis & Recognition: Transcription, Summarization, and Similarity; Sound Mixtures
and Separation: CASA, ICA, and Model-Based Separation.
References:
1. Thomas F. Quatieri, “Discrete-Time Speech Signal Processing”, Pearson Education,
2004.
2. Nelson Morgan & Ben Gold, “Speech and Audio Signal Processing: Processing and
Perception of Speech and Music” 1999.
3. Martin Russ, “Sound Synthesis and Sampling”, Focal Press, Elsevier, 2004.
4. John Watkinson, “The Art of Digital Audio”, Focal Press, Elsevier, 2001.
5. Deller J. R., Hansen J. H. L. & Proakis J. G., “Discrete Time Processing of Speech
Signals”, John Wiley, IEEE Press, 1999.
6. Kirk R. & Hunt A. “Digital Sound Processing for Music and Multimedia”, Focal
Press, 1999.
7. Eargle J. H. “Music Sound and Technology”, Van Nostrand Reinhold, 1995.
8. Vijay Madisetti, “Video, Speech, and Audio Signal Processing and Associated
Standards”, CRC Press, 2009.
25
MECAE 106 - 4 EMBEDDED SYSTEM DESIGN L T P C
3 0 0 3
Module 1: System Design Methodologies
System Design Challenges, Processor-Level Models, System-Level Models, System
Design Tools. System Design Methodologies: Bottom-up Methodology, Top-down
Methodology, Meet-in-the-middle Methodology, Platform Methodology, FPGA
Methodology, System-level Synthesis, Processor Synthesis.
Module 2: Modelling and Synthesis
Models of Computation, System Design Languages, System Modeling, Processor
Modeling, System Synthesis, System Design Trends, Automatic TLM Generation,
Platform Synthesis.
Module 3: Software Synthesis
Target Languages for Embedded Systems, RTOS, Software Synthesis Overview, Code
Generation, Multi-Task Synthesis, Internal Communication, Startup Code, Binary Image
Generation, Execution.
Module 4: Hardware Synthesis
RTL Architecture, Input Models, Estimation and Optimization, Register Sharing,
Functional Unit Sharing, Connection Sharing, Register Merging, Chaining and Multi-
Cycling, Functional-Unit Pipelining, Datapath Pipelining, Control and Datapath Pipelining
Scheduling, Interface Synthesis.
Embedded Design Practice: System Level Design Tools, Embedded Software Design
Tools, Hardware Design Tools, Case Study.
References:
1. Gajski D. D., Abdi S., Gerstlauer A. & Schirner G. “Embedded System Design:
Modeling, Synthesis, Verification”, Springer, 2009.
2. Peckol & James “Embedded Systems: A Contemporary Design Tool”, John Wiley &
Sons, 2008.
3. Marwedel P., “ Embedded System Design”, Springer, 2006.
4. Gerstlauer A., Doemer R., Peng J. & Gajski D., “System Design: A Practical Guide
with SpecC”, Kluwer, 2001.
26
5. Groetker T., Liao S., Martin G. & Swan S., “System Design with SystemC”, Kluwer,
2002.
6. Vahid F. & Givargis T., “Embedded System Design: A Unified Hardware / Software
Introduction”, John Wiley & Sons, 2001.
27
MECAE 107 ELECTRONIC SYSTEM DESIGN LAB - I L T P C
0 0 3 2
System simulation experiments based on the courses MECAE 101, MECAE 102,
MECAE 103 and MECAE 104 and the elective courses opted by the student in the first
semester.
MECAE 108 SEMINAR – I L T P C
0 0 2 1
Each student shall present a seminar on any topic of interest related to the core / elective
courses offered in the first semester of the M. Tech. Programme. He / she shall select the
topic based on the references from international journals of repute, preferably IEEE
journals. They should get the paper approved by the Programme Co-ordinator / Faculty
member in charge of the seminar and shall present it in the class. Every student shall
participate in the seminar. The students should undertake a detailed study on the topic and
submit a report at the end of the semester. Marks will be awarded based on the topic,
presentation, participation in the seminar and the report submitted.
28
MECAE 201 ELECTRONIC PRODUCT DESIGN L T P C
3 1 0 4
Module 1: Design for Manufacturability
Introduction, Growth, Mature and Saturation, Product Life Cycle Management, Design for
Manufacturability, Need of DFM: Higher Quality, Lower Cost, Faster Time to Market,
Better Yield Etc. Designer Vs. Manufacturer Need for Different DFM Techniques for
Different Companies, Different Applications, Different Manufactures, Different
Equipment and Processes. Development of DFM Rules: Design Guidelines, Exceptions.
Simple Assembly Process Vs. Complex and Expensive Components, Simple Component
Manufacture Vs. Complex Manufacturing Process, Simple and Inexpensive Design Vs.
Expensive and Complex Service and Support.
Module 2: PCB Design and Manufacturing Process
Design Considerations for Different Types of PCBs: Single Layer PCB, Multilayer PCB,
Flexible PCB, etc. Design Considerations for PCBs for Different Applications: Digital
Circuits, Analog Circuits, High Speed Circuits, Power Circuits, etc.
Layout Rules and Parameters. Design Rule Checks: Signal Layer Checks, Power / Ground
Checks, Solder Mask Check, Drill Check, etc.
Automated Processes, Through Hole Vs. SMT Technologies. Thermal Management for IC
and PCBs, Cooling Requirements, Electronic Cooling Methods.
Module 3: Electromagnetic Compatibility
Conducted Emission, Conducted Susceptibility, Radiated Emission, Radiated
Susceptibility, Common EMC Units, Practical Experiences and Concerns, Non-Ideal
Behavior of Electronic Components, FCC Regulations, CISPR / IEC Regulations,
Measurement of Radiated and Conducted Interference, Capacitive and Inductive Coupling,
Effect of Shield on Capacitive, Inductive and Magnetic Coupling, Shield Transfer
Impedance, Shielding Properties of Various Cable Configurations.
Grounding: Safety Grounds, Signal Grounds, Single-Point and Multipoint-Point Ground
Systems, Hybrid Grounds, Functional Ground Layout, Practical Low Frequency
Grounding, Hardware Grounds, Grounding of Cable Shields, Ground Loops, Common
Mode Choke, Shield Grounding at High Frequencies, Guarded Instruments.
29
EMC Components : EMI Suppression Cables, EMC Connectors, EMC Gaskets, Isolation
Transformers, Opto-Isolators.
Module 4: Electrostatic Discharge and Electronic Packaging
Electrostatic Discharge (ESD): Static Generation, Human Body Model, Static Discharge,
ESD Protection in Equipment Design, Transient and Surge Protection Devices, Software
and ESD Protection, ESD Vs. EMC, ESD Testing.
Functions of an Electronic Package: Packaging Hierarchy, Driving Forces on Packaging
Technology, Materials for Microelectronic Packaging, Material for High-Density
Interconnect Substrates, Electrical Anatomy of Systems Packaging, Signal Distribution,
Power Distribution, Electromagnetic Interference, Design Process.
References:
1. Michael Orshansky, Sani Nassif & Duane Boning, “Design for Manufacturability and
Statistical Design: Constructive Approach”, Springer, 2008.
2. Chiang, Charles, Kawa & Jamil “Design for Manufacturability and Yield for
Nano-Scale CMOS”, Springer, 2007.
3. Owen Molloy, Steven Tilley & Ernest Warman, “Design for Manufacturing and
Assembly: Concepts, Architectures and Implementation”, Springer, 1998.
4. Clyde F. Coombs, “Printed Circuits Handbook”, McGraw Hill, 2007.
5. Richard K. Ulrich &William D. Brown, “Advanced Electronic Packaging”, 2nd
Ed.,
Wiley, 2006.
6. Henry W. Ott, “Noise Reduction Techniques in Electronic Systems”, 2nd
Ed., Wiley,
1998.
7. Henry W Ott, “Electromagnetic Compatibility Engineering”, Wiley, 2009.
8. Prasad Kodali V., “Engineering Electromagnetic Compatibility: Principles,
Measurements, Technologies and Computer Models”, 2nd
Ed., Wiley, 2001.
30
MECAE 202 ANALOG AND DATA CONVERSION SYSTEM
DESIGN L T P C
3 1 0 4
Module 1: Linear Op-Amp Circuits
Review of Inverting and Non-Inverting Configurations, Current to Voltage and Voltage to
Current Converters, Current Amplifiers, Difference Amplifiers, Instrumentation Amplifier,
Input Offset Error, Compensation in Op-Amp Circuits, Op-Amp Noise, Noise Filtering.
Low Input Offset Voltage Op-Amps, Low Input Offset Current Op-Amps, Low Noise
Op-Amps, Amplifier Input Errors, Amplifier Output Errors,
Module 2: Dynamic Analog Circuits
Characteristics of MOSFET Switch, Sample and Hold Circuits: Sample and Hold / Track
and Hold Amplifiers, SHA / THA Performance Parameters, Types of SHA / THA.
Comparators: Characterization, Two-Stage Open-Loop Comparators, Discrete-Time
Comparators, High-Speed Comparators, Analog Multiplexers.
Switched Capacitor Circuits: Switched Capacitor Amplifiers, Switched Capacitor
Integrators, Models of Two-Phase Switched Capacitor Circuits, First and Second Order
Switched Capacitor Circuits, Switched Capacitor Filters.
Module 3: Data Converter Fundamentals and Architecture
Analog Vs. Discrete Time Signals, Specifications of Digital-to-Analog Converter (DAC),
Specifications of Analog-to-Digital Converter (ADC), Mixed-Signal Layout Issues.
DAC Architectures: Resistor-String DAC, Current-Steering DAC, Charge-Scaling DAC,
Cyclic DAC, Pipeline DAC. ADC Architectures: Flash ADC, Pipeline ADC, Integrating
ADC, Successive Approximation ADC, Oversampling ADC.
Module 4: Implementation of Data Converters
Implementation of DACs: R-2R Topologies for DACs, Current-Mode and Voltage-Mode
R-2R DAC, Wide-Swing Current-Mode R-2R DAC, Topologies without an OP-Amp.
Characteristics of Op-Amps used in Data Converters. Implementation of ADCs:
Implementing the Sample and Hold, Implementing Cyclic and Pipelined ADCs
Design of Multi Channel, Low Level and High Level, Data Acquisition Systems using
ADC / DAC, SHA and Analog Multiplexers.
31
References:
1. Franco S., “Design with Operational Amplifiers and Analog Integrated Circuits”,
3rd
Ed., McGraw Hill, 2002.
2. Philip E. Allen & Douglas R. Holberg, “CMOS Analog Circuit Design”, 2nd
Ed.,
Oxford University Press, 2009.
3. Jacob Baker R., “CMOS: Circuit Design, Layout, and Simulation”, Wiley, 2010.
4. David A. Johns & Ken Martin, “Analog Integrated Circuit Design”, Wiley India Pvt.
Ltd., 2008.
5. Walt Kester, “Mixed-Signal and DSP Design Techniques”, Newnes, Elsevier Science,
2003.
6. Walt Kester, “Analog-Digital Conversion”, Analog Devices Inc., 2004.
32
MECAE 203 HIGH SPEED DIGITAL SYSTEM DESIGN
L T P C
3 1 0 4
Module 1: Introduction to High Speed Digital Design
Frequency, Time and Distance; Capacitance and Inductance Effects; High Speed
Properties of Logic Gates; Speed and Power; Modelling of Wires: Geometry and
Electrical Properties of Wires, Electrical Models of Wires; Transmission Lines: Lossless
LC Transmission Lines, Lossy LRC Transmission Lines, Special Transmission Lines.
Module 2: Power Distribution and Noise
Power Supply Network, Local Power Regulation, IR Drops, Area Bonding, Onchip
Bypass Capacitors, Symbiotic Bypass Capacitors, Power Supply Isolation, Noise Sources
in Digital System: Power Supply Noise, Cross Talk, Intersymbol Interference.
Module 3: Signalling Convention and Circuits
Signalling Modes for Transmission Lines, Signalling over Lumped Transmission Media,
Signalling over RC Interconnect, Driving Lossy LC Lines, Simultaneous Bi-Directional
Signalling, Terminations, Transmitter and Receiver Circuits.
Module 4: Timing Convention and Synchronisation
Timing Fundamentals: Timing Properties of Clocked Storage Elements, Signals and
Events, Open Loop Timing Level Sensitive Clocking, Pipeline Timing, Closed Loop
Timing, Clock Distribution, Synchronization Failure and Metastability, PLL and DLL
Based Clock Aligners.
References:
1. William S. Dally & John W. Poulton, “Digital Systems Engineering”, Cambridge
University Press, 2008.
2. Howard Johnson & Martin Graham, “High Speed Digital Design: A Handbook of
Black Magic”, Prentice Hall, 1993.
3. Masakazu Shoji, “High Speed Digital Circuits”, Addison Wesley Publishing
Company, 1996.
4. Jan M. Rabaey, Anantha Chandrakasan & Borivoje Nikolic, “Digital Integrated
Circuits: A Design Perspective”, 2nd
Ed. Pearson Education Asia, 2007.
33
MECAE 204 DSP ALGORITHM AND ARCHITECTURE DESIGN
L T P C
3 1 0 4
Module 1: DSP Algorithm Design
DSP Representations (Data-Flow, Control-Flow, and Signal-Flow Graphs, Block
Diagrams), Fixed-Point DSP Design (A / D Precision, Coefficient Quantization,
Round-off and Scaling), Filter Structures (Recursive, Non-Recursive and Lattice),
Algorithmic Simulations of DSP Systems in C, Behavioral Modelling in HDL. System
Modeling and Performance Measures.
Module 2: Circuits and DSP Architecture Design
Fast Filtering Algorithms (Winograd's, FFT, Short-Length FIR), Retiming and Pipelining,
Block Processing, Folding, Distributed Arithmetic Architectures, VLSI Performance
Measures (Area, Power, and Speed), Structural Modeling in VHDL. Analog Signal
Processing for Fast Operation. Impact of Non Ideal Characteristics of Analog Functional
Blocks on the System Performance.
Module 3: DSP Module Synthesis
Distributed Arithmetic (DA), Advantages of Using DA, Size Reduction of Look-Up
Tables, Canonic Signed Digit Arithmetic, Implementation of Elementary Functions
Table-Oriented Methods, Polynomial Approximation Random Number Generators, Linear
Feedback Shift Register, High Performance Arithmetic Unit Architectures (Adders,
Multipliers, Dividers), Bit-Parallel, Bit-Serial, Digit-Serial, Carry-Save Architectures,
Redundant Number System, Modeling for Synthesis In HDL, Synthesis Place-And-Route.
Module 4: Parallel Algorithms and their Dependence
Applications to Some Common DSP Algorithms, System Timing using the Scheduling
Vector, Projection of the Dependence Graph using a Projection Direction, The Delay
Operator and Z-Transform Techniques for Mapping DSP Algorithms onto Processor
Arrays, Algebraic Technique for Mapping Algorithms, Computation Domain, Dependence
Matrix of a Variable, Scheduling and Projection Functions, Data Broadcast and Pipelining,
Applications using Common DSP Algorithms.
34
References:
1. Sen M. Kuo, Woon-Seng S. Gan, “Digital Signal Processors: Architectures,
Implementations, and Applications”, Prentice Hall, 2004.
2. Keshab K. Parhi, “VLSI Signal Processing Systems, Design and Implementation”,
John Wiley & Sons, 1999.
3. Uwe Meyer-Baese, “Digital Signal Processing with Field Programmable Gate Array”,
Springer- Verlag, 2001.
4. John G. Proakis & Dimitris Manolakis K. “DSP Principles, Algorithms and
Applications”, Prentice Hall, 1995.
5. Pirsch, “Architectures for Digital Signal Processing”, John Wiley & Sons, 1998.
6. Lars Wanhammar, “DSP Integrated Circuits”, Academic Press, 1999.
7. Parhami & Behrooz “Computer Arithmetic: Algorithms and Hardware Designs”,
Oxford University Press, 2000.
8. Israel Koren & A. K. Peters, “Computer Arithmetic Algorithms”, Natick, 2002.
35
MECAE 205 - 1 WIRELESS COMMUNICATION SYSTEM
DESIGN L T P C
3 0 0 3
Module 1: Fading and Diversity
Wireless Channel Models: Path Loss and Shadowing Models, Statistical Fading Models,
Narrow Band and Wideband Fading Models, Review of Performance of Digital
Modulation Schemes over Wireless Channels.
Diversity: Time Diversity, Frequency and Space Diversity, Receive Diversity, Concept of
Diversity Branches and Signal Paths, Performance Gains; Combining Methods: Selective
Combining, Maximal Ratio Combining, Equal Gain Combining, Performance Analysis for
Rayleigh Fading Channels.
Module 2: Cellular Communication
Cellular Networks; Multiple Access: FDMA, TDMA, Spatial Reuse, Co-Channel
Interference Analysis, Hand-off, Erlang Capacity Analysis, Spectral Efficiency and Grade
of Service, Improving Capacity: Cell Splitting and Sectorization.
Module 3: Spread Spectrum and CDMA
Direct Sequence Spread Spectrum (DS-SS), Frequency Hopping Spread Spectrum
(FH-SS), ISI and Narrow Band Interference Rejection, Code Design- Maximal Length
Sequences, Gold Codes, Design of SS Transmitters.
Diversity in DS-SS Systems, Rake Receiver, Performance Analysis, CDMA Systems:
Interference Analysis for Broadcast and Multiple Access Channels, Capacity of Cellular
CDMA Networks, Reverse Link Power Control, Hard and Soft Hand-off Strategies,
Design of SS Receivers.
Module 4: Capacity and Standards
Capacity of Wireless Channels: Capacity of Flat and Frequency Selective Fading
Channels.
Cellular Wireless Communication Standards: Overview of Second Generation Cellular
Wireless Systems: GSM and IS-95 Standards, 3G Systems: UMTS & CDMA 2000
Standards and Specifications, Vision of 4G Standards.
36
References:
1. Andrea Goldsmith, “Wireless Communications”, Cambridge University press, 2006.
2. Rappaport T. S., “Wireless Communication, principles & practice”, Prentice Hall of
India, 2002.
3. Simon Haykin & Michael Moher, “ Modern Wireless Communications”, Person
Education, 2007.
4. Stuber G. L, “Principles of Mobile Communications”, 2nd
Ed., Kluwer Academic
Publishers, 2001.
5. Peterson R. L, Ziemer R. E. & David E. Borth, “Introduction to Spread Spectrum
Communication”, Pearson Education, 1995.
6. Viterbi A. J., “CDMA: Principles of Spread Spectrum”, Addison Wesley, 1995.
37
MECAE 205 -2 RF INTEGRATED CIRCUIT DESIGN L T P C
3 0 0 3
Module 1: Elements of Microwave Integrated Circuits (MIC)
Planar Transmission Line, Lumped Element for MIC, Substrate for MIC, Hybrid
Technology: Thin Film, Thick Film and Mid Film Technologies. Monolithic Technology.
Planar Transmission Lines, Method of Analysis TEM Analysis, Method of Conformal
Transformation, Variational Approach, Transverse Transmission Line Technique. Finite
Difference Method.
Module 2: Microwave Integrated Subassemblies
Salient Features of MICs, Characteristics and Properties of Substrate, Conductor,
Dielectric and Resistive Materials, MMIC Fabrication Techniques, Diffusion and Ion
Implantation, Oxidation and Film Deposition, Epitaxial Growth, Lithography, Etching and
Photo Resist, Deposition Methods, Steps Involved in the Fabrication of MOSFET.
Module 3: RF IC Design Flow
System Design and Behavioral Modelling, Schematic Entry and Design Environment,
Time and Frequency Domain Circuit Simulation, Layout, Electromagnetic Extraction,
Parasitic Extraction, DRC and LVS, Verification in System Bench.
RFIC Layout, RFIC Packaging and System Integration, System Design Considerations:
Packaging, Power, Heat Dissipation, Parameter Tradeoffs.
Module4: Coupled Microstrip, Directional Couplers
Introduction to Coupled Microstrip, Even and Odd Mode Analysis, Directional Couplers,
Branch Line Coupler.
References:
1. Frank Ellinger, “Radio Frequency Integrated Circuits and Technologies”, Springer,
2007.
2. Gupta K. C. & Amarjit Singh, “Microwave Integrated Circuits" John Wiley & Sons,
1975.
3. Hoffman R. K., “Handbook of Microwave Integrated Circuits”, Artech House
Publishers, 1987.
4. Leo G. Maloratsky, “Passive RF & Microwave Integrated Circuits”, Elsevier, 2004.
38
5. Joseph J. Carr, “RF Components and Circuits”, Newnes, 2002.
6. Inder Bahl, “Lumped Elements for RF and Microwave Circuits”, Artech House, 2003.
39
MECAE 205 - 3 DSP SYSTEM DESIGN L T P C
3 0 0 3
Module 1: Introduction
Need for Special Digital Signal Processors, Processor Trends: Von Newmann Vs. Harvard
Architecture, Architectures of Superscalar and VLIW Fixed and Floating Point Processors,
New Digital Signal Processing Hardware Trends, Selection of DS Processors.
Module 2: Typical DS Processor
Introduction to a Popular DSP from Texas Instruments (TMS330C6000 Series), CPU
Architecture, CPU Data Paths and Control, Internal Data / Program Memory. On Chip
Peripherals: Timers, Multi Channel Buffered Serial Ports, Extended Direct Memory
Access, Interrupts, Pipelining.
Module 3: Filter Design Techniques
Design Aspects: Introduction to the C6713 DSK, Code Composer Studio IDE, Matlab and
Basic Skills, Review of FIR Filtering: FIR Filter Design Techniques and Tools, Review of
IIR Filtering: IIR Filter Design Techniques and Tools, Sampling, Quantization and
Working with the AIC23 Codec, Writing Efficient Code: Optimizing Compiler, Effect of
Data Types and Memory Map: TMS320C6713 Assembly Language Programming:
Instructions Set And Addressing Modes, Linear Assembly.
Module 4: Current Trends
Current Trend in Digital Signal Processors: DSP Controllers, Architecture of
TMS320C28XX Series DSP and its Applications. Architecture Trends of Other Texas
Instruments DSP Processors, Analog Devices DS Processors: Introduction to Sharc / Tiger
Sharc / Blackfin Series, Other Major Vendors in the DSP Market and the Latest Trends.
References:
1. Online TI Materials for the TI C6713 DSK Board: http://www.ti.com
2. User's Manuals of Various Fixed and Floating Point DS Processors.
3. Naim Dahnoun, “Digital Signal Processing Implementation Using the TMS320C6000
Processors”, Prentice Hall, 2000.
4. Chassaing R., “Digital Signal Processing and Applications With the C6713 and C6416
DSK”, John Wiley & Sons, 2004.
40
5. Sen M. Kuo & Woon-Seng Gan, “Digital Signal Processors: Architectures,
Implementations, and Applications”, Pearson, 2005.
6. David J. De Fatta, Joseph G. Lucas & William S. Hodgkiss, “Digital Signal
Processing: A System Design Approach”, Wiley India, 2009.
7. Oppenheim A. V. & Schafer R. W., “Discrete-Time Signal Processing”, 2nd
Ed.,
Prentice Hall, 1989.
8. John G. Proakis & Dimitris G. Manolakis, “Digital Signal Processing: Principles,
Algorithms and Applications”, 4th
Ed., Pearson, 2007.
41
MECAE 205 - 4 ASIC DESIGN L T P C
3 0 0 3
Module 1: Types of Asics
Design Flow, Economics of Asics, ASIC Cell Libraries, CMOS Logic Cell Data Path
Logic Cells, I / O Cells, Cell Compilers.
Module 2: ASIC Library Design
Transistors as Resistors, Parasitic Capacitance, Logical Effort Programmable ASIC
Design Software: Design System, Logic Synthesis, Half Gate ASIC, ASIC Construction,
Floor Planning & Placement, Routing.
Module 3: System on Chip Design Process
A Canonical SoC Design, SoC Design Flow, Waterfall Vs. Spiral, Top-Down Vs.
Bottom-Up, Specification Requirements, Types of Specifications, System Design Process,
System Level Design Issues, Soft IP Vs. Hard IP, Design for Timing Closure, Logic
Design Issues, Physical Design Issues, Verification Strategy, On-Chip Buses and
Interfaces, Low Power, Manufacturing Test Strategies, MPSoCs, Techniques for
Designing MPSoCs.
Module 4: Soc Verification
Verification Technology Options, Verification Methodology, Verification Languages,
Verification Approaches, and Verification Plans. System Level Verification, Block Level
Verification, Hardware / Software Co-Verification, and Static Net List Verification.
References:
1. Michael John Sebastian Smith, “Application Specific Integrated Circuits”, Pearson
Education India, 2008.
2. Farzad Nekoogar , Faranak Nekoogar & Jeffrey Ebert, “From ASICs to SOCs: A
Practical Approach”, Prentice Hall, 2003.
42
MECAE 206 - 1 OPTICAL COMMUNICATION SYSTEM DESIGN L T P C
3 0 0 3
Module 1: Review of Fiber Optic Communication Systems
Evolution, Benefits and Disadvantages of Fiber Optics, Transmission Windows,
Transmission through Optical Fiber, The Numerical Aperture (NA), The Optical Fiber,
Types of Fiber, Different Losses and Issues in Fiber Optics, Attenuation, Dispersion,
Connectors and Splices, Bending Loses, Absorption, Scattering, Very Low Loss Materials,
Plastic and Polymer-Clad-Silica Fibers, Wave Propagation in Step Index and Graded
Index Fiber, Fiber Dispersion, Single Mode Fibers, Multimode Fibers, Dispersion Shifted
Fiber, Dispersion Flattened Fiber, Polarization, Cut-Off Condition and V-Parameter.
Light Sources and Transmitters, Detectors and Receivers.
Module 2: Fiber Optic System Design Considerations and Components
Indoor Cables, Outdoor Cables, Cabling Example, Power Budget, Bandwidth and Rise
Time Budgets, Electrical and Optical Bandwidth, Connectors, Fiber Optic Couplers.
Optical Fiber Communication System: Telecommunication, Local Distribution Series,
Computer Networks, Local Data Transmission, Digital Optical Fiber Communication
System, First and Second-Generation System, Future Systems. Noise Sources, Channel
Impairments, and Optical Transmission System Design.
Module 3: Advanced Multiplexing Strategies
Optical TDM, Subscriber Multiplexing (SCM), WDM and Hybrid Multiplexing Methods;
Network Element Technology: (D)WDM Technology; Gratings, Filters, Passive and
Active Devices, Signal Processors, Gain Equalizer, Power Splitter, Combiner, Coupler,
Optical Switching and Routing; Space, Time, and Wavelength Granularity, Add / Drop
Mux, Advanced Optical Signal Processing, Functions of Photonic Integrated Circuits,
Advanced Modulation Formats, OFDM, Polarization Multiplexing, Constrained Coding,
and Coherent Detection.
Module 4: Optical Networking
Data Communication Networks, Network Topologies, MAC Protocols, Network
Architecture: SONET / TDH, Optical Transport Network, Optical Access Network,
Optical Premise Network. Broadcast and Select WDM Concepts, Wavelength Routed
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Protocols, Performance of WDM + EDFA Systems, Solitons, Optical CDMA,
Introduction to IP Over WDM, Optical Packet Switching, Optical Burst Switching,
Optical Switch Fabrics OSFs and their Application.
References:
1. John Senior, “Optical Fiber Communications: Principles and Practice”, 3rd
Ed.,
Prentice Hall, 2008.
2. Optical Society of America, “Fiber Optics Handbook: Fiber, Devices, and Systems for
Optical Communications”, McGraw Hill, 2001.
3. Iizuka K., “Elements of Photonics”, Volume II, Wiley, 2002.
4. Shieh W., & Djordjevic I., “OFDM for Optical Communications”, Elsevier, 2009.
5. Javier Aracil, “Enabling Optical Internet with Advanced Network Technologies”,
Springer, 2009.
6. Masataka Nakazawa, “High Spectral Density Optical Communication Technologies”,
Springer, 2010.
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MECAE 206 - 2 RF AND MICROWAVE NETWORK DESIGN L T P C
3 0 0 3
Module1: Microwave Network Analysis
Equivalent Voltages and Currents, Concept of Impedance, Impedance and Admittance
Matrices of Microwave Junctions, Scattering Matrix Representation of Microwave
Networks, Microwave One-Port Network, Symmetry of Input Impedance and Reflection
Coefficient, N-Port Microwave Network, Generalized Scattering Parameters, Definition of
Scattering Matrix, Properties of the Scattering Matrix, S-Parameters at Arbitrary Planes,
Transmission (ABCD) Matrix, Equivalent Circuits for Two-Port Networks, Signal Flow
Graphs, Scattering Matrix of a Two Port Network, Salient Features of S-Matrix, Salient
Features of Multiport Network, Losses in Microwave Circuits, Return Loss, Insertion
Loss, Transmission Loss, Reflection Loss, Impedance Matrix, Short Circuit Admittance
Parameters of a Π-Network, S-Matrix of Series Element in the Transmission Line,
S-Matrix for E-Plane Tee Junction, S-Matrix for H-Plane Tee Junctions,
Module 2: Analysis of Symmetrical Networks
Introduction, Magnitude Theorem For 2-Port Passive Lossless Circuits, Determinate
Theorem For 2-Port Passive Lossless Circuits, Simultaneous Conjugate Match Theorem
for A 2-Port Passive Lossless Circuit, Input and Output Matching Network Theorem,
Lumped-Element Matching Networks, Distributed-Element Matching Networks,
Bandwidth Considerations for Matching Networks,
Module 3: Power Dividers and Couplers
Scattering Matrix of 3-Port and 4-Port Junctions, T-Junction Power Divider, Wilkinson
Power Divider, Input Considerations, Mode Decomposition, Even Mode, Odd Mode and
Layout.
Qualitative Description of Two-Hole and Multi-Hole Waveguide Couplers, Hybrid
Junctions.
Directional Couplers: Performance Measures, Coupler Scattering Matrix, Types of 4-Port
Couplers, Coupler Applications, Even and Odd Mode Analysis. Branchline Coupler: Even
and Odd Mode Decomposition, Even and Odd Mode Analysis. Parallel Line Coupler:
S-Parameter Determination, Mode Decomposition: Even Mode, Odd Mode, Performance
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Comparison. Directivity Enhancement Techniques for Microstrip Parallel Line Couplers:
Analysis, Design Procedure, Lang Couplers.
Module 4: Ferrimagnetic Components
Microwave Ferrites, Permeability Tensor, Wave Propagation in Ferrite Medium, Faraday
Rotation, Birefringence, Ferrite Loaded Waveguides, Ferrite Circulators, Isolators and
Phase Shifters.
References:
1. David M. Pozzar, “ Microwave Engineering”, Wiley India, 2007.
2. Leo G Maloratsky, “Passive RF & Microwave Integrated Circuits”, Elsevier, 2004.
3. Hee-Ran Ahn, “Asymmetric Passive Components in Microwave Integrated Circuits”,
John Wiley & Sons, 2006.
4. Sorrentino R. & Bianchi G., “Microwave and RF Engineering,” John Wiley, 2010.
5. Joseph J. Carr, “RF Components and Circuits “, Newnes, 2002.
6. Guillermo Gonzalez, “Microwave Transistor Amplifiers: Analysis and Design”,
2nd
Ed., Prentice Hall, 1997.
7. Robert E. Collin, “Foundations for Microwave Engineering”, 2nd
Ed., McGraw Hill,
1992.
46
MECAE 206 - 3 DETECTION AND TRACKING SYSTEM DESIGN L T P C
3 0 0 3
Module 1: Reception in White Noise
Introduction, The Active Radar or Sonar Signal, Physical Interpretation, Passive Listening,
Optimum Reception in White Noise: Principle, Estimation of a Parameter, Simultaneous
Estimation of Several Parameters, Optimum Detection, Optimum Receiver, Optimum
Detector, The Ambiguity Function, Detection Performance.
Module 2: Reception in Colored Noise
Optimum Reception in Colored Noise, Receiver Structure, Application to Spurious Echoes
or Jammers, Stationary Colored Noise and Infinite Observation Time, Adaptive
Processing, Adaptive Filtering using a Transversal Filter, Adaptive Whitening, Sensor
Arrays, Space-time Processing, Passive Listening, MUSIC.
Module 3: Tracking
Modeling Detection and Tactical Decision Aids, Cumulative Probability of Detection,
Tracking Target Motion Analysis and Localization, Design and Evaluation of Sonars and
Radars.
Module 4: Digital Sonar System
Design of Digital Sonar: Implementation Method of Various Function of Digital Sonar,
System Simulation Technique in Digital Sonar Design, Examples of Typical Modern
Digital Sonar.
References:
1. François Le Chevalier, “Principles of Radar and Sonar Signal Processing”, Artech,
2002.
2. Richard P. Hodges, “Underwater Acoustics: Analysis, Design and Performance of
Sonar”, Wiley, 2010.
3. Li Qihu, “Digital Sonar Design in Underwater Acoustics”, Springer, 2011.
4. Samuel S. Blackman & Robert Popoli, “Design and Analysis of Modern Tracking
Systems”, Artech, 1999.
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MAE 206 - 4 EMBEDDED NETWORK DESIGN L T P C
3 0 0 3
Module 1: Programming for Embedded Systems
Pointers and Memory Mapping in Operating System. C Internals. RTOS: OS Basics, OS:
Ucos2, Linux, Linux Internals, OS Compilation and Optimization. Real Time OS Kernel
Architecture, Scheduling Algorithms: Priority Based, Shortest Job First, Round-Robin,
FIFO, etc. Task Synchronization: Mutual Exclusion, Semaphores. Embedded Operating
Systems, Mobile Operating Systems, Porting RTOS or EOS on a Hardware Platform.
Module 2: Embedded Communication Systems
Standards for Embedded Communication, USART, SPI, 12C, CAN, USB, Firewire,
Ethernet, Wireless Communications like IrDA, Bluetooth, 802.11, etc., Security Issues in
Embedded Communication.
Writing Codes for Serial Communication in C or CPP, MP3 Decoding Using C, Java
Enabled Information Appliances, Mobile Java Application (Jini), Embedded Database
Applications, Voice-Over IP.
Module 3: Device Drivers
Recapitulation of Kernel Mechanisms; Character Drivers, Block Drivers, Network
Drivers, Device Driver and Networking Stack Development. Device Driver Development
on Linux.
Protocol Implementation On Microcontroller And Processors: Device Awareness:
PIC, 8051, AVR, ARM-7, Configuring Network Devices, WLAN Authentication and Data
Transfer Protocols: TCP / IP 80211.A, 80211.B, 80211.G, Encryption Protocols.
Module 4: Automotive Networked Embedded Systems
Trends, Time Triggered Communication, CAN for Embedded Systems, LIN Standard,
System Software for Automotive Applications.
Networked Embedded Systems in Industrial Automation: Fieldbus Systems,
Real-Time Ethernet, WLAN and WPAN for Industrial Environments.
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References:
1. Gregory J. Pottie & William J. Kaiser, “Principles of Embedded Networked Systems
Design”, Cambridge University Press, 2009.
2. Richard Zurawski, “Embedded Systems Handbook, Second Edition: Networked
Embedded Systems”, CRC Press, 2009.
3. Dreamtech Software Team, “Programming for Embedded Systems: Cracking the
Code”, 2009.
4. John Catsoulis, “Designing Embedded Hardware”, 2nd
Ed., O’reilly Media, 2005.
5. Daniel Wesley Lewis, “Fundamentals of Embedded Software: Where C and Assembly
Meet”, PHI Learning, 2009.
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MECAE 207 ELECTRONIC SYSTEM DESIGN LAB -II L T P C
0 0 3 2
System simulation experiments based on the courses MECAE 201, MECAE 202,
MECAE 203, MECAE 204 and the elective courses opted by the student in the second
semester.
MECAE 208 SEMINAR – II L T P C
0 0 2 1
Each student shall present a seminar on any topic of interest related to the core / elective
courses offered in the second semester of the M. Tech. Programme. He / she shall select
the topic based on the references from international journals of repute, preferably IEEE
journals. They should get the paper approved by the Programme Co-ordinator / Faculty
member in charge of the seminar and shall present it in the class. Every student shall
participate in the seminar. The students should undertake a detailed study on the topic and
submit a report at the end of the semester. Marks will be awarded based on the topic,
presentation, participation in the seminar and the report submitted.
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MECAE 301 INDUSTRIAL TRAINING AND /OR
MINIPROJECT L T P C
0 0 20 10
The student shall undergo
i) An Industrial Training of 12 weeks duration in an industry / company / institution
approved by the institute under the guidance of a staff member in the concerned field.
At the end of the training he / she have to submit a report on the work being carried
out.
OR
ii) An Industrial Training of 1 month duration and Mini Project of 2 months duration in
an industry / company / institution approved by the institute under the guidance of a
staff member in the concerned field. At the end of the training he / she have to submit
a report on the work being carried out.
MECAE 302 MASTER’S THESIS PHASE - I L T P C
0 0 10 5
The thesis (Phase - I) shall consist of research work done by the candidate or a
comprehensive and critical review of any recent development in the subject or a detailed
report of project work consisting of experimentation / numerical work, design and or
development work that the candidate has executed.
In Phase - I of the thesis, it is expected that the student should decide a topic of thesis,
which is useful in the field or practical life. It is expected that students should refer
national & international journals and proceedings of national & international seminars.
Emphasis should be given to the introduction to the topic, literature survey, and scope of
the proposed work along with some preliminary work / experimentation carried out on the
thesis topic. Student should submit two copies of the Phase - I thesis report covering the
content discussed above and highlighting the features of work to be carried out in
Phase – II of the thesis. Student should follow standard practice of thesis writing. The
candidate will deliver a talk on the topic and the assessment will be made on the basis of
the work and talks there on by a panel of internal examiners one of which will be the
internal guide. These examiners should give suggestions in writing to the student to be
incorporated in the Phase – II of the thesis.
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MECAE 401 MASTER’S THESIS L T P C
0 0 30 15
In the fourth semester, the student has to continue the thesis work and after successfully
finishing the work, he / she have to submit a detailed thesis report. The work carried out
should lead to a publication in a National / International Conference. They should have
submitted the paper before M. Tech. evaluation and specific weightage should be given to
accepted papers in reputed conferences.
MECAE 402 MASTER’S COMPREHENSIVE VIVA
A comprehensive viva-voce examination will be conducted at the end of the fourth
semester by an internal examiner and external examiners appointed by the university to
assess the candidate’s overall knowledge in the respective field of specialization.