+ All Categories
Home > Documents > Synplify Userguide

Synplify Userguide

Date post: 02-Jun-2018
Category:
Upload: behnam5670
View: 381 times
Download: 0 times
Share this document with a friend

of 278

Transcript
  • 8/10/2019 Synplify Userguide

    1/278

    Synplify Pro

    User Guide and TutorialFebruary 2001

    Synplicity, Inc.

    935 Stewart Drive

    Sunnyvale, CA 94085

    408.215.6000 direct

    408.990.0290 fax

    www.synplicity.com

    http://www.synplicity.com/support/index.htmlhttp://www.synplicity.com/support/index.html
  • 8/10/2019 Synplify Userguide

    2/278

    LO

    Preface

    ii Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    Preface

    Disclaimer of WarrantySynplicity, Inc. makes no representations or warranties, either expressed

    or implied, by or with respect to anything in this manual, and shall not be

    liable for any implied warranties of merchantability or fitness for a partic-

    ular purpose of for any indirect, special or consequential damages.

    Copyright Notice

    Copyright 1994-2001 Synplicity, Inc. All Rights Reserved.

    Synplicity software products contain certain confidential information of

    Synplicity, Inc. Use of this copyright notice is precautionary and does not

    imply publication or disclosure. No part of this publication may be repro-

    duced, transmitted, transcribed, stored in a retrieval system, or trans-

    lated into any language in any form by any means without the prior

    written permission of Synplicity, Inc. While every precaution has been

    taken in the preparation of this book, Synplicity, Inc. assumes no respon-

    sibility for errors or omissions. This publication and the features

    described herein are subject to change without notice.

    Trademarks

    Synplicity, the Synplicity S logo, Behavior Extracting Synthesis

    Technology, Embedded Synthesis, HDL Analyst, SCOPE, Simply Better

    Results, Simply Better Synthesis, Synplify, and Synthesis Constraint

    Optimization Environment are registered trademarks of Synplicity, Inc.

    Amplify, B.E.S.T., Certify, DST, Direct Synthesis Technology, Partition-

    Driven Synthesis, and Physical Optimizer are trademarks of

    Synplicity, Inc.

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://www.synplicity.com/support/index.htmlhttp://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    3/278

    Preface

    Synplify Pro User Guide, February 2001 iii

    Go BackIndexRelated

    Documents1st Page

    Verilog is a registered trademark of Cadence Design Systems, Inc. IBM

    and PC are registered trademarks of International Business Machines

    Corporation. Microsoft is a registered trademark of Microsoft Corporation.

    Sun, SPARC, Solaris, and SunOS are trademarks of Sun Microsystems,

    Inc. UNIX is a registered trademark of UNIX Systems Laboratories, Inc. Allother product names mentioned herein are the trademarks or registered

    trademarks of their respective owners.

    Restricted Rights Legend

    Government Users: Use, reproduction, release, modification, or disclosure

    of this commercial computer software, or of any related documentation of

    any kind, is restricted in accordance with FAR 12.212 and DFARS

    227.7202, and further restricted by the Synplicity Software License Agree-

    ment. Synplicity, Inc., 935 Stewart Drive, Sunnyvale, CA 94086, U.S.A

    Printed in the U.S.A

    February 2001

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    4/278

    LO

    Preface

    iv Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    Synplify Pro Software License Agreement

    Important! READ CAREFULLY BEFORE PROCEEDING

    This is a legal agreement between you, the user (Licensee) and Synplicity, Inc.(Synplicity) regarding the software program that is attached to or enclosed withthis software license agreement, or that is the subject of this documentation (theSOFTWARE). The term SOFTWARE also includes related documentation(whether in print or electronic form) and, if Licensee is obtaining an update, anypre-existing software and data provided within earlier software releases (to theextent such earlier software and data is retained by, embodied in or in any wayused or accessed by the upgraded SOFTWARE provided with this Agreement). IfLicensee is a participant in the University Program or has been granted anEvaluation License, then some of the following terms and conditions may notapply (refer to the sections entitled, respectively, Evaluation LicenseandUniversity Program, below).

    By opening the packaging of the SOFTWARE, or by installing or using theSOFTWARE, Licensee agrees to be bound by the terms of this Software LicenseAgreement (the Agreement). If Licensee does not agree to the terms of thisAgreement, then do not install the SOFTWARE and return the copy of theSOFTWARE to the place from which you obtained it.

    Evaluation License. The following applies, in addition to the other terms andconditions and as a limit on the license, if Licensee has obtained an EvaluationLicense. If Licensee has obtained the SOFTWARE pursuant to an evaluationlicense, then the following additional terms, conditions, and restrictions apply:(a) The license to the SOFTWARE terminates after 20 days (unless otherwise

    agreed to in writing by Synplicity); and (b) Licensee may use the SOFTWARE onlyfor the sole purpose of tests and other evaluation to determine whether Licenseewishes to license the SOFTWARE on a commercial basis. Licensee shall not usethe SOFTWARE to design any integrated circuits for production or pre-production purposes or any other commercial use including, but not limited to,for the benefit of Licensees customers. If Licensee breaches any of the foregoingrestrictions, then Licensee shall pay to Synplicity a license fee equal toSynplicitys standard license fee for the commercial version of the SOFTWARE.

    License. Synplicity grants to Licensee, a non-exclusive right to install theSOFTWARE and to use or authorize use of the SOFTWARE by up to the numberof nodes for which Licensee has a license and for which Licensee has the securitykey(s) or authorization code(s) provided by Synplicity or its agents. All

    SOFTWARE must be used within the country for which the systems werelicensed and at Licensee's site (contained within a one kilometer radius);however, remote use is permitted by employees who work at the site but aretemporarily telecommuting to that same site from less than 50 miles away (forexample, an employee who works at a home office on occasion). In addition,Synplicity grants to Licensee a non-exclusive license to copy and distributeinternally the documentation portion of the SOFTWARE in support of its licenseto use the program portion of the SOFTWARE.

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    5/278

    Preface

    Synplify Pro User Guide, February 2001 v

    Go BackIndexRelated

    Documents1st Page

    Copy Restrictions. This SOFTWARE is protected by United States copyright lawsand international treaty provisions and copying not in accordance with thisAgreement is forbidden. Licensee may copy the SOFTWARE only as follows: (i) todirectly support authorized use under the license and (ii) in order to make a copyof the SOFTWARE for backup purposes. Copies must include all copyright and

    trademark notices.Use Restrictions. This SOFTWARE is licensed to Licensee for internal use only.Licensee shall not (and shall not allow any third party to): (i) decompile,disassemble, reverse engineer or attempt to reconstruct, identify or discover anysource code, underlying ideas, underlying user interface techniques oralgorithms of the SOFTWARE by any means whatever, or disclose any of theforegoing; (ii) provide, lease, lend, or use the SOFTWARE for timesharing orservice bureau purposes, on an application service provider basis, or otherwisecircumvent the internal use restrictions; (iii) modify, incorporate into or withother software, or create a derivative work of any part of the SOFTWARE; (iv)disclose the results of any benchmarking of the SOFTWARE, or use such resultsfor its own competing software development activities, without the prior written

    permission of Synplicity; or (v) attempt to circumvent any user limits, maximumgate count limits or other license, timing or use restrictions that are built into theSOFTWARE.

    Transfer Restrictions. Licensee shall not sublicense, transfer or assign thisAgreement or any of the rights or licenses granted under this Agreement, exceptin the case of a merger or sale of all or substantially all of Licensees assets.

    Ownership of the SOFTWARE. Synplicity retains all right, title, and interest inthe SOFTWARE (including all copies), and reserves all rights not expresslygranted to Licensee. This License is not a sale of the original SOFTWARE or ofany copy.

    Ownership of Design Techniques. Design means the representation of an

    electronic circuit or device(s), derived or created by Licensee through the use ofthe SOFTWARE in its various formats, including, but not limited to, equations,truth tables, schematic diagrams, textual descriptions, hardware descriptionlanguages, and netlists. Design Techniques means the Synplicity-supplied data,circuit and logic elements, libraries, algorithms, search strategies, rule bases,and technical information incorporated in the SOFTWARE and employed in theprocess of creating Designs. Synplicity retains all right, title and interest in and toDesign Techniques incorporated into the SOFTWARE, including all intellectualproperty rights embodied therein. Licensee acknowledges that Synplicity is in thebusiness of licensing SOFTWARE which incorporates Design Techniques.Licensee agrees that in the event Licensee voluntarily discloses any designtechniques to Synplicity without designating such as Licensees ConfidentialInformation, Synplicity has an unrestricted, royalty-free right to incorporatethose Design Techniques into its software, documentation and other products,and to sublicense third parties to use those incorporated design techniques.

    Protection of Confidential Information. Confidential Information means (i)the source code of the SOFTWARE, and any included trade secrets (including anytechnology, idea, algorithm or information contained in the SOFTWARE, andspecifically including Design Techniques); (ii) either partys product plans,

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    6/278

    LO

    Preface

    vi Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    designs, costs, prices and names; non-published financial information;marketing plans; business opportunities; personnel; research; development orknow-how; (iii) any information designated by the disclosing party as confidentialin writing or, if disclosed orally, designated as confidential at the time ofdisclosure and reduced to writing and given to the receiving party and designated

    as confidential in writing within 30 days; and (iv) the terms and conditions of thisAgreement; provided, however that Confidential Information will not includeinformation that: (a) is or becomes generally known or available by publication,commercial use or otherwise through no fault of the receiving party; (b) is knownand has been reduced to tangible form by the receiving party at the time ofdisclosure and is not subject to restriction; (c) is independently developed by thereceiving party without use of the disclosing partys Confidential Information; (d)is lawfully obtained from a third party who has the right to make suchdisclosure; or (e) is released for publication by the disclosing party in writing.

    Each party will protect the others Confidential Information from unauthorizeddissemination and use with the same degree of care that each such party uses toprotect its own like information. Neither party will use the others Confidential

    Information for purposes other than those necessary to directly further thepurposes of this Agreement. Neither party will disclose to third parties the othersConfidential Information without the prior written consent of the other party.

    Termination. Synplicity may terminate this Agreement in the event of breach ordefault by Licensee. Upon termination Licensee will relinquish all rights underthis Agreement, and must cease using the SOFTWARE and return or destroy allcopies (and partial copies) of the SOFTWARE and documentation.

    Export. Licensee shall not allow the Synplicity SOFTWARE to be sent or used inany country except in compliance with applicable U. S. laws and regulations.

    Limited Warranty and Disclaimer. Synplicity warrants that the programportion of the SOFTWARE will perform substantially in accordance with the

    accompanying documentation for a period of 90 days from the date of receipt.Synplicitys entire liability and Licensees exclusive remedy for a breach of thepreceding limited warranties shall be, at Synplicitys option, either (a) return ofthe license fee, or (b) providing a fix, patch, work-around, or replacement of theSOFTWARE that does not meet such limited warranty. In either case, Licenseemust return the SOFTWARE to Synplicity with a copy of the purchase receipt orsimilar document. Replacements are warranted for the remainder of the originalwarranty period or 30 days, whichever is longer. Some states/jurisdictions donot allow limitations on duration of an implied warranty, so the above limitationmay not apply. EXCEPT AS EXPRESSLY SET FORTH ABOVE, NO OTHERWARRANTIES OR CONDITIONS, EITHER EXPRESS OR IMPLIED, ARE MADE BYSYNPLICITY WITH RESPECT TO THE SOFTWARE AND THE ACCOMPANYINGDOCUMENTATION (STATUTORY OR OTHERWISE), AND SYNPLICITYEXPRESSLY DISCLAIMS ALL WARRANTIES AND CONDITIONS NOT EXPRESSLYSTATED HEREIN, INCLUDING BUT NOT LIMITED TO THE IMPLIEDWARRANTIES OR CONDITIONS OF MERCHANTABILITY, NONINFRINGEMENT,AND FITNESS FOR A PARTICULAR PURPOSE. SYNPLICITY DOES NOTWARRANT THAT THE FUNCTIONS CONTAINED IN THE SOFTWARE WILL MEETLICENSEES REQUIREMENTS, BE UNINTERRUPTED OR ERROR FREE, OR

    THAT ALL DEFECTS IN THE PROGRAM WILL BE CORRECTED. Licensee

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    7/278

    Preface

    Synplify Pro User Guide, February 2001 vii

    Go BackIndexRelated

    Documents1st Page

    assumes the entire risk as to the results and performance of the SOFTWARE.Some states/jurisdictions do not allow the exclusion of implied warranties, so theabove exclusion may not apply.

    Limitation of Liability. IN NO EVENT SHALL SYNPLICITY OR ITS AGENTS BE

    LIABLE FOR ANY INDIRECT, SPECIAL, CONSEQUENTIAL OR INCIDENTALDAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FORLOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTIONS, LOSS OFBUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OUT OF

    THE USE OF OR INABILITY TO USE THESE SYNPLICITY PRODUCTS, EVEN IFSYNPLICITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Inno event will Synplicity be liable to Licensee for damages in an amount greaterthan the fees paid for the use of the SOFTWARE. Some states/jurisdictions donot allow the limitation or exclusion of incidental or consequential damages, sothe above limitations or exclusions may not apply.

    Intellectual Property Right Infringement. If a claim alleging infringement of anintellectual property right arises concerning the SOFTWARE (including but notlimited to patent, trade secret, copyright or trademark rights), Synplicity in itssole discretion may elect to defend or settle such claim. Synplicity in the event ofsuch a claim may also in its sole discretion elect to terminate this Agreement andall rights to use the SOFTWARE, and require the return or destruction of theSOFTWARE, with a refund of the fees paid for use of the SOFTWARE less areasonable allowance for use and shipping.

    Miscellaneous. If Licensee is a corporation, partnership or similar entity, thenthe license to the Software that is granted under this Agreement is expresslyconditioned upon acceptance by a person who is authorized to sign for and bindthe entity. This Agreement is the entire agreement between Licensee andSynplicity with respect to the license to the SOFTWARE, and supersedes anyprevious oral or written communications or documents (including, if you areobtaining an update, any agreement that may have been included with the initialversion of the Software). This Agreement is governed by the laws of the State ofCalifornia, USA. This Agreement will not be governed by the U. N. Convention onContracts for the International Sale of Goods and will not be governed by anystatute based on or derived from the Uniform Computer Information

    Transactions Act (UCITA). If any provision of this Agreement is found to be invalidor unenforceable, it will be enforced to the extent permissible and the remainderof this Agreement will remain in full force and effect. Failure to prosecute apartys rights with respect to a default hereunder will not constitute a waiver ofthe right to enforce rights with respect to the same or any other breach.

    Government Users. The Software contains commercial computer software andcommercial computer software documentation. In accordance with FAR 12.212and DFARS 227.7202, use, duplication or disclosure is subject to restrictionsunder paragraph (c)(1)(ii) of the Rights in Technical Data and Computer Softwareclause at 252.227-7013, and further restricted by this Agreement. Synplicity,Inc., 935 Stewart Drive, Sunnyvale, CA 94085, U. S. A.

    University Program. The following section applies only if Licensee is a participantin Synplicitys University Program; it does not replace the remainder of theAgreement and supersedes only those terms that directly conflict.

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    8/278

    LO

    Preface

    viii Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    University Program: License. Subject to the terms and conditions of thisAgreement, Synplicity hereby grants to Licensee (a University) for the License

    Term (defined below), a non-exclusive license, only for purposes of course work orteaching in connection with a university-sponsored class, or for academicresearch either sponsored by or conducted under the auspices of Licensee, to (a)

    install and use the SOFTWARE, and (b) reproduce and distribute copies of thedocumentation included in the SOFTWAREsubject only to payment for thosecopies (which may be based on the number of users, the number and type ofcopies, or both). If the SOFTWARE is licensed pursuant to a node-locked license,then the Licensee may install and use the SOFTWARE on the authorizedworkstations. If the SOFTWARE is licensed pursuant to a floating license, thenthe Licensee may install the SOFTWARE on the authorized server and use theSOFTWARE on up to the number of nodes for which Licensee has paid licensefees and Synplicity has granted authorization.

    University Program: License Term and Termination. For purposes of theUniversity Program, License Term means one year unless otherwise agreed to inwriting. This Agreement will terminate at the end of the License Term, unless

    earlier terminated in accordance with this Agreement.University Program: License Restrictions.As Licensee, University may not (i)allow access to the SOFTWARE by any user not registered for a course orparticipating in an academic research project for which use of the SOFTWAREhas been authorized; (ii) use the SOFTWARE to design any commercial products;or (iii) disclose the results of any benchmarking of the SOFTWARE, or use suchresults for its own competing software development activities, without the priorwritten permission of Synplicity.

    University Program: Technical Liaison. Licensee shall appoint a TechnicalLiaison who will serve as the single point of contact between Synplicity andLicensee with respect to the subject matter of this Agreement. The TechnicalLiaison will coordinate installation and maintenance of the SOFTWARE,communicate with Synplicity regarding license procedures, administer Licenseesobligations under this Agreement and respond to inquiries by Synplicity relatedto the subject matter of this Agreement.

    University Program: Technical Support in North America.Unless otherwiseagreed in writing, Synplicity will accept calls only from the appointed TechnicalLiaison. No technical support will be provided other than calls from the TechnicalLiaison relating to installation of the SOFTWARE. SOFTWARE upgrades may beobtained from the Synplicity Web Site.

    University Program: International Technical Support.Technical support isprovided through Synplicitys authorized distributors in accordance with theirapplicable policies.

    revised 02/01

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    9/278Synplify Pro User Guide, February 2001 ix

    Go BackIndexRelated

    Documents

    Contents

    Chapter 1: Introduction

    Synplify Pro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

    About the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

    Supported Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

    Supported Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

    Synplicity Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

    The Generic FPGA Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4HDL Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

    Logic Optimization (Compilation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

    Technology Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

    Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

    Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

    FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

    Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

    Scope of the Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

    Starting the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

    Setting Up Your License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

    Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

    User Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

    Chapter 2: Synplify Pro Tutorial

    Introduction to the Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

    The Tutorial Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

    Start the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    10/278

    LO

    Contents

    x Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    Set up Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

    Create a Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

    Check the Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

    Resolve Source File Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

    Examine the RTL View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

    Altera Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

    Set Altera Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

    Set Altera Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

    Run Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

    Analyze the Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

    Examine the Technology View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

    Check Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

    Analyze Critical Paths in the Technology View . . . . . . . . . . . . . . . . . . . . . . . 2-25Rerun Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

    Rerun Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

    Check the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

    Xilinx Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

    Set Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

    Set Xilinx Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

    Run Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

    Analyze the Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35Examine the Technology View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

    Check Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

    Analyze Critical Paths in the Technology View . . . . . . . . . . . . . . . . . . . . . . . 2-39

    Rerun Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

    Check the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    11/278

    Contents

    Synplify Pro User Guide, February 2001 xi

    Go BackIndexRelated

    Documents1st Page

    Chapter 3: Tasks and Tips

    The Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

    Setting Up HDL Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

    Creating Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3Checking Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

    Viewing and Editing Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

    Crossprobing from the Text Editor Window . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

    Setting Editing Window Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

    Useful Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

    Setting Up Project Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

    Creating a Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

    Opening an Existing Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

    Making Changes to a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

    Using Mixed Language Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17Setting Project View Display Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

    Useful Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

    Setting Implementation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

    Setting Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

    Setting Constraint and Optimization Options . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

    Specifying Result Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

    Specifying Source Code Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27

    Setting Constraints with SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

    Opening SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29

    Entering and Editing Constraints Directly in SCOPE . . . . . . . . . . . . . . . . . . . 3-30

    Entering Default Constraints with the Wizard . . . . . . . . . . . . . . . . . . . . . . . . . 3-33

    Defining Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35

    Setting SCOPE Display Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38

    Working in the RTL and Technology Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39

    Differentiating Between the Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40

    Opening the Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41

    Analyzing Your Design Graphically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42

    Selecting Objects in the RTL/Technology Views . . . . . . . . . . . . . . . . . . . . . . 3-42

    Finding Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43

    Traversing Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44Working with Multisheet Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49

    Setting Preferences from the UI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50

    Setting Preferences in the .ini File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51

    Managing Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    12/278

    LO

    Contents

    xii Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    Crossprobing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54

    Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54

    Crossprobing within an RTL/Technology View . . . . . . . . . . . . . . . . . . . . . . . . 3-55

    Crossprobing from the RTL/Technology View . . . . . . . . . . . . . . . . . . . . . . . . 3-56

    Crossprobing from the Text Editor Window . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57Crossprobing from the Tcl Script Window . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60

    Crossprobing from the FSM Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60

    Working with HDL Analyst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61

    Flattening Schematic Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-62

    Filtering Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64

    Extending Selected Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65

    Viewing Critical Paths in HDL Analyst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67

    Handling Negative Slack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68

    Useful Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70

    Checking the Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72

    Viewing the Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72

    Analyzing Results Using the Log File Reports . . . . . . . . . . . . . . . . . . . . . . . . 3-74

    Using the Log Watch Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74

    Checking Results in the Tcl Script Window . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76

    Handling Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76

    Using the Symbolic FSM Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82

    Choosing When to Use the FSM Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82

    Running the FSM Compiler on the Whole Design . . . . . . . . . . . . . . . . . . . . . 3-83

    Running the FSM Compiler on Individual State Machines . . . . . . . . . . . . . . . 3-85

    Specifying FSMs with Attributes and Directives . . . . . . . . . . . . . . . . . . . . . . . 3-87

    Using the FSM Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89

    Viewing FSM Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89

    Useful Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94

    Adding Attributes and Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95

    Adding Attributes and Directives in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95

    Adding Attributes and Directives in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . 3-96

    Adding Attributes in SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-97

    Adding Attributes From the RTL and Technology Views . . . . . . . . . . . . . . . . 3-99

    Optimizing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100

    Controlling Flattening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100

    Setting Fanout Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    13/278

    Contents

    Synplify Pro User Guide, February 2001 xiii

    Go BackIndexRelated

    Documents1st Page

    Preventing Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102

    Preserving Objects from Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102

    Preserving Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103

    Working with Multiple Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-104

    Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-106

    General Optimization Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-106

    Area Optimization Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107

    Timing Optimization Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107

    Generating Vendor-Specific Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-109

    Chapter 4: Advanced Techniques

    Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

    Running Batch Mode on a Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

    Running Batch Mode with a Tcl Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

    Working with Tcl Scripts and Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

    Crossprobing from the Tcl Script Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

    Using Tcl Commands and Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

    Generating a Job Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

    Creating a Tcl Synthesis Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

    Using Tcl Variables for Multiple Runs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

    Running Bottom-up Synthesis with a Script . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

    Working with Constraint Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

    When to Use Constraint Files over Source Code . . . . . . . . . . . . . . . . . . . . . . . 4-9General Tcl Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

    Creating Constraint Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

    Creating Constraint Files for Forward Annotation . . . . . . . . . . . . . . . . . . . . . 4-12

    Defining Black Boxes for Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

    Instantiating Black Boxes and I/Os in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

    Instantiating Black Boxes and I/Os in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . 4-17

    Adding Black Box Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19

    Adding Other Black Box Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21

    Defining Black Boxes Using STAMP Models . . . . . . . . . . . . . . . . . . . . . . . . . 4-22

    Defining State Machines for Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24Defining Verilog State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24

    Defining VHDL State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    14/278

    LO

    Contents

    xiv Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    Using FSM Explorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26

    Deciding When to Use the FSM Explorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26

    Running the FSM Explorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26

    Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29

    Prerequisites for Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30

    Pipelining the Entire Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30

    Adding Pipelining Attributes in the Source Code . . . . . . . . . . . . . . . . . . . . . . 4-31

    Adding Pipelining Attributes Interactively . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32

    Retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34

    Retiming During Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35

    Retiming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37

    Retiming Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38

    Inserting Probes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38

    Specifying Probes in the Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38Adding Probe Attributes Interactively . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40

    Inferring RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41

    Inference vs. Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42

    Structuring RAMs for Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42

    Coding Altera RAMs for Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46

    Coding Xilinx Block RAMs for Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49

    Specifying RAM Implementation Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51

    Classic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52

    Working with Altera Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54

    APEX Design Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54

    FLEX Design Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55

    Instantiating LPMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55

    Inferencing ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-56

    Working with Altera EABs and ESBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57

    Packing I/O Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58

    Working with Xilinx Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59

    Designing for Xilinx Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59

    Instantiating CoreGen/PCI Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60

    Using Clock DLLs in Virtex Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60

    Packing Registers for I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-62

    Controlling Placement with RLOCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64

    Instantiating Special I/O Standard Buffers for Virtex . . . . . . . . . . . . . . . . . . . 4-66

    Inferring Dynamic Shift Register Lookup (SRL) Tables . . . . . . . . . . . . . . . . . 4-67

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    15/278

    Contents

    Synplify Pro User Guide, February 2001 xv

    Go BackIndexRelated

    Documents1st Page

    Using the Xilinx Modular Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-71

    Introduction to the Modular Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-71

    Initial Design Budgeting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-71

    Active Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-75

    Final Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80Design Files and Area Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81

    Synplify Pro and Amplify Modular Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-86

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    16/278

    LO

    Contents

    xvi Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    17/278

    Go BackIndexRelated

    Documents

    Chapter 1Introduction

    This chapter contains an introduction to Synplify Pro, and describes the

    following:

    Synplify Pro on page 1-2

    The Generic FPGA Design Flow on page 1-4

    Audience on page 1-7

    Scope of the Document on page 1-7

    Starting the Software on page 1-8

    User Interface Overview on page 1-12

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    18/278

    LO

    Chapter 1: Introduction Synplify Pro

    1-2 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    Synplify Pro

    This section briefly discusses the following topics:

    About the Software

    Supported Platforms

    Supported Standards

    Synplicity Product Family

    About the Software

    Synplify Pro

    is a logic synthesis tool for FPGAs (Field ProgrammableGate Arrays) and Complex PLDs (Programmable Logic Devices), developed

    by Synplicityof Sunnyvale, California. Synplify Pro starts with high-level

    designs written in Verilog and VHDL hardware description languages

    (HDLs). Using proprietary Behavior Extracting Synthesis Technology

    (B.E.S.T.), the tool converts the HDL into small, high-performance,

    design netlists that are optimized for popular technology vendors. Option-

    ally, Synplify Pro can write post-synthesis VHDL and Verilog netlists that

    you can use for simulation to verify functionality.

    Synplify Pro has the following built-in features:

    The HDL Analyst, a graphical tool for analysis and crossprobing.

    The Synplify Pro Text Editor Window, with a language-sensitive

    editor for writing and editing HDL code.

    SCOPE (Synthesis Constraint Optimization Environment), which

    uses a spreadsheet-like interface to manage the timing constraints

    and attributes in the design.

    A symbolic FSM Compiler, which performs advanced state machine

    optimizations.

    The FSM Explorer, which tries different state machine optimizations

    before picking the best implementation.

    The FSM viewer, which lets you view the transitions in detail.

    A command line interface from which you can run TCL scripts.

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    19/278

    Synplify Pro Chapter 1: Introduction

    Synplify Pro User Guide, February 2001 1-3

    Go BackIndexRelated

    Documents1st Page

    Supported Platforms

    Synplify Pro runs on these platforms:

    PC (Windows98/Windows 2000/NT 4.0/Windows ME)

    Sun (Sun OS 5.6 and 5.7/Solaris 2.6 and 2.7)

    HP-UX 10.20

    Supported Standards

    Verilog

    Synplify Pro supports a synthesizable subset of Verilog95 (IEEE

    1364).

    VHDL

    Synplify Pro supports a synthesizable subset of VHDL93 (IEEE

    1076), and the following IEEE library packages:

    std_logic_1164

    numeric_std

    numeric_bit

    std_logic_unsigned std_logic_signed

    std_logic_arith

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    20/278

    LO

    Chapter 1: Introduction The Generic FPGA Design Flow

    1-4 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    Synplicity Product Family

    Synplicity products are based on core synthesis technology, and share a

    common look and feel. Synplify is the basic synthesis tool. Synplify Pro is

    an advanced version of Synplify, with many additional features andcapabilities. You can also buy Amplify, the physical optimizer, as an

    option to Synplify Pro.

    The Generic FPGA Design Flow

    The following figure contains a generic design flow showing the typical

    steps a designer follows when implementing an FPGA. The shaded box

    shows the steps you can accomplish with Synplify Pro. This generic

    design flow complements the specific design flow used for the tutorial.

    Refer to The Tutorial Design Flowon page 2-3for a description.

    Synplify

    Synplify Pro Amplify

    Certify

    Synthesis

    Board Verification

    Physical Optimization

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    21/278

    The Generic FPGA Design Flow Chapter 1: Introduction

    Synplify Pro User Guide, February 2001 1-5

    Go BackIndexRelated

    Documents1st Page

    The following sections describe each step more fully.

    HDL Design Entry

    The starting point for FPGA design is to specify the logic of the FPGA

    circuit to be implemented. You can do this by drawing a schematic,

    writing an HDL description, or specifying Boolean expressions.

    For Synplify Pro, design entry is the step in which you generate the input

    for the tool. The input must be Verilog or VHDL descriptions. Synplify Pro

    provides you with an environment in which you can write or edit HDL

    descriptions.

    Logic Optimization (Compilation)

    This is the first stage of synthesis, in which the software restructures the

    original network into a set of combinational functions. In Synplify Pro, the

    combinational functions are represented as a Boolean network. At thispoint in the design process, you modify the initial logic design to optimize

    the area or speed of the final circuit, or both. The optimization is calcu-

    lated from the netlist and is independent of the target technology. It

    includes operations like redundancy removal and common subexpression

    elimination.

    HDL Design Entry

    Logic Optimization

    Technology Mapping

    Routing

    Placement

    FPGA Configuration

    Synplify Pro

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    22/278

    LO

    Chapter 1: Introduction The Generic FPGA Design Flow

    1-6 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    Technology Mapping

    Technology mapping is the second phase of optimization, in which the

    logic is optimized to a specific technology. During this phase, the

    compiled design is transformed into a circuit of optimized FPGA logicblocks. Depending on your design priorities, you might want to focus on

    area optimization (minimizing the total number of blocks), delay optimiza-

    tion (minimizing the number of logic block stages in time-critical paths),

    or both.

    Synplify Pro uses architecture-specific mapping techniques to map the

    logic design. It has built-in tools to analyze critical paths, crossprobe, and

    check the RTL view. Synplify Pro outputs netlists in formats appropriate

    for the place and route tools that follow.

    Placement

    Placement is the first step of the physical design process. During place-

    ment, the logic blocks are placed in an FPGA array. At this point, consid-

    erations like the total interconnect length become important.

    This is the point at which Synplify Pro gives control of the design to

    another tool. However if you have the AmplifyPhysical Optimizer, you

    can use the results from an initial placement pass to further optimize

    your logic design.

    Routing

    Routing is the final step of the physical design process. At this stage, use

    the place-and-route tool to connect the placed logic blocks by assigning

    wire segments and choosing programmable switches.

    FPGA Configuration

    In this design phase, you configure the final FPGA chip and implement it.

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    23/278

    Audience Chapter 1: Introduction

    Synplify Pro User Guide, February 2001 1-7

    Go BackIndexRelated

    Documents1st Page

    Audience

    Synplify Pro is targeted towards the FPGA system developer. It is assumed

    that you are knowledgeable about the following:

    Design synthesis

    RTL

    FPGAs

    Verilog/VHDL

    Scope of the Document

    This user guide is part of a document set, and is intended for use with the

    other documents in the set. It concentrates on describing how to use

    Synplify Pro to accomplish typical tasks. This implies the following:

    The user guide only explains the options needed to do the typical

    tasks described in the manual. It does not describe every available

    command and option. For complete descriptions of all the command

    options and syntax, refer to the Synplify Pro Reference Manual.

    The user guide contains task-based information. For a breakdown of

    how information is organized, see Getting Helpon page 1-11.

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    24/278

    LO

    Chapter 1: Introduction Starting the Software

    1-8 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    Starting the Software

    This section shows you how to get started with Synplify Pro. It describes

    the following topics, but does not supersede the information in the instal-lation instructions about licensing and installation:

    Getting Started

    Setting Up Your License

    Getting Help

    Getting Started

    1. If you have not already done so, install Synplify Pro according to theinstallation instructions.

    2. Start the software.

    If you are working on a PC, select Programs->Synplicity->Synplify Pro

    from the Startbutton.

    If you are working on a UNIX workstation, type this at the

    command line:

    synplify_pro

    The command starts the Synplify Pro synthesis tool, and opens the

    Project window. If you have run the software before, the window

    displays the previous project. For more information about the inter-

    face, see the Synplify Pro Reference Manual.

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    25/278

    Starting the Software Chapter 1: Introduction

    Synplify Pro User Guide, February 2001 1-9

    Go BackIndexRelated

    Documents1st Page

    Setting Up Your License

    The most current and comprehensive licensing information is included in

    the installation instructions. This section describes how to set up node-

    locked licenses on the PC with the wizard. For other licensing informationlike trial licenses, or setting up license servers, refer to the installation

    instructions.

    1. To enter license information,

    Select Help->License Wizard.

    Select the Edit or enter license information received from Synplicitybutton at

    the bottom of the form, and click Next.

    Follow the instructions.

    2. To select a new floating license or change your current license,

    Pick Help->Preferred License Selection. Click on a license from the License Typelist, and click Select.

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    26/278

    LO

    Chapter 1: Introduction Starting the Software

    1-10 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    To automatically start the selected license the next time you start

    Synplify Pro select Save as default license typeat the bottom of the

    window.

    Click Saveand restart the software.

    3. For Windows 98, Windows ME, Windows NT, and Windows 2000,

    install the sentinel driver.

    Double click on the setupx86.exefile in the \Synplicity\sentinel directory.

    In the installation window that opens, click Functions(located in the

    upper left hand corner) to select Install Sentinel driver. A dialog boxspecifying the path for I386 pops up.

    Confirm that the path is correct.

    After the drive has been installed, restart the computer. You can

    now start Synplify Pro.

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    27/278

    Starting the Software Chapter 1: Introduction

    Synplify Pro User Guide, February 2001 1-11

    Go BackIndexRelated

    Documents1st Page

    Getting Help

    Before you call Synplicity Support, look through the documented informa-

    tion. You can access the information online from the Helpmenu, or refer to

    the printed manual. The following table shows you how the information isorganized.

    For help with... Refer to the...

    Licensing Installation Guide

    Attributes and directives Synplify Pro Reference Manual

    Synthesis features Synplify Pro Reference Manual

    Language and syntax Synplify Pro Reference Manual

    Tcl Online help (select Help->Tcl Help)

    Using tool-specificfeatures and attributes

    Synplify Pro User Guide

    How to... Synplify Pro User Guide, application notes on theSynplicity support web site

    Flow information Synplify Pro User Guide, application notes on theSynplicity support web site

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    28/278

    LO

    Chapter 1: Introduction User Interface Overview

    1-12 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    User Interface Overview

    The user interface (UI) consists of a main window, called the Project view,

    and specialized windows or views for different tasks. For details abouteach of the features, see the Synplify Pro Reference Manual. Synplify Pro

    gives you the choice of two UIs. It is recommended that you use the

    standard interface shown below and used in illustrations in the rest of the

    document.

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    29/278

    User Interface Overview Chapter 1: Introduction

    Synplify Pro User Guide, February 2001 1-13

    Go BackIndexRelated

    Documents1st Page

    The other choice is shown below. In this interface, some features are only

    available from the menus. For information about using this interface, see

    Classic Interfaceon page 4-52.

    Menu

    Project View

    Toolbars

    ButtonPanel

    Status Bar

    TCL Script WindowView Tab Log Watch Window

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    30/278

    LO

    Chapter 1: Introduction User Interface Overview

    1-14 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    Menus

    Toolbars

    Status

    Project View

    UI Buttons

    and Options

    TCL Script Window

    View Tab

    Log Watch Window

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    31/278

    Go BackIndexRelated

    Documents

    Chapter 2Synplify Pro Tutorial

    The tutorial shows you how to use Synplify Pro in the design process.

    Information is organized into these topics:

    Introduction to the Tutorial on page 2-2

    The Tutorial Design Flow on page 2-3

    Start the Software on page 2-4

    Set up Source Files on page 2-6

    Altera Flow on page 2-17

    Set Altera Constraints on page 2-17

    Run Synthesis on page 2-22

    Analyze the Synthesis Results on page 2-22

    Rerun Synthesis on page 2-27

    Xilinx Flow on page 2-29

    Set Constraints on page 2-30

    Set Xilinx Device Options on page 2-32

    Run Synthesis on page 2-35

    Analyze the Synthesis Results on page 2-35

    Rerun Synthesis on page 2-40

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    32/278

    LO

    Chapter 2: Synplify Pro Tutorial Introduction to the Tutorial

    2-2 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    Introduction to the Tutorial

    This tutorial is designed to walk you through some typical tasks and

    familiarize you with the user interface, but it does not cover all thepossible tasks you could do. For additional information, refer to the

    following sources:

    The tutorial design is an eight-bit micro controller. After completing this

    tutorial, you will be familiar with the tool and able to apply the knowledge

    you gained to your own, more complicated designs.

    This tutorial assumes that you have

    Installed the software correctly

    Obtained the necessary licenses

    If you need help with these issues, refer to the installation instructions.

    For information about... See...

    Installation information The installation instructions

    Information about the interface Synplify Pro Reference Manual

    Common tasks not covered in thetutorial

    Chapter 3, Tasks and Tips

    Advanced techniques Chapter 4,Advanced Techniques

    Detailed information about thecommands and syntax

    Synplify Pro Reference Manual

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    33/278

    The Tutorial Design Flow Chapter 2: Synplify Pro Tutorial

    Synplify Pro User Guide, February 2001 2-3

    Go BackIndexRelated

    Documents1st Page

    The Tutorial Design Flow

    This flow diagram graphically illustrates the procedures demonstrated in

    this tutorial:

    Set up Source Files

    Set Constraints

    Run

    Start Software

    Analyze

    Implement FPGA

    Set Options

    Source files

    Technology parameters

    Rerun

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    34/278

    LO

    Chapter 2: Synplify Pro Tutorial Start the Software

    2-4 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    Start the Software

    You can start the software and run the tutorial from either a PC or a UNIX

    workstation. If your setup is different, talk to your system administrator.

    1. Make sure you have installed the software and obtained a license.

    2. Copy the contents of the tutorialdirectory to your working area. Keep

    the directory structure, because the tutorial is based on this

    structure. When you work on your own designs, you can set up the

    structure any way you want.

    Your tutorialdirectory contains the following directories and files. The

    directories are apexand virtex, the two technologies used

    in this tutorial.

    3. Start the software.

    If you are working on a PC, select Programs->Synplicity->Synplify Pro

    from the Startbutton.

    If you are working on a UNIX workstation, type this at the

    command line: synplify_pro.

    tutorial

    Source Files

    verilogvhdl

    Source Files

    Source Files Source Files

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    35/278

    Start the Software Chapter 2: Synplify Pro Tutorial

    Synplify Pro User Guide, February 2001 2-5

    Go BackIndexRelated

    Documents1st Page

    The command starts the synthesis tool and opens the Project

    Window. This figure shows the window the first time you start the

    software. If you have run the software before, the window displays

    the previous project. For more information about the interface, see

    the Synplify Pro Reference Manual.

    Menu

    Project Window

    Toolbars

    TCL Window Log Watch Window

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    36/278

    LO

    Chapter 2: Synplify Pro Tutorial Set up Source Files

    2-6 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    Even though you do not use the Tcl window in this tutorial, you can

    leave it open to view status and other informational messages.

    You can access common commands in different ways: through the

    menu, popup menus, keyboard shortcuts, and icons. Throughout

    this tutorial, the alternate methods are listed first and the menu

    command is listed at the end.

    Set up Source Files

    The first step is to set up the input files for the project. A project is a

    design that you work on, and consists of the input files and the imple-mentation files. This section shows you how to do the following:

    Create a Project File

    Check the Source Files

    Resolve Source File Warnings

    Examine the RTL View

    Create a Project File

    To run synthesis, you need a project file. So, the first step is to create a

    project file. A project contains the data needed for a particular design: the

    list of source files, the synthesis results file, and your device option

    settings. The following procedure shows you how to set up a project file.

    1. In the window, select File -> Build Project to open a form.

    2. In the Select Files to Add to Project dialog box, do the following to set the

    directory and project file name:

    Set the Look In: field at the top of the form to the appropriate

    directory: tutorial\vhdl\. If you plan to work through the

    Altera flow in the tutorial, select apexfor the technology; if you

    want to work through the Xilinx flow, select virtex. The tutorial only

    illustrates these two technologies, but the software supports many

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    37/278

    Set up Source Files Chapter 2: Synplify Pro Tutorial

    Synplify Pro User Guide, February 2001 2-7

    Go BackIndexRelated

    Documents1st Page

    other technologies. If you use a technology that is not covered by

    the tutorial, you can still follow the general flow of the tutorial but

    substitute parameters specific to your technology.

    Set Files of Typeto HDL Files (.vhd, .v). This tutorial uses only the VHDL

    files. If you want to use Verilog, use the Verilog source files

    provided in the tutorial\verilogdirectory, but your results might not

    exactly match all the steps in this tutorial.

    The next step is to add the source files to your project file.

    3. Add the source files, by doing the following in the dialog box:

    Set the Look Infield at the top to the folder. This

    tutorial uses VHDL source files. However, when you run the

    software on your own design, you also have the option of using

    Verilog source files or mixed input files.

    Set Files of TypetoVHDL files (*.vhd). If you are using Verilog files, you

    must set this to Verilog files (*.v).

    Add the package file first. Select the const_pkg.vhd file and clicktheAddbutton on the right side of the form. The file appears in the

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    38/278

    LO

    Chapter 2: Synplify Pro Tutorial Set up Source Files

    2-8 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    text box at the bottom of the form. You do not need to add the

    package file first in Verilog.

    Add the other files. Click theAdd Allbutton on the right side of the

    form to add all the files in the directory. The text box now displays

    all the .vhdfiles.

    Click OK.

    Your project window displays a newly-created project file called

    const_pkgwith a folder called vhdland a directory under it called rev_1,

    The rev_1directory will contain the files from the first implementation

    of your design. Implementations are revisions of your design within

    the context of the synthesis software, and do not replace external

    source code control software and processes. Multiple implementa-

    tions let you modify device and synthesis options to explore design

    options. Each implementation has its own synthesis and deviceoptions and its own project-related files.

    4. Click on the plus sign next to the vhdlfolder.

    You see a list of the source HDL files for the project.

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    39/278

    Set up Source Files Chapter 2: Synplify Pro Tutorial

    Synplify Pro User Guide, February 2001 2-9

    Go BackIndexRelated

    Documents1st Page

    5. Make sure the package file is the first file and the top-level file is the

    last in the list of files in the Project window. Click the top-level file

    (eight_bit_uc.vhd) in the text box and drag it to the end of the list offiles. The order of the rest of the files does not matter.

    6. Save and rename the project. Select File->Save, type tutorialas the name

    of the project, and click Save. The Project window reflects your

    changes.

    If your files are not in a folder under the tutorialdirectory, you canset this preference by selecting the Options->Project View Options

    command and checking the View project files in foldersbox. This separates

    one kind of file from another in the Project view by putting them in

    separate folders.

    Check the Source Files

    1. Press F7or selectRun -> Compile Only.

    The software optimizes the logic using technology-independent

    operations, and checks for syntax and hardware-related synthesis

    errors. When it has compiled, you see the following changes:

    The status box at the top contains the message Done (Warnings).

    The RTL icon in the toolbar is now selectable.

    There is an exclamation mark next to the ins_decode.vhdfile, which

    indicates a warning. Errors are more serious than warnings;

    warnings are more serious than notes, which are often

    informational.

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    40/278

    LO

    Chapter 2: Synplify Pro Tutorial Set up Source Files

    2-10 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    2. Review the warning. To see the warning, click the Warnings tab in

    the Tcl window. Double-click the ins_decode.vhdfile in the Project view.

    This opens the Text Editor window, with the error highlighted in red.

    @W: ins_decode.vhd(21): Map for port tris_we of componentins_decode not found

    @W: eight_bit_uc.vhd(171): tris_we is not assigned a value(floating)

    Resolve Source File Warnings

    You can edit the source files directly in the Text Editor window, which you

    opened by double-clicking on the file in the project window.

    1. Check the warning in the ins_decode.vhdsource file.

    Read the highlighted line in the source file. If you are not at the

    line with the warning, press F5 to go to the correct line. The

    TRIS_WE : out std_logicline is highlighted.

    Check the bottom of the Text Editor window for an explanation of

    the error:

    Warning: Map for port tris_we of component ins_decode notfound.

    There is a discrepancy between port definitions at the component

    level and the top level.

    2. Return to the project view and check the top-level design file.

    Close the window with the ins_decode.vhdsource file.

    Double-click eight_bit_uc.vhd in the project window to open the top-

    level file.

    Press Ctrl-fto open the Edit->Findform.

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    41/278

    Set up Source Files Chapter 2: Synplify Pro Tutorial

    Synplify Pro User Guide, February 2001 2-11

    Go BackIndexRelated

    Documents1st Page

    Type TRISin the Find Whatfield of the form and click Find Next.The

    software finds this line:

    TRIS_XWE : out std_logic;

    3. Correct the error by changing TRISX_WEto TRIS_WEto match the portdefined in the ins_decodecomponent.

    Normally you would also check the schematic view of the design, but

    for the purposes of the tutorial, just correct the typing mistake.

    4. Close the editing window, and click Yesin the dialog box that asks

    you if you want to save your changes.

    5. Press F7to recompile.

    This time there are no errors, and the status box displays the

    message Done!

    Examine the RTL View

    Now that you have compiled the design and your source files do not have

    any errors, you can look at an RTL schematic view of the design.

    1. Click the RTL View icon from the toolbar, or select HDL Analyst ->

    RTL -> Hierarchical Viewto open the RTL view.

    This view is a hierarchical, technology-independent schematic view,

    that is generated by the software. The RTL view has two panes: the

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    42/278

    LO

    Chapter 2: Synplify Pro Tutorial Set up Source Files

    2-12 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    left pane lists the nets and ports in the design and the right pane

    contains the schematic. At the top, it lists the number of sheets in

    the schematic.

    2. To view the design, use these icons from the toolbar,

    or the corresponding commands from the Viewmenu.

    Click the lens icon with a plus (+) on it, and use the Z-shaped

    cursor to define a rectangle for zooming in.

    Zoom into the prgrmcntrblock and look at the incrementor, state

    machines, and large mux. Zoom into the regsblock to see how the

    software inferred the RAM. The RTL view shows components at a

    high level of abstraction, so you can recognize the pieces of logic

    from the source code.

    Zoom intothis areamarked bythe redrectangle

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    43/278

    Set up Source Files Chapter 2: Synplify Pro Tutorial

    Synplify Pro User Guide, February 2001 2-13

    Go BackIndexRelated

    Documents1st Page

    Click on the Zoom inicon again to exit zoom mode or right-click in

    an empty area of the RTL view. The Z-shaped cursor changes to

    the crosshair cursor, which indicates the default selection mode.

    3. Select the Push/Pop Hierarchyicon and click on the Prgrm_Cntr

    block in the schematic. You see a schematic of the program counter.

    Synplicitys proprietary B.E.S.T (Behavioral Extraction Synthesis

    Technology) automatically detects and extracts some high-levelbehavioral constructs. This is different from other synthesis tools

    which decompose the RTL into low-level boolean primitives that have

    to be reconstructed into higher-level primitives at the place-and-

    route stage. The software extracts high-level behavior, represents it

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    44/278

    LO

    Chapter 2: Synplify Pro Tutorial Set up Source Files

    2-14 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    as an abstract (like the incrementor in the program block), and

    operates on this abstract.

    4. Crossprobe from the Prgrm_Cntrschematic to the source code.

    Zoom in and find the incrementor symbol . Click the Zoomicon

    again to get out of zoom mode, and then double-click the

    RTL View

    RTL View after you pushinto the hierarchy

    Incrementorsymbol

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    45/278

    Set up Source Files Chapter 2: Synplify Pro Tutorial

    Synplify Pro User Guide, February 2001 2-15

    Go BackIndexRelated

    Documents1st Page

    incrementor symbol. The software displays the corresponding RTL

    code. Close the source file window when you are done.

    Click the Push/Pop Hierarchyicon and then click in a blank area of

    the view (you see an arrow pointing upwards) to return to the toplevel.

    5. To crossprobe from the source code to the schematic, double-click

    the alu.vhdfile in the Project view. This opens the source file.

    Select the Push/Pop Hierarchyicon and click the ALU block in the RTL

    view. You see a schematic of the ALU function.

    Select the entire bitdecoder definition in the source file. You can

    use Ctrl-fto find the definition, which begins with this code:

    BITDECODER

  • 8/10/2019 Synplify Userguide

    46/278

    LO

    Chapter 2: Synplify Pro Tutorial Set up Source Files

    2-16 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    If necessary, select the Sheet icon to move to the correct sheet

    of the ALU schematic. You might not need to do this, depending

    on the settings in your .inifile.

    6. Close the source code window and return to the top-level schematic

    view. You can iconize the RTL view, but do not close it.

    The rest of the tutorial varies slightly, depending on the technology

    you use. So, if you are working with Altera technology, go to Altera

    Flowon page 2-17for the next step. If you are working with Xilinx

    technology, go to Xilinx Flowon page 2-29for the next step. If you do

    not use either of these vendors, you can follow the methodology usedin either of these flows and substitute device options specific to your

    vendor.

    Select this definition in the sourcecode to see these componentshighlighted in the RTL view of theALU block.

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    47/278

    Altera Flow Chapter 2: Synplify Pro Tutorial

    Synplify Pro User Guide, February 2001 2-17

    Go BackIndexRelated

    Documents1st Page

    Altera Flow

    The Altera design flow in this tutorial uses APEX technology. The following

    sections show you how to

    Set Altera Constraints

    Set Altera Device Options

    Run Synthesis

    Analyze the Synthesis Results

    Rerun Synthesis

    To work through the tutorial with the Xilinx design flow, see Xilinx Flow

    on page 2-29. If you do not use Altera or Xilinx, you can still follow along

    with the tutorial, using device options specific to your vendor.

    Set Altera Constraints

    Design constraints are optional, but most designers use them to define

    the frequency goals and describe the environment around the design. Fordesigns without aggressive timing goals, you can just set the clock period.

    You can set constraints in a text file that you can create with any text

    editor, but it is easier to use SCOPE (Synthesis Constraint Optimization

    Environment). SCOPE provides an easy-to-use spreadsheet interface for

    entering constraints.

    The tutorial design uses basic constraints, which you enter as follows:

    1. Start SCOPE in the open project window by doing one of the

    following:

    Clicking the Constraint file (SCOPE) icon in the toolbar.

    Selecting File - >New Constraint file (SCOPE).

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    48/278

    LO

    Chapter 2: Synplify Pro Tutorial Set Altera Constraints

    2-18 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    The Initialize New Constraintsdialog box opens.

    2. Click Initialize.

    The SCOPE window opens, with the most common constraints, clockfrequency and input/output delays, initialized.

    3. Do the following to set a clock frequency constraint:

    Select the Clockstab at the bottom, if it is not already selected.

    Click the box in the Enabledcolumn to enable the clock constraint.

    Enter 65 in the Valuecolumn to set the global frequency value.

    4. To set input/output delay constraints,

    Click the Inputs/Outputstab.

    Enable the and by clicking the

    respective boxes.

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    49/278

    Set Altera Constraints Chapter 2: Synplify Pro Tutorial

    Synplify Pro User Guide, February 2001 2-19

    Go BackIndexRelated

    Documents1st Page

    Set a value of 5 ns for each of them.

    5. Save the constraint file by clicking the icon, or by selecting File ->

    Save.

    6. Select Yesin the dialog box that asks you if you want to add the file to

    the project.

    You should now have the following files in the project:

    A vhdlfolder that contains the source files

    A constraint folder with the constraint file (tutorial.sdc)

    An implementation folder (rev_1)

    Now that you have your files set up, you can set the device options and

    run synthesis.

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    50/278

    LO

    Chapter 2: Synplify Pro Tutorial Set Altera Device Options

    2-20 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    Set Altera Device Options

    At this point, you set the device options for the first implementation

    (rev_1).

    1. Select rev_1, and click the Impl Optionsbutton on the left side of the

    project window, click the current device options listed just under the

    Synplify Pro banner, or select Project -> Implementation Options.

    The dialog box that opens lists the implementation (rev_1) at the top.

    It has five sections, and opens with the Devicesection options (the

    technology parameters) displayed.

    2. In the Devicesection,

    Set TechnologytoAltera APEX20KC. The software supports a largeselection of target technologies. The software has specific

    algorithms for optimizing each technology for best results.

    Leave the other defaults (Partat EP20K100CSpeedat -7and Package

    at TC144). The dialog box should look like this:

    3. Click the Options/Constraintstab at the top, and set the following:

    Leave the default optimization switches (Symbolic FSM Compilerand

    Resource Sharing).

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    51/278

    Set Altera Device Options Chapter 2: Synplify Pro Tutorial

    Synplify Pro User Guide, February 2001 2-21

    Go BackIndexRelated

    Documents1st Page

    Make sure the constraint file is checked.

    The settings on this tab and the Implementation Resultstab look like this:

    4. Click the Implementation Resultstab, and check the Write Vendor Constraint

    Fileoption is checked. Leave the other defaults.

    5. Do not make any changes on the VHDLtab. Click OK.

    You have already specified the top-level module in the project window

    by putting it last in the list. If you had not done that, you would

    specify the top-level module in the VHDLtab.

    You have now set all the device options and can run synthesis.

    http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/
  • 8/10/2019 Synplify Userguide

    52/278

    LO

    Chapter 2: Synplify Pro Tutorial Run Synthesis

    2-22 Synplify Pro User Guide, February 2001

    Go BackIndexRelated

    Documents1st Page

    Run Synthesis

    1. Make sure you have the prerequisites for synthesis:

    Source files

    Target technology (device options)

    An optional constraint file

    2. Click the Runbutton to start synthesis.

    The software goes through two synthesis phases, compilation and

    mapping. It reflects these stages in the Statusbox in the upper right of

    the project window. Compilation is the creation of a technology-

    independent boolean structure, and mapping is the technology-

    specific optimization of the boolean structure. You can see the

    results of compilation in the RTL view and the results after mapping

    in the Technology view.

    You can now go on to analyze your results and check timing.

    Analyze the Synthesis Results

    After you have run synthesis, you can analyze the results. This section

    shows you how to

    Examine the Technology View

    Check Timing

    Analyze Critical Paths in the Technology View

    Examine the Technology View

    1. To see the graphical results of your run, click the icon to open

    the Technology view.

    http://goback/http://synplify_docs.pdf/http://synplify_docs.pdf/http://synplify_docs.pdf/http://goback/
  • 8/10/2019 Synplify Userguide

    53/278

    Analyze the Synthesis Results Chapter 2: Synplify Pro Tutorial

    Synplify Pro User Guide, February 2001 2-23

    Go BackIndexRelated

    Documents1st Page

    The Technology view contains a schematic of the design after

    technology mapping, with base cells that are directly mapped to the

    target technology.

    2. Zoom into one of the technology-specific components, like theATOMs. You can pick any component.

    In the Hierarchy Browser on the left side of the Technology view,

    click the symbol for one of the components. The schematic in the

    Technology view moves to the correct sheet and you see the

    component highlighted in red. The actual number of sheets in the

    schematic vary, depending on the preference set in your .ini file.

    Select the Zoomicon from the toolbar and click the cursor on the

    highlighted component to zoom in and see details. Your tutorial

    design may not be implemented with the component shown in this

    example because of ongoing optimizations to the technology andthe synthesis soft


Recommended