Synthesis Synthesis Synthesis Synthesis

Gookyi Dennis A. N. Gookyi Dennis A. N.

September.02.2014

ContentsContents Design Flow of ASICs and FPGA Based Systems Language Structure Synthesis

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The General Design FlowThe General Design Flow Design flow is a set of procedures that allows

designers to progress from a specification to the final implementation in an error-free manner

The general design flow is shown below:

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Heart of front-end

Heart of back-end

RTL Synthesis FlowRTL Synthesis Flow RTL synthesis flow chart:

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Convert RTL description to generic gates and registers and then optimize the logic to improve speed and area

This block is often used in ASIC (cell-based design) but not FPGA

Insert or modify logic and registers to aid in manufacturing test

Static timing analysis checks the temporal requirement of the design and Power analysis estimates the power consumption of the circuit

Physical Synthesis FlowPhysical Synthesis Flow Divided into placement and routing stages:

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Stages Sub-divisions

Placement (logic cells are placed in at fixed positions to minimise total area and wire length)

Partitioning: Partition the circuit into partsFloorplanning: Determines location of each module in a rectangular chip areaPlacement: Finds the best position of each module

Routing (complete the connections of signal nets among the cell modules placed by placement)

Global: Decompose large routing problems into small manageable sub-problemsDetailed: Carries out actual connections of signal nets among modules

Timing-Driven PlacementTiming-Driven Placement In PAR, timing information can only be obtained after

layout has been completed In order to satisfy post-layout timing requirement, we

have to go back to logic synthesis and start again Timing-driven placement solves this problem by

incorporating timing analysis into the placement stage

The critical path can then be placed into the layout with priority

Some terms used:

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Term Definition

Arrival time Time elapsed for a signal to arrive at a certain point

Required time

Latest time at which a signal can arrive without making the clock cycle longer than desired

Slack time Difference between required time and arrival time

Timing-Driven PlacementTiming-Driven Placement

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Timing-Driven PlacementTiming-Driven Placement Features of the slack time include:

The path with the smallest slacks are called the critical path

Negative slack means the associated path is the critical path

As a results, the slack time is used to analyze the critical path of the design

Another use of slack time is in timing-dependent algorithm one of which is known as the zero slack algorithm

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Zero-slack algorithmZero-slack algorithm The assumptions made include:

Signal-arriving time at each primary input and the time a signal is required at the primary outputs are known

Algorithm: Begin repeat:

compute all slacks; find the minimum positive slack; find a path with all slacks equal to the minimum slack; distribute the slacks along the path segment;

until (there exist no positive slack);End

The purpose of the algorithm is to is to compute and distribute the slack time evenly in the interconnect along with the path from the primary input to the output

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Zero-slack algorithmZero-slack algorithm An example of the zero-slack algorithm:

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Zero-slack algorithmZero-slack algorithm Final placement of results from the slack-algorithm:

The nets with a higher slack time may use longer wires and the nets with lower slack time may use shorter wires

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Design Environment and Design Environment and ConstraintsConstraints Both design environment and constraints are

required for a design to be synthesized They must be provided along with the RTL codes and

technology library to the synthesis tool

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Component description

Environment Provides process parameters and I/O port attributes

Constraints Provide clock related constraints, I/O delays and timing exceptions

Logic SynthesisLogic Synthesis Architecture of logic synthesizers:

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Checks the syntax of the source code and creates internal components to be used in the next phase

Connects all internal components, unrolls loops, expands generate-loops, initializations etc Manages design

hierarchy, extract FSM, explore resource sharing

This is the heart of the synthesizerIt creates a new gate network which computes the functions specified by a set of Boolean functions, one per primary output

Logic Synthesis Logic Synthesis The general operations involved in technology-

independent synthesis are grouped into:Restructuring operations: includes operations that

modify the structure of the Boolean network by introducing new nodes and eliminating others

Node minimization: includes operations that simplify the logic equations associated with nodes

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Restructuring OperationsRestructuring Operations Decomposition: replaces a divisor of a function by a

new literal For example:

f = wyz + xyz + uv let g = yz and h = w+x then f = gh+uv

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Restructuring OperationsRestructuring Operations Extraction: this is related to decomposition but

operates on a number of given functions With extraction, the given functions are expressed in

terms of newly created intermediate functions and variables

For example f = xyz+uw g = xyz+uv

xyz can be extracted and denoted by a new function h

therefore: h = xyz

f = h+uw g = h+uv

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Restructuring OperationsRestructuring Operations Factorization: takes three steps

Generate all potential common factors Choses which factors to substitute into the networkReconstruct the network by adding the new factors

For example f = wyz+xyz+uv can be factored into: f = yz(w+x)+uv

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Multilevel Logic SynthesisMultilevel Logic Synthesis The motivation behind multilevel logic synthesis is

that:Most often there are too many functions that are too

expensive in terms of area and propagation time to implement in two-level logic

For example, consider the two logic functions: f(w,x,y,z) = wx+xy+xz g(w,x,y,t) = wx’+x’y+x’t

The above functions contain 12 literals and need a total of 8 gates to implement

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Multilevel Logic SynthesisMultilevel Logic Synthesis Hardware requirement is reduced when using three-

level logic structure by factoring both functions and extracting the common factor

f(w,x,y,z) = wx+xy+xz = x(w+y)+xz = x.k+xz g(w,x,y,t) = wx’+x’y+x’t = x’(w+y)+x’t = x’.k+x’t k(w,y) = w+y

The result has 10 literals and need only 7 gates

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Multilevel Logic SynthesisMultilevel Logic Synthesis The general operations involved in multilevel

synthesis are:Minimizing two-level logic functionFinding common sub-expressionsSubstituting one expression into anotherFactoring single functions

One fundamental approach used in multilevel logic synthesis is the kernel approach

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Multilevel Logic SynthesisMultilevel Logic Synthesis The kernel approach (terminologies):

The divisors of f are defined as the set: D(f) = {g| f/g != R}Primary divisors of f are defined as the set: P(f) = {f/c| c is a cube} eg if f = wxy+wxzt, then f/w = xy+xzt is a primary divisorEvery divisor of f is contained in the primary divisorAn expression is cube-free if no cube divides the

expression evenly example xy+z is cube free but xy+xz is not

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Multilevel Logic SynthesisMultilevel Logic Synthesis The kernels of f are cube-free primary divisors of f: K(f) = {k/k e P(f), k is cube-free} For given f = wxy+wxzt, then f/w = xy+xzt is a

primary divisor but not cube-free since x is a factor: f/w = x(y+zt)

A cube c used to obtain the kernel k = f/c is called a cokernel of k

Example f/wx = y+zt is a kernel and wx is the cokernel

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Multilevel Logic SynthesisMultilevel Logic Synthesis Kernel and cokernel: Consider the function f(w,x,y,z) = xz+yz+wxy There are 7 literal and we find the cokernels and

kernels as follows: f/w = xy f/x = z+wy f/y = z+wx f/z = x+y

w is not a cokernel because xy is not cube free The cokernel set is: {x,y,z} The kernel set is: {z+wy, z+wx, x+y}

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Multilevel Logic SynthesisMultilevel Logic Synthesis Consider: f(t,u,v,w,x,y,z) =

twy+txy+uwy+uxy+vwy+vxy+z There are 19 literals, use the table below to find the

cokernel:

Combining the two cokernel set, we get: {ty, uy, vy, wy, xy, y} 24

twy txy uwy uxy vwy vxy

twy *

txy ty *

uwy wy y *

uxy y xy uy *

vwy wy y wy y *

vxy y xy y wy vy *

ty uy vy wy xy

ty *

uy y *

vy y y *

wy y y y *

xy y y y y *

Multilevel Logic SynthesisMultilevel Logic Synthesis The kernels corresponding to the cokernal is as

follows:f/ty = w+x = K1f/uy = w+x = K1f/vy = w+x = K1f/wy = t+u+v = K2f/xy = t+u+v = K2f/y = tw+tx+uw+ux+vw+vx = t(w+x)+u(w+x)+v(w+x) = (w+x)(t+u+v) = K3 = K1K2

The function can be reduce to:f = K3y+z = (w+x)(t+u+v)y+z

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Multilevel Logic SynthesisMultilevel Logic Synthesis From F = K3y+z = (w+x)(t+u+v)y+z , there are only

7 literals and the resulting circuit diagram is shown below:

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Multilevel Logic SynthesisMultilevel Logic Synthesis A multi-output example: Consider following functions:

F1(t,u,v,w) = tv+tw+uv+uwF2(v,w,x,y) = vxy’+wxy’F3(u,v,w,x,y,z) = uv+uw+z’

There are 19 literals, the cokernel set is as follows:Cf1 = {t,u,v,w}Cf2 = {xy’}Cf3 = {u}

The kernel set is as followsKf1 = {v+w,t+u}Kf2 = {v+w}Kf3 = {v+w}

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Multilevel Logic SynthesisMultilevel Logic Synthesis From the kernel list, the common divisor is v+w Therefore the functions can be modified to:

f1(t,u,v,w) = g(t+u)f2(v,w,x,y) = gxy’f3(u,v,w,x,y,z) = gu+z’Where g = v+w

The logic circuit is given below

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Technology Dependent Technology Dependent SynthesisSynthesis Involves finding minimum cost covering of boolean

network by choosing from the collection of primitive logic elements in the target library

Optimization is done for both area and delay A simple approach for LUT-based FPGA architecture is

introduced

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Technology Dependent Technology Dependent SynthesisSynthesis For LUT-based FPGA architecture, we assume that

each LUT has at most 4 inputs The following steps are then followed:

The network is decomposed into nodes with at most 4 inputs

Reduce the number of nodes by combining some of them

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Language Structure SynthesisLanguage Structure Synthesis Synthesis tools perform the following tasks:

Detect and eliminate redundant logic Detect combinational feedback loopsDetect unused states Detect and collapse equivalent statesMake state assignments

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Synthesis of Assignment Synthesis of Assignment StatementsStatements Assignment statements including continuous and

procedural assignments are the most straight forward language structures in Verilog

Continuous assignment is basically an expression comprising of operands and operators

Almost all operators in Verilog HDL are synthesizable The exceptions include: case equality, arithmetic

shift, exponent and modulus operators

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Synthesis of Assignment Synthesis of Assignment StatementsStatements Synthesizable and non-synthesizable entities

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Synthesizable Non-synthesizable

Module instances, primitive gate, tasks

Timing constraints

Procedural assignments: always, if-else, case, casex, casez

Initial statements

Procedural blocks: begin-end, named blocks, disable statements

Loop statements: for, while and forever

Synthesis of Selection Synthesis of Selection StatementsStatements Selection statements and their synthesis results:

Depending on whether a design is combinational or sequential logic, only a part of the selection statement will be needed

For combinational logic an incomplete selection statements infers a latch

For sequential logic, there is no need to specify a complete selection statement

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Selection statement Synthesis results

If-else 2-to-1 multiplexer

Nested if-else Cascaded combination of multiplexers

Case Multiplexer

Incomplete if-else and case statements

Latch

Synthesis of Selection Synthesis of Selection StatementsStatements This shows that a latch is inferred by the synthesis

tool due to the lack of the else part in a combinational logic using and if-else statement

Code and RTL schematic

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Synthesis of Selection Synthesis of Selection StatementsStatements A complete if-else statement infers a multiplexer Code and RTL schematic:

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Synthesis of Selection Synthesis of Selection StatementsStatements An incomplete case statement (without default) infers

a latch Code and RTL schematic:

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Synthesis of Selection Synthesis of Selection StatementsStatements To prevent a latch from being inferred in a case

statements, the default must be included Code and RTL schematic:

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Delay ValuesDelay Values Synthesis tools ignore delay values This is because the ultimate delays of the network

will be determined by the actual delays of the gates used to implement the gate-level netlist

Delays are only used during simulations

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Delay ValuesDelay Values Ignored delay values – non synthesizable The example is a module of a four-phase clock

generator Code and testbench:

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Delay ValuesDelay Values Ignored delays – non synthesizable RTL schematic and waveform:

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Delay ValuesDelay Values A four phase clock generator – synthesizable version Code and testbench

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Delay ValuesDelay Values A four phase clock generator – synthesizable version RTL schematic and waveform

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Synthesis of Negative and Synthesis of Negative and Positive SignalsPositive Signals Positive and negative-edge clock signals are used to

perform operations in sequence Most synthesis tools support the mix use of two or

more different edge triggered signals but cannot accept the mix use of edge-triggered and level-sensitive signal in the same always block

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Synthesis of Negative and Synthesis of Negative and Positive SignalsPositive Signals This code shows the mix use of edge-triggered and

level-sensitive signals which is not accepted by synthesis tools

Try to synthesize this code and the error below will be generated:

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Synthesis of Negative and Synthesis of Negative and Positive SignalsPositive Signals An example of the mixed use of posedge and

negedge signals Code and RTL schematic:

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Synthesis of Loop StatementsSynthesis of Loop Statements Loop statements contain for, while, repeat and

forever For, while and forever are synthesizable except that

while and forever must contain timing control @(posedge) or @(negedge)

Repeat is generally not synthsizable To synthesize a for loop:

The elaborator unrolls the for loopThe synthesizer proceeds with analysis/translation and

logic optimization

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Synthesis of Loop StatementsSynthesis of Loop Statements An example illustrating the loop statement This example adds two n-bit operands and produces

an (n+1)-bit sum Code:

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This is what happens at the elaboration phase

Each statement corresponds to a full adder. The four full adders are then cascaded together as a 4-bit Ripple-carry adder

Synthesis of Loop StatementsSynthesis of Loop Statements An example illustrating the loop statement RTL schematic:

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