Synthesized processing techniques for monolithic integrationof nanometer-scale hole type photonic band gap crystalwith micrometer-scale microelectromechanical structures
Selin H. G. Teo and A. Q. Liua�
School of Electrical and Electronic Engineering, Nanyang Technological University,Singapore 639798, Singapore
M. B. Yu and J. SinghInstitute of Microelectronics, 11 Science Park Road, Singapore 117685, Singapore
�Received 22 December 2005; accepted 26 April 2006; published 28 June 2006�
The fabrication of photonic crystals1 �PhCs� has been afield of intense study2 since the proposals3,4 of photonic bandgap effect almost two decades ago. The challenges involvedin the fabrication of superdense, periodic deep submicrome-ter size PhCs sensitive to optical wavelengths require criticaldimensions �CDs� with periods of only a few hundred na-nometers and even smaller linewidths. Such high density ar-rays of CDs have been a nontrivial challenge in fabricationeven without the addition of other features,5,6 such as theintroduction of tunability into PhC devices.7,8 Yet, worldwideresearch efforts to realize tunable PhC devices for applica-tions with dynamic functionality,9 compensation of fabrica-tion deviations, or modulation of signals10 in ultrasmall sizeoptical integrated circuits11 remain intense. Mechanisms in-vestigated for these purposes include temperature control,12
liquid crystal effects;13 material nonlinearity,14 opticaltuning,15 and mechanical tuning mechanisms, of which, amicroelectromechanical system �MEMS� tuning method16,17
has been identified to be suitable in the application to flip-state modulations where the inflection of states for dynamicPhC devices is enabled with switching times in the order ofmilliseconds.18 Hence, tunable PhC devices designed with
a�Author to whom correspondence should be addressed; electronic mail:
1689 J. Vac. Sci. Technol. B 24„4…, Jul/Aug 2006 1071-1023/2006/
MEMS would allow for an active control of PhC deviceoutput levels, useful in the application to next generationoptical communication networks, and dynamic photonic in-tegrated circuit devices. However, the incorporation ofMEMS �Refs. 19 and 20� structures into PhC devices inevi-tably exacerbates fabrication challenges since MEMS fabri-cation by itself constitutes another set of specialrequirements21 in addition to those required by thenanometer-scale PhC structures.
The considerations necessary are as follows: To fabricatePhC devices operating at optical communication wave-lengths centered about 1550 nm, the corresponding CDs re-quired are in the hundred nanometer range. This requires notonly the reduction of the optical lithographic wavelengthfrom 365 nm i line to 248 nm, but also the ability of suchdeep ultraviolet �DUV� lithographic scanner systems to workat the sublithographic wavelength order. At the same time,because the ultrasmall CDs also shrink the process windowsof all the other processing modules, especially in dimensionsensitive reactions such as etching,22 advance fabricationtechniques for each of these fabrication modules need to bedeveloped.23
First, in patterning, albeit there are some other high reso-lution methods such as zone-plate-array lithography24
�ZPAL�, electron beam lithography25 �EBL�, holographic26
lithography �HL�, and focused ion beam lithography
1690 Teo et al.: Synthesized processing techniques for monolithic integration 1690
�FIBL�, DUV optical lithography27 �OL� was selected fordevelopment. This is because, although EBL �Ref. 28� is oneof the most commonly used methods to define PhC patternsdue to its ability to pattern arbitrary patterns at a very highresolution, it is affected by trade-offs between throughputand patterning flexibility. Such trade-offs in performance arealso faced by the other methods such as HL and FIBL. WhileZPAL is not constrained in this way, such systems are stillnot easily available. Therefore, in this article, the OL tech-nique was chosen for development in application to the PhCwith MEMS structures based on its inherent advantages ofhigh throughput processing and also on its flexibility in ex-posure pattern type and density. Yet, the use of OL is funda-mentally limited29 by its lithographic wavelength, and thediffraction limit defines the resolution of the smallest featurethat can be patterned. Hence, for a predetermined litho-graphic wavelength system, further resolution enhancementtechniques were developed to produce CDs smaller than thelithographic wavelength, using a method of pattern and par-tial coherence control.
Similarly, the challenges arising from the increased de-mand on CDs and reduced error tolerances30 are also en-countered for other modules of PhC device fabrication, es-pecially in etching and postprocessing. In etching, line edgeroughness,31 etch lag,32 and notching33 effects, which hastypical length scales in hundreds of nanometers to a fewmicrometers becomes critical to the successful fabrication ofthe hundred-nanometer-scale PhC CD structures. At the sametime, the other processes of electrode metallization,34 andpostprocessing buried oxide release35 �for air bridge PhCstructures and movable MEMS actuators�, also constitutechallenges arising not only from the requirement of materialcompatibility36 and contamination control,37 but also frometch aspect ratio specifications38 and movable structure re-lease stiction issues.39,40
To present the details of this work in a sequential order,this article is organized as follows: In the first section, thetechnical rationale behind the designed process flow is given.The specific challenges addressed in each of the processingmodules are presented in Sec. II. Specifically, Sec. II A de-scribes the development of the subwavelength OL with reso-lution enhancements using only a conventional binarychrome patterned mask, while Sec. II B describes the issuesof the resist deactivation for the chemical lithography devel-oping process. Sections II C and II D goes on to describe theetch fabrication of optical quality PhC structures withoutnotching damage. Finally, Sec. II E describes the modules forthe integration of metallic electrode-annealing; postprocess-ing CD etching by focus ion beam �FIB� milling, and alsothe release of movable micromechanical structures withoutstiction or electrode peeling. In Sec. III, the results of thefabrication process designed and verified to enable the real-ization of deep submicrometer size tunable PhCs withMEMS comb drive actuators �comprising interdigitatedcomb fingers and folded suspension beam structures�, re-
The design of the process flow is a critical factor in thefabrication of PhC with MEMS structures not only for aneffective development of each process module such that dif-ferent requirements with corresponding recipes may be dis-covered through a rigorous design of experiments, but alsofor the proper sequence of processing steps to prevent theelemental contamination of reaction chambers, material deg-radations, process overruns, etc. Figure 1 depicts a schematicof the integrated fabrication process flow for PhC withMEMS structures, which may be described in four mainparts: �I� film deposition for hard mask and electrode metal-lization, �II� PhC and MEMS comb drive CD patterning andtransfer, �III� optical testing structure �OTS� fabricationaligned to the PhC device, and �IV� PhC etching andpostprocessing.
Film material deposition processes were initiated with un-doped silicate glass �USG� on cleaned silicon-on-insulator�SOI� wafers. Following an electrode pattern opening in hardmask �Fig. 1�a��, copper seed deposition and metallizationplating �Fig. 1�b�� were carried out to enable the applicationof the MEMS actuation voltage. Planarization was then car-ried out using chemical mechanical polishing. To avoid con-tamination in subsequent steps, another layer of the USGfilm was deposited to cover the defined electrode �Fig. 1�c��.The deposition of this protective USG layer therefore com-pletes the first part of the thin film processes and lays foun-dation for the second set of steps necessary for a CD defini-tion. Here, PhC together with MEMS comb drive structureswere defined in photoresist on a layer of antireflection coat-ing �Fig. 1�d�� prior to the magnetically enhance reactive ionetching �MERIE� of PhC for a good profile transfer of CDsonto the hard mask layer �Fig. 1�e��. A complete resist stripafter this step �Fig. 1�f�� in the second phase then allows thethird phase of the OTS fabrication to begin.
Here, a different photoresist of higher viscosity was spunon thickly without first coating a bottom antireflection layer�Fig. 1�g��. Due to the shallow depths of the hard mask pat-terns defined in the previous phase, the resist coating recipemay be developed to successfully planarize the surface, en-abling the exposure of the second photomask after the align-ment to at least five underlying marks patterned during thefirst exposure �Fig. 1�h��. The testing structures exposed maytherefore be sequentially etched for the hard mask oxide, SOIdevice silicon, SOI buried oxide, then SOI handle siliconagain, till an etch depth of nearly 60 �m �Fig. 1�i��. This stepcompletes the construction of OTS, and the wafers undergothe final phase of PhC and MEMS actuator etching and otherpostprocessing modules.
In Fig. 1�j� photoresist stripping and polymer cleaningwere performed prior to the device etching so as to enable asimultaneous etching of both PhC structures and the OTSusing an etch recipe developed to optimize the etch qualityof the PhC devices. After a device sidewall optimization,
chemical buffered oxide etching �BOE� was then performed
1691 Teo et al.: Synthesized processing techniques for monolithic integration 1691
to release both the movable MEMS structures and the air-bridge-type PhC devices �Fig. 1�k��. In this step, not onlywas peeling of the metallic electrodes prevented; precautionwas also taken to ensure no further rework in case of con-tamination arising from the exposed electrodes. In Fig. 1�l�,FIB milling was performed on released PhC air bridge struc-tures to complete the process.
FIG. 1. Integrated fabrication process flow for PhC with MEMS structures. Slayers. Steps �d�–�f� describe the PhC and MEMS comb drive critical dimenlarge alignment structures, while steps �j�–�l� depict the oxide release and a
JVST B - Microelectronics and Nanometer Structures
A. Pattern and partial coherence control forsublithographic wavelength critical dimensionpatterning without phase shift masking
In the optical lithography experiments, the CD of thesmallest feature needed was less than the wavelength of thelithographic laser system. Such sublithographic wavelength
�a�–�c� describe the deposition of the metal electrodes and oxide hard maskpattern definition and transfer process. Steps �g�–�i� describe the opening ofostprocessing modules.
tepssionlso p
1692 Teo et al.: Synthesized processing techniques for monolithic integration 1692
OL is diffraction limited, and special efforts are needed toenable a successful patterning. In the past, the most straight-forward way to improve resolution was to decrease thewavelength of radiation, as illustrated in Fig. 2�a�. However,the reduction of the wavelength beyond ArF lasers emittingat 193 nm would require a drastic redesigning of the litho-graphic system since shorter wavelengths are simply ab-sorbed by the quartz lenses that direct the source light incurrent systems with laser wavelengths of 193–432 nm. Al-ternatively, resolution enhancement techniques41–43 �RETs�such as phase shift masking �PSM�, optical proximity correc-tion �OPC�, and off axis illumination �OAI� may be used forexposure systems with specific wavelengths to improve theirrespective resolution limits �as indicated by the line markedwith round symbols in Fig. 2�a�. While each of these tech-niques improves base line resolutions, they are limitedmainly by their respective drawbacks, which for PSM �Fig.2�c�� and OPC are the cost and computational efforts re-quired for implementation, while for the various OAIschemes illustrated in Fig. 2�b�, it is the discriminationneeded for varying pattern densities. Therefore, alternativeapproaches for achievement of subwavelength lithographyresolutions have been widely investigated in recentyears.44,45
In this set of experiments carried out to achieve a sub-
FIG. 2. �a� Illustration of resolution improvement through the reduction ofquadrupole schemes. �c� Phase shift masking technique with use of shifters wfor the depiction of maximum cone angles in the condenser and projection
lithographic wavelength OL, only conventional binary
chrome-on-glass photomasks of four times magnificationwithout phase shift features were used. A positive DUVchemically amplified resist �CAR� Shipley UV210 wascoated atop a bottom antireflection coating of Shipley AR3using a Tokyo Electron ACT8 wafer-track system. A DUVNikon S203B laser step and scan system was used for acontrolled 248 nm wavelength exposure.46,47 The SOI waferswere first prepared using standard steps of cleaning, particlecounting, and surface profiling before a blanket deposition of5000 Å USG using a Novellus Concept Two Sequel plasmaenhanced chemical vapor deposition �PECVD� system. Theuniformity of the hard mask and other characterizations werethen checked before the commencement of the lithographyprocess.
Here, in the development of the OL process, it was a keyconsideration that out of the major components used in a setof optical exposure system, the radiation source cannot beeasily changed as compared to the parameters of the con-denser, mask, wafer, pattern design, resist chemistry, coatingmechanisms, etc. The various parameters of the imaging sys-tem such as the lens set numerical aperture �NA� and thepartial coherence of the condenser system design can also bevaried for different lithographic performances. While anideal lithographic projection tool should be coherent with aunity NA �a measure of how well a lens is able to collect
cal lithographic wavelengths. �b� Off axis illumination of the annular andthe glass mask. �d� Schematic of an on-axis illumination lithographic system
optiithinlens.
diffracted light from a photomask and in turn project the
1693 Teo et al.: Synthesized processing techniques for monolithic integration 1693
image onto the wafer as illustrated in Fig. 2�d��, real systemswithout an immersion technology cannot provide a unity NAnor a purely coherent illumination since the total image is thesum of all the intensity images from all source points. Thedegree of the coherence factor is usually expressed as
� =NAc
NAp, �1�
where NAc=n sin �c and NAp=n sin �max represent the nu-merical aperture of the condenser and the projection lens,respectively which are in turn determined by n, the refractiveindex at the image plane; �max and �c are the maximum coneangles of rays subtended by the maximum pupil diameter atthe image and condenser planes, respectively �see Fig. 2�d��.
Based on the theoretical resolution limits of an otherwiseideal imaging system, the Rayleigh equation for the resolu-tion of the imaging system is given by
R = k1��/NA� , �2�
where � is the wavelength and k1 is the process dependentconstant. This equation not only provides the limits of OL asshown in Fig. 2�a� but also indicates the latitude of process-ing windows for different CDs. Hence, for 100, 200, and300 nm resolutions, the k1 process constant needed can becalculated as shown in Table I. Since controllable processestypically operate in the range of k1�0.6–0.7, it can be de-duced from the table that while the resolution near 200 nm isdifficult to achieve without a high NA, RETs are essential forCDs below 200 nm. At the same time, while lens with ahigher NA would be able to collect more diffracted ordersand consequently more information to correctly reproducethe required image, there would be an inherent trade off withthe depth of focus �DOF�, since
DOF = k2�
NA2 , �3�
where k2 is the second process constant. It is clear therefore
TABLE I. Process constants required for theoretical resolution limits of 100,200, and 300 nm linewidths by deep ultraviolet optical lithography.
that for a high resolution, increases in lens NA quickly de-
JVST B - Microelectronics and Nanometer Structures
creases the DOF, which should have preferably a large value�since tolerances for wafer flatness, resist coating, etc. aretypically in the order of a few hundred nanometers�. There-fore, an alternative control of the photomask pattern densityand the lithographic partial coherence should be used toachieve such similar resolution improvements. For a partiallycoherent system, the resolution of the imaging system can bedescribed with some correction to Eq. �2� such that
R = k1�
�1 + ��NA. �4�
Therefore, the increase of the coherence factor can be used toderive improved resolutions.
Based on this, critical linewidth experiments may be car-ried out. An optimized resist coating recipe was applied, firstwith wafer surface priming by hexamethyldisilazane for anadhesion preparation, followed by a layer of AR3 that wasspun at a combination of rotation speeds from1.5 to 4.5 k rpm for 40 s before it was baked at 205° for60 s. AR3 of 600 Å was then baked at 130° for 60 s. For theapplication of CAR with a thickness of 4800 Å, the resistwas spun at rotation speeds from 1.5 to 2.5 k rpm for 40 s.After a preexposure bake, the wafers undergo a wafer edgeexposure for the removal of edge beads formed in the resistcoating spiral stage �after about a thousand revolutions�.Linewidth experiments were then carried out using patternsof lines with widths of 200 nm and duty factors �line/spaceratio� of 1:3 and 1:1, as shown in Fig. 3. CDs of each set ofduty factor experiments were taken using a Hitachi 9200 CDscanning electron microscopy �SEM� system. Based on animaging system with a calibrated zero focus and a NA of0.68, the designed linewidths of 200 nm were used in litho-graphic experiments for � values of 0.38, 0.45, and 0.51.
The results of the partial coherence variation experiments
FIG. 3. Lithography experiment patterns with constant linewidths but differ-ent pattern density of line/space duty factors of �a� 1:3 and �b� 1:1,respectively.
were plotted as measured CDs with respect to the exposure
1694 Teo et al.: Synthesized processing techniques for monolithic integration 1694
dosage used, as shown in Fig. 4. From the CD plots of thelinewidth experiments, it can be seen that the 1:3 densitypatterns are much more sensitive to coherence factor varia-tions than the 1:1 ones. Especially, the 1:3 density patternshave measured linewidths which were drastically reduced forthe exposure with a coherence factor of 0.51 as compared tothe exposures with coherence factors of 0.38 or 0.45. On theother hand, the higher density 1:1 patterns had similarly re-duced linewidths for all three coherence factors used. Fromfurther such experiments, it was obtained that the reductionof original linewidths to less than 200 nm allowed for a fur-ther reduction of CDs obtained. However, such progressivereduction of design linewidths for the corresponding reduc-tion of CDs approaches its limit at a drawn linewidth of130 nm. This is due to the reduced process window of thesmaller CDs, where small deviations in exposure and focus
FIG. 4. Critical dimension plots for lithographic experiments with a constantNA of 0.68 and varying coherence factors of 0.38, 0.45, and 0.51 for linepatterns with duty factors of �a� 1:3 and �b� 1:1.
Examples of typical exposure failures, brought about bysuch constraints, are shown in Figs. 5 and 6, where in Fig.5�a�, unresolved features result from an insufficient exposuredosage in spaces between dense line patterns, and in Fig.5�b�, resist peeling occurs at narrow ends of line patterns dueto overexposure. In Fig. 6, there is the necking effect, wherebiasing of patterns near line terminations is required in orderto prevent neck breakages at line ends. The layout and expo-sure lithographic variations are shown for a narrow line end�Fig. 6�a��, where there is the pull-back mechanism, and fora connected line end �Fig. 6�b��, where there is the flaringmechanism at the end of connected lines. Combined to-gether, these two effects constitute the mechanisms for neck-ing such that the pull-back mechanism coupled with flaringin the mild case leads to patterns of critical linewidths withconstricted “neck” interfaces, as shown in Fig. 7�a�. In theunbridled case of necking, extreme constrictions leading tocritical line breakages at the line-base interface are shown inFig. 7�b�.
B. Resist poisoning in PhC lattice sites
A DUV radiation exposure on the CAR results in the for-
FIG. 5. SEMs of sublithographic wavelength exposure failures for �a� unre-solved dense structures �b� and lifted off resist.
mation of minute catalytic amounts of acids in the exposed
1695 Teo et al.: Synthesized processing techniques for monolithic integration 1695
areas of CAR as determined by the openings on the chromephotomask. A subsequent processing by acid chemical-amplification processing then allows the CAR to becomesoluble in the alkaline-developer solution, allowing the re-moval of the exposed resist. If, however, the minute acidformed during the exposure is unintentionally quenched bybase impurities on the wafer or in the environment, thechemical amplification can be deactivated, causing an erro-neous patterning where CAR are not effectively removed bythe developer where an opening should be. This type of “re-sist poisoning”is illustrated, for example, in Fig. 8�a�, wherea PhC lattice of holes was patterned and some holes are notproperly developed to result in positions of missing holes.Such defects install optical states within band gap frequen-cies which can become microcavities that act as unintendedresonators �Fig. 8�b��. To prevent the formation of such de-activated CAR, the presence of a weak base pyrimidine�C4H4N2� resulting from a treatment with a solvent should beavoided with a minimization of the resident time after thesolvent cleaning process for a successful lithographicpatterning.48 It is important to avoid such instances of resistpoisoning since reworks are not only complicated but arealso often ineffective.
C. Dense deep submicrometer critical dimensionreactive ion etching profile control
To transfer the PhC patterns onto the device silicon, aMERIE recipe comprising a mixture of oxygen, argon, andcarbonated fluoride chemistry was first used to transfer theCAR patterns onto the USG hard mask layer. After this, asurface technology system etcher with ICP sources for an
FIG. 6. Schematic illustration of layout vs lithographic variations due to �a�a pull-back mechanism at the line end and �b� a flaring mechanism at theend of connected lines, combined to the cause “necking.”
independent control of plasma generation �coil� and biasing
JVST B - Microelectronics and Nanometer Structures
�platen� rf power was used to carry out the Bosch process,49
where time multiplexed etching and passivation processingallow for an abrupt application of reaction gases within theetch chamber. In this process, a silicon opening unprotectedby a masking material is first etched using fluorinated gaschemistry comprising mainly of sulphur hexafluoride �SF6�.Through the action of electron impact dissociation, reactiveions and ion-assisted fluorine radicals react with siliconopenings to form volatile silicon by-product gases which arethen removed to give an isotropic profile. This completes theetching phase, which is followed by the passivation phase,where octafluorocyclobutane �C4F8� gas was applied as aprotective polymer coating on both lateral and vertical sur-faces. Repeated cycles of etching and passivation thereforeconstitute the time multiplexed scheme of deep reactive ionetching �DRIE�. Especially, in such etching process, reactiveetching species are directed onto the wafer surface with theassistance of high platen power biased in the vertical direc-tion. Therefore, etching becomes much more significant inthe vertical rather than in the lateral directions. Since the rateat which fluorine radicals are bombarded onto the horizontal
FIG. 7. �a� Patterns of critical linewidths with constricted “neck” interfaces.�b� Extreme constrictions leading to critical linewidth breakages at the struc-ture interface.
surface far exceeds that of the vertical ones and passivation
1696 Teo et al.: Synthesized processing techniques for monolithic integration 1696
is continuously applied throughout the process, high etchingrate can be achieved together with a high mask selectivity.Hence, only a thin layer of hard mask is needed for etching,which in turn would require only a thin layer of CAR forMERIE patterning. In this way, a high selectivity of the etch-ing process allows for a high resolution patterning since athinner resist allows for a greater demand on lithographicCDs.
FIG. 8. �a� Cubic PhC hole array patterns with areas of resist poisoning�missing holes in uniform hole arrays�. �b� Unintended resonators formwithin the PhC hole lattice.
TABLE II. Etch and passivation time multiplexed reactive ion etching procvertical types.
In the experiments to develop DRIE conditions that allowthe realization of the superdense PhC arrays, the coil powerof the rf source was maintained at 600 W while the variedplaten power was applied for the bias of ions energetic in thevertical direction, normal to the wafer surface. For a chem-istry dominated by passivation, a slopped sidewall profiletends to result in gradually reduced etch openings that oftenresult in eventual self-induced etch stops. Conversely, an in-sufficient passivation causes loss in anisotropy such that lat-eral etching increases to result in retrograde sidewalls. Toavoid such sidewall profiles, etching and passivation processparameters can be delicately balanced in such high densitydeep submicrometer CD arrays to give conditions of sloped,retrograde, or vertical sidewall profiles, as given in the pro-cess parameters listing of Table II. Here, with time multi-plexed reactive ion etching �TMRIE� listed in condition IIIof Table II, the etch profile of the CD structures can be mod-erated to obtain nearly vertical sidewalls, as shown in thecross sectional SEM of the etched PhC holes lattice in Fig. 9.
D. RIE lag and notching of PhC device at buriedoxide interface
For etch patterns with different opening sizes, etch ratesvary according to the effect of the aspect ratio resulting inthe RIE lag. For etch openings of different linewidths, theetch rates vary drastically. This can be seen from the crosssectional SEM image of Fig. 10, where the most drastic dif-ference in etch depth was obtained for the OTS structureswith ultrawide etch areas, while for the thinner line patternson the left, correspondingly increased etch depths were ob-served with progressively increasing linewidths. Such varia-tions in etch rates with respect to aspect ratios and etch open-ing sizes arise as a result of several etch mechanisms, someof which include the ion and kinetic neutral shadowing ef-fects, the transport of etch reactants toward and away fromthe etch surface, and the effect of electrical charges on theetch surface. One of the most prominent of these would bethe transportation of etch reactants, which becomes progres-sively inhibited for narrower trenches. This is similarly so forthe charge effect on the etch surface, where the charge dis-tribution on the etch surfaces tends to be more highly con-centrated in smaller etch surface opening areas than in largerones. Hence, a higher charge density at the bottom of smaller
arameters for various etch sidewell profiles of the sloped, retrograde, and
1697 Teo et al.: Synthesized processing techniques for monolithic integration 1697
trenches tends to result in the repulsion of incoming chargedreactive species, which acts to reduce or even prohibit furtheretch actions eventually.
Such charge accumulation effect also comes into play inanother circumstance—notching of the device silicon at thedevice and buried cladding oxide interface. This critical RIEeffect is an important consideration in the SOI device etch-ing. A SEM of this type of etch problem is as shown in Fig.
FIG. 9. �a� Top view of PhC hole lattice with the dashed line showing wherethe cross section was taken to yield, �b� cross sectional SEM of PhC withcontrolled etch/passivation parameters yielding vertical sidewall profiles.
FIG. 10. RIE lag by aspect ratio dependent effects in plasma etching asshown for the high density pattern on the left of the SEM and the large OTS
opening on the right.
JVST B - Microelectronics and Nanometer Structures
11�a�. Here, there is a severe undercut of the silicon PhC nearthe bottom of the device, at the interface of the buried oxidelayer. This is due to the accumulation of positively chargedreactive ion etching species pulled down deep onto the etchsurface by the vertical platen bias power. Such residualcharge accumulation on the etch surface acts to deflect fur-ther incoming positive species when etching proceeds untilthe etch stop buried oxide charge insulating layer. This re-sults in the lateral etching of the PhC structures near thedevice-cladding interface, as the etch species are deflectedonto the sidewalls, as can be seen in Fig. 11�b�. In the case ofmild notching, the performance of the fabricated PhC struc-tures would be adversely affected. However, if notching dueto overetching was allowed to become extensive, then a totaldestruction of the designed device would result. To preventthis problem, this process was therefore designed as de-scribed in Sec. II such that only similar etch opening sizesand etch depths are required for each etch step. In this way,drastic etch lag effects would not result in the undercutting oflarger etch features at the etch stop layer due to the overetch-ing time required to complete the etching for the narrowestopenings. Otherwise, the use of the periodic dischargingtechnique to remove accumulated charges leading to sidewalldeflected reactive ion etching �through periodic plasma dis-charging� is another tool related method to ameliorate notch-ing effects.
E. Integrated metallization processing, air bridge,and movable structures released from buriedoxide layer and etching on critical dimensionsby focused ion beam milling
In the postprocessing process of the PhC, MEMS, andOTS devices, thermal oxidation was performed to improvethe optical quality of device sidewalls through the smooth-ening of sharp facets. To enable the high temperature furnaceprocess, a total strip of photoresist was necessary to avoid anorganic contamination of the oxidation chamber. Through awet clean recipe of piranha bath consisting of sulfuric acid�H2SO4� and hydrogen peroxide �H2O2� at high temperatureof 130 °C, the polymers and remaining photoresist left overin the lithographic and etch process were removed and in-spected under a defect review scanning electron microscopewith energy dispersive x-ray analysis to ensure a completestripping. The cleaned wafers were then oxidized in the fur-nace at 1050 °C for 90 min, consuming silicon at a rate ofabout 0.4 times the rate of oxidation. For oxidation of1000 Å thickness, the sidewall edges of the time multiplexedDRIE etched sidewalls �Fig. 12�a�� are then rounded withreduced scallop depths �Fig. 12�b��. Therefore, the opticalquality of the fabricated device was improved and the opticalscattering due to sidewall roughness was reduced.
Next, in the integration of electrode metallization for theMEMS comb drive electrodes, Cu seed deposition was firstcarried out using physical vapor deposition �PVD� for a con-formal film of 250 Å tantalum �Ta� before the deposition ofcopper on top of the Ta layer which proceeded until a con-
formal coating was formed. Following the seeding, the actual
1698 Teo et al.: Synthesized processing techniques for monolithic integration 1698
Cu film thickness required was then applied by electrochemi-cal plating �ECP�. In the plating cell, the Cu plating processwas carried out with CuSO4, H2SO4, and DI water solutionbaths. After plating, the wafer surface was cleaned by a DIwater spray in the postplating module. Postannealing at200 °C was then carried out before the Cu film was chemicalmechanically polished to achieve the required planarizedstack thickness and also to remove unwanted Cu over areasthat should not be coated. This planarizing step thereforeenables a subsequent processing of high resolution lithogra-phy after another USG deposition was carried out for coverover the metal electrodes �thereby preventing subsequent
FIG. 12. Postprocessing for �a� device sidewalls with undulating time mul-tiplexed sidewall scallop roughness. After the thermal oxidation, �b� sharp
edges of the roughness on device sidewalls are visibly reduced.
processing contamination�. Upon completion of subsequentclean room processes, the defined Cu electrodes were ex-posed in the final phase using buried oxide etch �BOE� re-lease which removes silicon oxide at a rate of 2500 Å/min.The wafers released with the wet etch bath �comprising am-monium fluoride and hydrofluoric acid� are then cleanedwith DI water. For clean wafers spun dry at standard quali-fied recipe of 1800 rpm, peeling of the thinner metal elec-trodes with less area of adhesion to the underlying devicesilicon results �Fig. 13�. To prevent such defects, two ap-proaches may be taken, namely, to reduce the spin speed ofthe dryer to 300 rpm or to alternatively allow the wafers tobe evaporated dry after an isopropyl alcohol bath rinse �with-out undergoing spin dry�. Although the latter method wasmore time consuming and less precise, its advantage overspin drying is the reduced likelihood for the occurrence ofstiction �the permanent sticking of released movablestructures�.
Therefore, following the sidewall optimization and buriedoxide release, the movable MEMS, PhC air bridge structure,and OTS were realized. A final FIB milling was then carriedout on the CD of the PhC air bridge. Here, the FIB systemuses liquid metal ion sources to form very small probes withhigh current densities. Where such high density ion beam
FIG. 11. Notching of a SOI wafer, as shown in the �a�SEM of PhC hole array etched into silicon and “etchstopped” at the buried oxide interface. �b� Schematicillustration of the charge buildup effect causing furtherincoming ions to be deflected onto sidewalls.
FIG. 13. Peeling of electrode copper metallization after the buffered oxide
etch and spin drying.
1699 Teo et al.: Synthesized processing techniques for monolithic integration 1699
strikes the required points on the silicon air bridge, siliconmaterial was removed through a physical sputtering process.To carry out FIB milling on a CD structure, it was importantthat surface oxide was removed prior to the processing sothat the effects of charging can be minimized for a sharperscanning electron imaging and therefore a more precise spa-tial milling. Optimized conditions were found for a magnifi-cation of 35,000 times and a beam duration of 8 s for eachPhC hole milling. For higher order of magnifications used,greater imaging precision was adversely affected by the in-creased specimen charging effect that reduced the resolutionof the PhC holes patterned.
III. RESULTS AND CONCLUSION
A synthesis of fabrication processes, including deep UVlithography, time multiplexed RIE, structural release, andFIB milling on PhC CD structures, was realized to enable amonolithic integration of PhC optical structures with MEMSactuation devices. Figure 14�a� shows the fabricated PhCMEMS microactuators with the interdigitated comb fingers�supported by the folded suspension beam structures� to-gether with the PhC air bridge CD structure and orthogonalOTS. Figure 14�b� shows the close up SEM of the air bridgestructure with FIB milled PhC holes of 200 nm diameters,defined within a CD of 470 nm width. Here, for the foldedsuspension beam system, the displacement relationship ofthe comb drive with the voltage applied can be modeled asthe force generated Fx, being a ratio of the spring constant kz
of the suspension so that actuation is given as
x =Fx
kx=
V2�N�tbeam/d�2Etbeam�BW/BL�
, �5�
where � is the permittivity of free space, V is the voltageapplied across the electrodes, N is the number of comb fin-gers, d is the gap distance between the comb fingers, E is theYoung’s modulus of silicon, t is the thickness of the struc-tures, and BW and BL are the width and length of the sus-pension beams, respectively. Based on this model of thefolded suspension beam comb drive structures, the simulatedvoltage actuation behavior is plotted as a smooth line in Fig.15 where the abscissa plots the applied voltage and the ordi-nate plots the comb drive displacement distance. Also plottedon the same graph are the corresponding measurement re-sults for the mechanical testing experiments, where the directcurrent voltage was applied to the electrode of the staticcomb while the ground potential was maintained on the elec-trode of the moving comb. Based on the captured images ofthe comb fingers at different applied voltages, the displace-ment distances for the various applied voltages were ana-lyzed using image processing techniques to obtain the physi-cal displacement values for each actuation voltage, which arethen plotted as plus ��� symbols and connected by dottedlines on the graph of Fig. 15. A lateral instability was alsomonitored in the orthogonal direction using the same methodand plotted with cross �x� symbols connected by dashedlines. As can be seen from the results of Fig. 15, the theoret-
ical model describes the characteristics of the fabricated
JVST B - Microelectronics and Nanometer Structures
structures well in the actuation direction and reveals the lim-its of the operation till pull-in occurs, such that an effectivevoltage stability up to 20 V is determined. Other optical test-ing experiments for the PhC devices modulated by the move-ments of the MEMS actuator structures are still undergoingand will be presented in full detail in a future article.
To conclude, in the fabrication of tunable PhC withMEMS structures for disparate patterns and device etchdepths, many techniques were developed to overcome theunavoidable challenges. The foremost include the design of afeasible processing flow that allowed for both PhC CD defi-nition and etch together with actuator electrode metallizationand also suspended released structures. Through the investi-gation of each process module to satisfy the demands of thedevice operating specifications �such as the PhC device op-erating at the canonical optical communication wavelengthsand MEMS actuation voltage requirements, etc.�, insightsderived were applied to each module. In the first part of theprocess, an alternative method for the achievement of thesublithographic wavelength linewidth patterning, not com-
FIG. 14. �a� SEM of MEMS actuator comb drive fingers and folded suspen-sion beams with PhC structures and OTS. �b� FIB milled PhC holes on thereleased critical dimension air bridge structure.
monly used in RETs such as PSM, OAI, and OPC, was de-
1700 Teo et al.: Synthesized processing techniques for monolithic integration 1700
rived. Using low lithographic system requirements of a deepUV scanner working at a wavelength of 248 nm, chemicallyamplified photoresist coatings, and conventional chrome-on-glass photomasks, without expensive phase shift features orOAI systems, the sublithographic wavelength CDs were ob-tained using pattern and partial coherence control. Here,based on the key factors of pattern density bias and imagingsystem partial coherence variations, a smallest resolution of36%, that of mask value, can be obtained for a resolution of75 nm using a 200 nm binary photomask pattern. While thelimit in the reduction of design linewidths and types of pat-tern together with constricted patterning at the line/base in-terface by line end necking are the limitations of this devel-oped technique; the advantages of this method are itssimplicity and cost effectiveness for the enhancement of theresolution without the use of an expensive PSM or high-endcompensation computation technique, through simplifiedmask making requirements and a reduced demand on theexposure hardware sophistication. Such a derived methodtherefore may be used not only for PhC and deep submi-crometer sized MEMS structures, but also for applicationssuch as metal-semiconductor-metal photodetectors, nano-electromechanical structures, etc.
At the same time, besides the description of the issue ofresist poisoning in the patterning experiments, the etch lageffects and notching of devices at the interface of the silicondevice and the buried oxide layer were also presented for thesimultaneous implementation of PhC with MEMS actuators.The techniques of the FIB milling in the finalization step ofthe processing following the buried oxide release for PhCstructures on CD structures enabled a wide processing win-dow for both lithography and etch phases, avoiding severeloading effects caused by disparate pattern dimensions �suchas etch lag and notching�. Besides the realization of the deepetching TMRIE for the wide OTS grooves, PhC structures
FIG. 15. MEMS comb drive voltage actuation experiment results of mea-sured displacement plotted with theoretical simulations for progressivelyincreased applied voltage till “pull-in” instability occurs.
were also optimized through the delicate etch and passiva-
tion multiplexing balance and also through thermal oxida-tion. The effect of such fabrication process design not onlyaddressed challenges arising from the need to incorporatestructures with vastly different dimensional specifications,but also incorporates advantages of a batch processing capa-bility with a manufacturing compatibility to other silicon de-vices. By a careful development of each experiment processmodule, a high resolution MEMS tunable PhC for use at anoptical communication wavelength of 1550 nm was yieldedsuch that a monolithically integrated tunable PhC was fabri-cated simultaneously with electromechanical actuators inmixed densities of superdense PhC holes, dense line patterns,isolated waveguide structures, and ultrawide OTS groovesthat were defined as aligned to the deep submicron size PhCdevices.
ACKNOWLEDGMENTS
The authors are grateful to the Agency for Science, Tech-nology, and Research �A*STAR� Singapore for the AGS fel-lowship provided to the first author. The authors sincerelyacknowledge support from all staff of the Photonics Lab inthe Nanyang Technological University and the Deep Submi-cron ICs Lab of the Institute of Microelectronics.
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