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Synthesizer Tutorial V. S. Reinhardt Page 1Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Frequency and Time SynthesisA Tutorial
Victor S. ReinhardtJune 6, 2000
Synthesizer Tutorial V. S. Reinhardt Page 2Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Frequency and Time SynthesisTutorial Organization
• Basic Concepts– What is a Synthesizer?– Basic Concepts of Frequency and Time Synthesis
• Direct Analog Synthesis– Analog Building Blocks– (Digital Building Blocks used to Generate Frequencies)– No VCO’s
• Indirect Synthesis– Uses Phase or Frequency Locked VCOs
• Direct Digital Synthesis– Uses Digital Processing Techniques to Generate Output– Digital Circuits used to Process Numbers– No VCO’s
Synthesizer Tutorial V. S. Reinhardt Page 3Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Synthesizer
One or More
Reference Sources
Output fo
fr1
frN
...
Basic ConceptsWhat is a Synthesizer?
• One or More Input Reference Sources fr1…frn
• Translation to New Frequency fo
• Phase or Frequency Coherent With References
• Basic Properties– Frequency Range– Frequency Resolution– Switching Rate/Settling Time– DC Power, Weight, Cost, etc.
– Phase/Frequency Stability (Time Domain, Environmental Effects)
– Spectral Purity (Frequency Domain, Spurs, Noise)
Synthesizer Tutorial V. S. Reinhardt Page 4Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Ideal Periodic Waveform
• Periodic Function F(V = A F()= Phase of FunctionF(2) = F()
• In Time Domain= ot
o=Angular Frequency
o= 2fo
fo = 1/To = Frequency
• not a True Observable– Measurement Depends on
Inverting F()– Must Keep Track of Number of
Cycles for Multiples of 2– Best Determined at Zero Crossings
where Slope Large
Amplitude A
Positive Zero Crossingsat tn=nTo
n=2n
t
Amplitude At
Period To
=2
V
V
Sine WaveSine Wave
PulsePulse
Synthesizer Tutorial V. S. Reinhardt Page 5Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Non-Ideal Waveform
• Amplitude and Frequency Now Function of Time
• Angular Frequency Error
= d/dt
• Frequency Error f
f =• Fractional Frequency
Error y
y = = f/fo
y = (d/dt)
t
V
Zero Crossing Variation
Time or Phase Error
Peak Variation
Amplitude Error
• Force Nearly-Periodic Waveform into Periodic Form
V = ( A + a(t) )·F[ ot + (t) ]
a(t) Amplitude Error
(t) Phase Error
Synthesizer Tutorial V. S. Reinhardt Page 6Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Additive Noise and Phase & Time Error
• Additive Noise V Generates Phase Error
t = V(t)/A
– in Radians Equivalent to Noise/Signal Ratio
– dB() Equivalent to dBc
• Time Error in Positive Zero Crossing
t = - = -V/(A)
– Note Minus Sign
– Positive V Negative t Positive
, t
V
For Sine Wave Near Zero
V = A(ot+(t))
V
t
For Non-Sine Wave: Effective A is Determined by Slope Near Zero
Complex Representation
VI A VQ
VI = VQ = V
Synthesizer Tutorial V. S. Reinhardt Page 7Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Clock Reading vs Time Error
• A Basic Clock Contains a Frequency Reference and a Cycle Counter
• Zero Crossing Time Error t = - – Compares Equivalent Zero Crossings
at Different Times
• Clock Reading Error x = – Compares Cycle Counts or
Normalized Phases at Same Time
• Note That x = y dt But t = - y dt
x
t
Ideal Source
fo
FrequencyReference
CycleCounter
Basic Clock
x
Synthesizer Tutorial V. S. Reinhardt Page 8Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Ideal Coherent Synthesizer
• Coherent Frequency Translation by Factor K– Multiplies the Input Frequency fr
by a Factor K– Ideal: Doesn’t Add Noise
• Input Phase Error r Also Multiplied by K– The Phase Error Integral of the
Angular Frequency Error
• The y and x of a Reference Oscillator are Independent of the Final Output Frequency
yo =o
o
Kr
Kr
r
r= = = yr
xo =o
o
Kr
Kr
r
r= = = xr
fr
FrequencyReference
IdealCoherent
Synthesizerr
fo= Kfr
o= Kr
Synthesizer Tutorial V. S. Reinhardt Page 9Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Spectral Density Review
• A Random Variable u(t) is Wide Sense Stationary if the Autocorrelation Function R is only a Function of Ru() = T-1T u(t+)u(t) dt
• The Spectral Density is the Fourier Transform of Ru() Su(f) = ej2ft Ru() d
• For Frequency Translation K S-output(f) = K2 S-input(f)
Sy-output(f) = Sy-input(f) Sx-output(f) = Sx-input(f)
Sy(f) = 2Sx(f)
Sy(f) = S(f) 2
2
y(t) = dxdt
y(t) = o-1 d
dt
U(f) FilterH(f)
V(f) = H(f)U(f)
Sv(f) = |H(f)|2Su(f)
Important Property of S(f)
Synthesizer Tutorial V. S. Reinhardt Page 10Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Spurs in Time Domain
• Spurious Signal Rotates around Main Phasor at 2f
• Time Domain Measurements are Sampled at Multiples of
tn = nTo
• Generates Regular Pattern at Aliases of 1/f
V o(t) Spur at
fo+f
Discrete Samples When Phasor Crosses Real Axis
o
f
Phase Error Plot
NoiseSpur
Allan Variance
Counter Histogram
x
Phasor Diagram
Synthesizer Tutorial V. S. Reinhardt Page 11Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Direct Analog Synthesis
• Directly Generates fo Frequency without VCO
• Multiplicative Devices– Multipliers – Dividers– x Conserved
• Additive Devices– Mixers
• Others – Filters– Switches– Amps
• Also Add Their Own Noise
f x N Nf
Multipliers
÷ M f/Mf
Dividers
f1
f2
fn
.
.
.
.
fo
Switches
fa fbfb
fa
Mixers
fa+fb+fc
fb
Filters
Amplifiers
N /Mx x
x xfin
fout
x x
Synthesizer Tutorial V. S. Reinhardt Page 12Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Typical Direct Analog Synthesizer: Divide & Mix
• Two Parts of Synthesizer
• Switched Reference Section– Generates References 0, fr,…9fr
– Switch Refs to LO’s f1, f2,, f3 …
• Divide and Mix Section (3 Stages Shown)– Divide f3=N3fr by 10
– Mix with f2=N2fr and Filter to Produce f2+f3/10 (Bypass Mixer if N2=0)
– Repeat Divide, Mix, and Filter with f3=N3fr
• End Result
fo = [N1+ N2/10+N3/100 + …]fr
– Each N Selects Digit of Output
+ 10
f3=N3fr
f3/10f2=N2fr
f2+f3/10
f1=N1fr
+ 10
fo = f1+ f2/10+f3/100
fr
ReferenceGenerator
fr2fr9fr...
SwitchMatrix
f1f2f3...
fk=Nkfr
(Nk = 0 to 9)
Synthesizer Tutorial V. S. Reinhardt Page 13Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Component Design Parameters
• General Parameters– Frequency Response– Speed (Switches)– DC Power– Cost, Weight, & Size
• Phase Noise (See Left)
• Phase Stability (Time, Environment)– Filters: Phase Shift over
Temperature Critical Issue
• Spurs– Mixing IM’s– Switches: On/Of Loss Ratio
Determines Spurs– Unwanted Multiplier Orders
Phase Noise Characterization of Devices
S(f)
f
1/f Noise
White NoiseFloor
1/f Knee
Cascaded Multipliers & Dividers
xN1
• These Most Critical for S(f)• Make Lowest Noise and Highest N• All x Contributions the Same
Si 1-10 KHzGaAs, InP 0.1-1 MHz
1/f Knees
÷N3
xN2
÷N2
xN3
÷N1
Synthesizer Tutorial V. S. Reinhardt Page 14Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Frequency Dividers (Counters)
• Asynchronous (Ripple)– Lowest Power – Most Phase Variation (Cascading Delays)– Can Use Clean-up Circuit
• Synchronous– High Power – Lowest Phase Variation
• Dual-Modulus – Almost Lowest Power– Low Phase Variation – Limit on Divide Number
• Regenerative & Analog Dividers– Can be Very Simple & Low Noise– Limited Frequency Range– Susceptible to Cycle Slips
finOneShot
foutf’out
Clean-up Circuit
...
fin
fout
FF
Synchronous Counter
FF FF
fin
Asynchronous Counter
...fout
FF FF FF
finDelay
fout
RegenerativeDelay- Divider
R-SFF Q
Reset
Set
Synthesizer Tutorial V. S. Reinhardt Page 15Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Dual Modulus Counter
• Dual Modulus Counter– High Speed Dual Modulus (÷ P/P+1)
Prescaler– 2 Low Speed (÷M, ÷A) Counters
– fout = fin/(MP+A) M P, A = 0 to P-1– Minimum Divide Ratio = P(P-1)
• Operation– Prescaler Starts with ÷(P+1)– Prescaler Switches to ÷P when A Count
Reached – A and M Counters Reset when M Count
Reached (Thus Must Have M A) – Prescaler Switches Back to ÷(P+1)– For Contiguous Divide Numbers
A = 0 to P-1 (so Must Have M P-1)
DualModulusCounter
÷ P/P+1
ACounter
MCounter
÷A
P/P+1Control
fin÷
Out
÷M
fout
Reset
Reset
Synthesizer Tutorial V. S. Reinhardt Page 16Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Frequency Multipliers
• 1. Resistive Diode and Mixer– Broadband & Loss– Low Efficiency for High Harmonics
• 2. Step Recovery Diode & Varactor– Narrowband (to Match 5 Input Z)– Higher Efficiency for High
Harmonics
• 3. Transistor– Highest Efficiency (Gain)– Too High Drive Can Cause Slow
Damage from Avalanche Breakdown
• 2 & 3 Susceptible to Parametric Oscillations
NonlinearDevice Filter
f Nf
Good Efficiency Limit Nf 1
Sharpness of Distortion Features () Determine
Amplitude of High Harmonics
Device Degradation Due to Overdrive
Synthesizer Tutorial V. S. Reinhardt Page 17Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Mixers
• Many Types of Mixers– Single Device– Single, Double, Triple Balanced– SubHarmonic (Doubles LO Input)– Single Sideband
• Higher Order Mixers Suppress Spurious Mixing Products– fspur = NflO - MfR
– (N,M) = Spur Order
• Major Issue: Keeping Spurs Away From fIF
fLOfR
fIF
0 1 2 3 4 5 6 7 80 29 20 32 24 29 27 30 291 24 0 35 11 42 19 50 39 492 64 71 62 70 63 70 61 62 643 81 73 85 69 85 68 85 64 874 88 91 99 92 90 95 87 94 875 99 86 99 95 99 99 99 90 996 99 99 99 97 99 99 99 99 997 99 99 99 99 99 99 99 99 99
Har
mo
nic
s o
f f R
Harmonics of fLO
IF to Spur Ratios (dB)(WJ-M9E)
Synthesizer Tutorial V. S. Reinhardt Page 18Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Indirect Synthesis
• Utilizes Phase or Frequency Locked VCO to Act as:
• Operation Inverter– VCO Output fo Goes Through
Frequency Translation T(fo)– Phase or Frequency Discriminator
Compares fr to T(fo) and Generates Error Signal
– Through Loop Filter and VCO Frequency Control, Error Signal Driven to Zero so fr= T(fo)
– Thus VCO Output is Inverse of Tfo= T-1(fr)
• Tracking Filter– Uses Bandwidth Properties of Loop
to Filter Reference Signal
LoopFilter
fo = Nxfr
fr
÷N
fo/N
VCO
Example: Divider Loop
ErrorSignal
VCOLoopFilter
Phase orFrequency
Discriminator
fo = T-1(fr)
FreqControl
ErrorSignal
T(fo)
fr
Indirect Synthesis
FrequencyTranslation
Synthesizer Tutorial V. S. Reinhardt Page 19Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Basic Phase Locked Loop
• Definitions– Open Loop Gain G(f)– Output Phase Error – Reference Phase Error r
– VCO (Free Running) Phase Error o
• Closed Loop ResponseH(f) = /r = G(f)/(s + G(f))
– H(f) has Low Pass Response with Knee at fn
– 1-H(f) has High Pass Response with Knee at fn
• Output Phase Error = H(f)r + (1-H(f))o
– Reference Characteristic f << fn
– VCO Characteristic f >> fn
Vi = r-
VCO
r
= o- Vo/s
G(f) Vo Vi
Vo = G(f) Vi
1-H(f)1
f
fn
H(f)1
f
fn
Idealized PLL
Synthesizer Tutorial V. S. Reinhardt Page 20Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Optimum Loop Bandwidth
• Free Running VCO:– Higher Near In Noise– Lower White Noise Floor
• Reference– Lower Near In Noise– Higher White Noise Floor
• Optimum Loop Bandwidth fn for Integrated Noise is Where Curves Cross
• May Have Other Reasons not to Choose this fn Such as Settling Time Requirement
S(f)
f
Free Running VCO S(f)
Reference S(f)
OptimumPLL S(f)
Optimum fn
Synthesizer Tutorial V. S. Reinhardt Page 21Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Oscillator Noise Characteristics
• Simple Oscillator Model
• Amp NoiseSa(f) = (FkT/Pin)·(1 + ff/f)
• Leeson’s Equation– Net Phase Around Loop = 0
R = -a = -2QL·y
– Note Resonator R vs y slope Controls Oscillator Frequency
– Thus Amp Phase Noise is Converted to Oscillator Frequency Noise
Sy(f) = 1/(2QL)2 Sa(f)
– Since Sy(f) = (f2/fo2)S(f) We Obtain
Leeson’s Equation
S(f) = (fo/(2QLf))2+1)(FkT/Pin)(1+ ff/f)Gain = GaNoise Figure = FFlicker Knee = ff
Noise Density =
FkT
Resonator
Amp
Oscillation Conditions
|GaL| = Loop Gain > 1
Around Loop = 0
Pin
Near Resonance R = -2QL·y
Converted Noise + Original Amp Noise
Loss = LLoaded Q = QL
Synthesizer Tutorial V. S. Reinhardt Page 22Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Oscillator Noise Spectrum
• Oscillator Noise Spectrum– S(f) = K3/f3 + K2/f2 + K1/f + K0
– Some Components May Mask Others
• Converted Noise– K3/f3 and K2/f2
– Varies with (fo/(2QL)2 and FkT/Pin
• Amp Noise– K1/f and Ko
– Only Function of FkT/Pin
S(f) = (fo/(2QLf))2+1)(FkT/Pin)(1+ ff/f)
Oscillator Noise Spectrum
Leeson’s Equation
S(f)
f
K3/f3
K2/f2
K1/f K0
QL
Converted Noise
Amp Noise
Synthesizer Tutorial V. S. Reinhardt Page 23Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Multiplied Oscillator vs Higher Oscillator Frequency
• Multiplied Oscillator– Whole Curve xN2
– Higher Near-in Noise – Higher Far-out Noise
• Oscillator foNfo
– Only Converted Noise xN2 (Same QL)
– Higher Near-in Noise – Same Far-out Noise (Same
FkT/Pin)
• This is Why Indirect Synthesis is Attractive– For Lower VCO QL than Ref QL
Bump in Curve
Oscillator at fo vs Nfo (Same QL)
S(f)
N2
S(f) = (Nfo/(2QLf))2+1)(FkT/Pin)(1+ ff/f)
fo Nfo
vs
S(f)
fN2
S(f) = N2(fo/(2QLf))2+1)(FkT/Pin)(1+ ff/f)
Multiplied Oscillator
xNfo
Nfo
N2
Synthesizer Tutorial V. S. Reinhardt Page 24Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Classification of Loops
• Loop Order (1st, 2nd, etc.)
• Phase vs Frequency Lock– PLL Lower Near in Phase Noise
• PLL: Loop Noise Converted to White Phase Noise• FLL: Loop Noise Converted to White Frequency Noise
– FLL Settles Faster
• Implementation– Analog Loops
• Analog Phase Discriminator• Digital Phase Discriminator
– Digital Loop (Filter)
• Phase/Frequency Error Quantization – Contininuous (or Near Continuous)– Bang-Bang (Sign of Error)
Synthesizer Tutorial V. S. Reinhardt Page 25Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
1st & 2nd Order PLLs
• DC Open Loop Gain Set by n (= 2fn)
• VCO Drift will Eventually Cause Loop to Unlock
• Doesn’t Completely Suppress Near-in VCO Noise (1/f3)
• Fastest Settling Time for Same n
• Injection Locked Oscillators equivalent to 1st Order PLL
VCOr
1st Order PLL
n = G
s + n
H =n
• DC Open Loop Gain Virtually Infinite
• VCO Drift No Problem
• Completely Suppresses Near-in VCO Noise (1/f3)
• Slower Settling Time for Same n
VCOr
2nd Order PLL
s2+2sn+n2
H =2sn+n
2
=Damping
Factor
1-H = s for s << n 1-H = s2 for s << n
Synthesizer Tutorial V. S. Reinhardt Page 26Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Analog (Loop Filter) PLLs
• Phase Detectors – Mixers - Need Locking Circuit– Phase-Frequency Det. - Self-Locking – Loops with PFDs Also Called
“Digital” Loops
• Divider Loop– Easy Lock– ASIC Implementation with PFD– Mixer & Loop Noise xN
• Multiplier Loop– False Lock & Spur Issues– Mixer & Loop Noise Not Multiplied– Sampling Phase Detector This Type
• Can Also Have Multiple Conversions (Mixers)
fofr ÷Nfo/N
Divider Loop
VCO
Analog FrequencyTranslation
AnalogLoopFilter
Voltage OutputPhase Detector
fr
fo
fofr xNfrxN
Multiplier Loop
Synthesizer Tutorial V. S. Reinhardt Page 27Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Digital (Loop Filter) PLLs
VCODigitalLoopFilter
fo
fIF1
D/A
Counters
AnalogDown-
Conversions
fc from VCO
DigitalFrequency
Translations
Averaging
fIFk
fr1
frk
. .
..
• Can Lock to Many fr’s: fr1 ... frk
– Weighted Averages, Separate Frequency Offsets, Error Correction
• Digital Phase Detection – Mix each frk to Lower fIFk = K(frk-K’fo)
– Counters Measure Zero Crossings tnk of fIFk with Resolution 1/ fc
– Used to Calculate IFk = K(rk-K’vco)– Single Measurement Resolution
= 2fIF /fc Must be < Ref Noise to Avoid Spurs
• Digital Loop Filter & D/A Control VCO– Loop Filter Sampled at Rate fIF – D/A LSB Must be < Ref Noise in Time
1/fIF to Avoid Spurs (Note: Frequency Resolution is Not Set by D/A LSB)
TIF = 1/fIF
Tc = 1/fc
= 2Tc / TIF = 2fIF / fc
IFk = 2n - fIFk tnk )
tnk
Synthesizer Tutorial V. S. Reinhardt Page 28Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Example of Digital PLL
D/A
VCXO10.23 MHz
Event Clock& PLL Processor
Down-Converter
AFS1
13.4 MHzAFS’s
Down-Converter
100
Hz
fr1
AFS2
fr2
fIF1
fIF2
fofo VCXO AFS
180 KHz
76
3.53 KHz Cs2.76 KHz Rb
NN= 3800 CsN= 4858 Rb
~100 Hz
3.17 MHz
4
Downconverter
+
-
Offset
ComputePhase
+
f Offset
-
Integrate
2nd OrderLoop Filter
x 2n
98 nsEvent Clock
To
D/AF
rom
D/C 10.23 MHz
from VCXO
Integratex n
2/s
Event Clock &PLL Processor
(Reinhardt, 1999)
Synthesizer Tutorial V. S. Reinhardt Page 29Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Fast Settling Loop Techniques
• Pretune VCO Voltage– Approximate New Frequency
• Precharge Loop Integrator– Preset for New VCO Frequency
• Adaptive Loop Filter– Dynamically Adjust Bandwidth
• Reclock & Clear Divider– When Frequency Changes, Old
Nozero State is Phase Error that Must be Slewed Out in PLL
– Reclocking and Clearing Eliminates this Phase Slew
• Ping-Pong Switch & Second PLL– Presettle 2nd PLL before Switching
fo
fr
÷N
PingPong
Switch
2ndPLL
Reclock& ClearDivider
Pre-tune
AdaptiveLoopFilter
Pre-Charge
Synthesizer Tutorial V. S. Reinhardt Page 30Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2 2.5
Time - seconds
Clo
ck
Re
ad
ing
- n
s
Without Precharge
With Precharge
Effect of Precharge on Transient Response
• Precharge Pre-loads Integrator at Each New Frequency Command
• Generates More Ideal Stepped Frequency Response
Loop TC = 0.1 s
(Reinhardt, 1999)
Synthesizer Tutorial V. S. Reinhardt Page 31Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Cycle Slipping
• Becomes Problem at Low SNR within the Loop BW
• Phase Detectors are Periodic in Phase
• Finite Probability of Noise Burst Large Enough to Cause Slip to Next Cycle– Mean Time to Cycle Slip Exponential
Function of 1/SNR in Loop BW
• Especially Problem with Sampling Phase Detectors
(Kroupa, 1973)
En
erg
y
Mechanical Model of PLL with Noise
Noise BurstCausesCycleSlip
Average Noise
Synthesizer Tutorial V. S. Reinhardt Page 32Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Post-Tuning Drift
• Post-Tuning Drift is Further Settling of VCO Frequency After Main Exponential – Can Last s to Hours – Can Have Multiple time Constants
• Causes – Thermal Effects in Semiconductors– Surface Charging and Traps in
Semiconductors– Bias Circuits and Regulators
• Problems/Issues– Varactor Tuner Prime Source– GaAs Devices are Especially Prone
to Post-Tuning Drift– Semiconductor Effects are Very Lot
Dependent
VC
O F
req
uu
ency
Response to Voltage Step
Post-Tuning Drift
SingleExponential
Equivalent Circuit of a Diffusion Process
Synthesizer Tutorial V. S. Reinhardt Page 33Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Direct Digital Synthesizers
• DDSs also called Numerically Controlled Oscillators
• Directly Synthesize a Selectable Output Frequency from a Clock Using Digital Techniques
• Types of DDSs
– Pulse Output
– Sine Output
– Fractional Divider
– Fractional Divider Phase Interpolation
– Other
Synthesizer Tutorial V. S. Reinhardt Page 34Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
Pulse Output DDS
• DDS is N-Bit Accumulator – For Each Clock Period 1/fc
Rin + K Rout in N-bit arithmetic
– Can Write as Frac(rin + F) rout
– Fractional Frequency Word F = K/2N
– Fractional Register Value r = R/2N
• Carry (or MSB) Output– On Average fo = F fc
– RMS Jitter (No Output Filter)
• Period Jitter Tc/(12)0.5
• Phase Jitter F/(3)0.5
• Example F=3/8, (To=(8/3)Tc)– r = 0(C), 3/8, 6/8, 1/8(C), 4/8, 7/8,
2/8(C), 5/8, 0(C), …..
– Period Errors (T/To): 1/3, 1/3, -2/3
N-BitRegister
N-BitAdder
Clock
FrequencyWord K A
BRout
A+B“Square”
Wave OutMSBRin
Carry
Pulse Out fo
Accumulator Used as DDS
fc
1 2 3 4 5 6 7 8 9
ClockCycles
Carry
Carry
CarryR
TimingJitter
PulseOut
Tc
Synthesizer Tutorial V. S. Reinhardt Page 35Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.
0
-20
-40
-60
-800 0.2 0.4 0.6 0.8 1.0
Carrier
f = 0.1225 Hz f = 1 Hzo c
Frequency (Hz)
Typical Pulse Output DDSFrequency Spectrum
• Large Spurs Very Close to Carrier
• Nature of Spurs Changes Drastically with fo
• Filtering Doesn’t Necessarily Reduce Phase Jitter (When Nearby Spurs Present)
• In General Closest Spur 2-Nfc
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Sine Output DDS
• Reduces Spurs by Adding Sine Table and DAC– N Determines Frequency Resolution– Argument of Sine Table = W Bits out
of N Bit Accumulator – Sine Table Value = J Bits– DAC M Bits
• Nyquist Theorem: No (In-Band) Spurs if– Sine Table and DAC Perfect
– fo < 0.5 fc (Must LP Filter Output)
• Spur Levels – 6 dBc per bit for W & J– 6-8 dBc per bit for M (Use Effective
Number of Bits not Actual Bits)– Worst Case Determines Spurs
Stepped DDS Output
N-BitAccumulator
fc
K
SineTable
DACFilter
WBits
M-Bits
J-Bits
fo
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Typical Sine Output DDSFrequency Spectrums
5-Bit DAC 11-Bit DAC0
-10
-20
-30
-40
-50
-60
-70
-90
-80
dBc
fo=333.25 KHz fc=1 MHz Span=10 KHz RBW=10 Hz
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High Speed DACsSpur Levels vs Speed
dBc
Output Frequency (MHz)
Spurious/Harmonics
-79
-69
-59
-49
-39
-29
-19
450
295
245
190
333
12525
0.29
STEL-2373,[1]
Raytheon [2]
Plessey(4) SP2002,[3]
Rockwell,[4]
TI / Lincon Labs LDDS,[5]
Sciteq DCP-1A,[7]
Sciteq ADS-43x[7]
Sciteq (5) ADS-63x [7]
Hughes Space[8],[9]
Philips MicrowaveLimeil,Thomson CNI[10]
TRW DDS/HDAC-1,[11]
DAC Triquent SC-0806-C,(1)[21]
(Essenwanger & Reinhardt, 1998)
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Sine Table CompressionAlgorithms
CompressionAlgorithm
ROMReq’ed
CompressionRatio
LogicCircuits
Algorithm Error (dBc)
None 214x12 1:1 (none) -97.23
Cordic (none) N/A 14 pipelined stages18 Bits Wide
-84.25
Nicholas 128:1 adder/subtract -88.9428x9 28x3
RaytheonTaylorSeries
67:1multiplier
multiplexer,adder
13-bits±1 LSB
25x7
27x14 27x11
Modified Sunderland
28x9 59:1 adder -86.9128x4
UnmodifiedSunderland
51:1 adder28x11 28x4
12-bits±2 LSB
ConventionalTaylor Series 64:1 2 adders
multiplier -97.0427x14 27x9 25x3
(*Modified from Essenwanger & Reinhardt, 1998)
IIR Filter*(Presti, et. Al.) (none) N/A
3 pipelined stagesRequires 1 calc
of Sin & Cos per FreqNo Limit
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Fractional Divider or Pulse Swallowing DDS
• Dual Modulus Prescaler– Normally ÷ n– Output Clocks Accumulator– On Accumulator Carry ÷ (n+1)
Next Cycle
• N-Bit AccumulatorR + K R
– Carry on Overflow
• Output on Prescaler– On Average fo = fc/(n+F)– RMS Jitter (No Output Filter)
• Period Jitter Tc/(12)0.5
• Phase Jitter /(n+F)(3)0.5)
N-BitAccumulator
fc K
DualModulusPrescaler
÷n/n+1
fo
Carry÷n/n+1Control
ClockCycles
Carry
Carry
R
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Phase Interpolation Fractional Divider (in PLL)
• Fractional Dividers Utilized Most Often in PLLs
• Can Reduce Phase Jitter by Utilizing R Value– At Carry rTc = Period Error– Utilize DAC & Linear Phase
Detector to Correct for Error Represented by R
• Spur Levels Limited by– Linearity of Phase Detector– DAC Resolution
• Without Interpolation Can Reduce Spurs if 2-Nfc >>Loop Bandwidth
N-BitAccumulator
K
Divide by n/n+1
n/n+1Control
CarryOutput
LinearPhase
Detector
fr
DACR
LoopAmp
VCO
fo
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r-Space Spectrum
1 3 5 7
Harmonics
r-Space Frequency
Spur Generation in DDSs
Look-UpTablev(r)
•Quantized Sine Wave (Sine DDS)
•Square Wave (Pulse DDS)
•v(r) Periodic in r (Period=1)
•Discrete r-Space Harmonics
AccumulatorSamples v(r)
at rn=fotn
•v(fot) Translates mth Harmonic to mfo
•Sampling at tn Causes Aliasing at f=mfo - m’fc
Stepped Output
Hold Function
•Stepping Adds Hold-Function Filter
•Spectrum of Hold Function Sinc2(f/fc)
Output Spectrum
2fcfc0
t-Space SampledSpectrum
2fcfo
13
57
1
75
3
0
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DDS Spur Algebra
• Time Domain Properties of rn = Frac(nF) – Produces Periodic Sequence– In Irreducible form F can be Written as a/b (a and b Relatively Prime)– Time Domain Sequence Permutation of 0, 1/b, 2/b, …. (b-1)/b
– So Period of Sequence bTc and Number of Unique Values b
• Frequency Domain Properties – Since Period bTc Sequence has Harmonic Exdpansion
kfc/b = 0, fc/b, 2 fc /b, …. (b-1) fc /b, ....
kfc/b = mfo - m’fc = [m(a/b) - m’]fc
– Thus
• There are b Spurs from 0 to fc
• The Spur Spacing is fc/b
• There is a Large (Principal) Spur at fc-fo that is an Alias of the (Negative) Fundamental Frequency
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Converts Spurs to Broadband Spectrum
fo
S(f) JittersOutput at fo
by Jitters spur from mth Harmonic of
v(r) by m
fspur f
Spur Height Reduced Because of Larger
Jitter
Heuristic Explanation
v(r)v(r + p)
FractionalFrequency F
N-BitAccumulator
r
RandomNumber
Generator
r + p
p
Destroying Coherence With Register Jitter
• Spurs Occur Because Uniformly Stepped Sequences Periodic – Introducing Jitter
Destroys Periodicity– Jitter More Efficient
with Spurs from High Harmonics of v(r) Expansion
• Converts Spur Energy to Broadband Phase Noise
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Wheatley Jitter Injection
• Used with Pulse Output DDS
• Destroys Spurs but Produces High Degree of Broadband Noise
0
-20
-40
-60
-800 0.2 0.4 0.6 0.8 1.0
Carrier
f = 0.1225 Hz f = 1 Hzo c
Frequency (Hz)
0
-20
-40
-60
-800 0.2 0.4 0.6 0.8 1.0
Carrier
f = 0.1225 Hz f = 1 Hzo c
Without Jitter Injection With Jitter Injection
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Randomized DAC DDS Experimental Results
• Used with Sine Output DDS
• Less Efficient at Reducing Spurs but with Lower Broadband Noise
5-Bit DAC No Jitter 5-Bit DAC With Jitter 11-Bit DAC No Jitter0
-10-20-30-40-50-60-70
-90-80
dBcfo=333.25 KHz fc=1 MHz Span=10 KHz RBW=10 Hz
0 -10-20-30-40-50-60-70
-90-80
dBc(Reinhardt,1993)
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Frequency and Time SynthesisFinal Summary
• The Basic Concepts Basic Outlined Here are Provide a Framework for Both the Design & Specification of Frequency and Time Synthesizers
• The 3 Types of Approaches Outlined Here Are– Analog Synthesis– Indirect Synthesis– Direct Digital Synthesis
• The Above Architectures Used in Combination are Often the Best Design Approach
• A List of References Follows