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Computer Architecture & Organization

Instruction set, number of bits used for data representation,

I/O mechanisms, addressing techniques, etc.

e.g. Is there a multiply instruction?

Control signals, interfaces, memory technology, etc.

e.g. Is there a hardware multiply unit or is it done by

repeated addition?

hmmm

chicken/egg

problem ?

Architecture attributes visible to the programmer

Organization how features are implemented

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 2

What Should I already know re

Computer Arch & Org ?

computer

keyboard

mousedisplay

disk / optical

speakers

other ?

.

.

.

connected devices

Peripherals

printer

communication

links

networktelephone

cable

wireless

other ?

.

.

.

Black Box !

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 3

Function & Structure

SYSC 2001 will lookinside the black box (ITBB)!

peripherals and commn links are outside black box

Will construct various models of ITBB components:

Function the operation of individual components as

parts of the structure

Structure how components relate to each other

ITBB

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 4

Function

ALL computer functions are:

Data PROCESSING

Data STORAGE

Data MOVEMENT

CONTROL

NOTHING ELSE!

Data = Information

Coordinates How

Information is Used

IMPORTANT

SLIDE !

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 5

Functional view of Black Box

Operating Environmentsource/sink for information

MOVEMENT

CONTROL

PROCESSINGSTORAGE

connectionsto peripherals

and commn

links

ITBB

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 6

Operations (1) Data movement

e.g. copy a file

between disks

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 7

Operations (2) Storage

e.g. load a text

file for editing

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 8

Operation (3) Processing from/to storage

e.g. compute an

intermediate

result from some

operands & save

for later use

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 9

Operation (4)

Processing from storage to I/O

e.g. compute and

display a result

from someoperands

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 10

Structure - Top Level ITBB

Computer

Main

Memory

Input

Output

Systems

Interconnection

Peripherals

Communication

lines

Central

ProcessingUnit

Computer

What about

Function?

More

Black

Boxes

ITBB!

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 11

Structure - The CPU

Computer Arithmetic

and

Logic Unit

ControlUnit

Internal CPU

Interconnection

Registers

CPU

I/O

Memory

System

Bus

CPU

What about

Function?

Drilling

DownI(ITBB)!

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 12

Structure - The Control Unit

CPU

ControlMemory

Control Unit

Registers and

Decoders

Sequencing

Logic

Control

Unit

ALU

Registers

InternalBus

Control Unit

What about

Function?

Too deep for

SYSC 2001

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 13

Brief History of Computer Evolution

Two phases:

1. before VLSI 1945 1978

ENIAC

IAS

IBM

PDP-8

1. VLSI 1978 present day

microprocessors !

see text discussion

VLSI = Very Large

Scale Integration

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 14

Growth in CPU Transistor Count

Moores Law

Pentium Evolution

PowerPC Evolution

Cell 234 M

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 15

Speeding Up the Processor

Pipelining

On board cache

On board L1 & L2 cache

Branch prediction

Data flow analysis

Speculative execution

chicken / egg

again !

well seesome of

these as the

course

progresses

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 16

But Performance Mismatch!

Processor speed increased

Memory capacity increased

Memory speed lags behind (and increasing slower than)

processor speed

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 17

DRAM and Processor Characteristics

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2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 18

Some Solutions

Increase number of bits retrieved at one time

Make DRAM wider rather than deeper

Change DRAM interface

Cache

Reduce frequency of memory access

More complex cache, and cache on chip

Increase interconnection bandwidth

High speed buses

Hierarchy of buses