System Integration Module MTT48 5 - 1 Motoola SYSTEM INTEGRATION MODULE (SIM)

System Integration Module MTT48 5 - 1Motoola

SYSTEM INTEGRATION

MODULE(SIM)


Module Objectives

Understand Reset handling performed by SIM

Understand Interrupt handling performed by SIM

Configure control registers for your system

Module exercise:

As part of reset servicing, determine which reset occurred and

call an appropriate reset recovery routine.


68HC08CPU

SystemIntegration

Module(SIM)

ClockGeneration

Module(CGM)

TimerInterfaceModule(TIM)

DirectMemoryAccessModule(DMA)

SerialCommunications

Interface(SCI)

Internal Bus (IBUS)

SerialPeripheralInterface

(SPI)

RandomAccess

Memory(RAM)

ElectronicallyProgrammable

ROM

LVI

COP

Monitor ROM

IRQ

BREAK

RESET

System Integration Module

• Derives Bus clocks from CGM• Bus clock generation and control for CPU and peripherals

– Stop/wait/reset/break entry and recovery– Internal clock control

• Master reset control, including power-on reset (POR) and COP timeout

• Interrupt control:– Acknowledge timing– Arbitration control timing – Vector address generation

• CPU enable/disable timing

• Modular architecture expandable to 128 interrupt sources


SIM Block Diagram

CLOCKCONTROL CLOCK GENERATORS

POR CONTROL

RESET PIN CONTROL

SIM RESET STATUS REGISTER

INTERRUPT CONTROLAND PRIORITY DECODE

MODULE STOP

MODULE WAIT

CPU STOP (FROM CPU)CPU WAIT (FROM CPU)

SIMOSCEN (TO CGM)

CGMOUT (FROM CGM)

INTERNAL CLOCKS

MASTERRESET

CONTROL

RESETPIN LOGIC

LVI (FROM LVI MODULE)

ILLEGAL OPCODE (FROM CPU)ILLEGAL ADDRESS (FROM ADDRESSMAP DECODERS)

COP (FROM COP MODULE)

INTERRUPT SOURCES

CPU INTERFACE

RESET

STOP/WAIT CONTROL

SIMCOUNTER COP CLOCK

CGMXCLK (FROM CGM)

2


System Integration Module- Bus Clocks -

Takes output of Clock Generation Module

• Distributes clocks to submodules

Controls system clocks in low power modes

• WAIT– Stops clock to CPU only

• STOP– Stops all bus clocks– Asserts SIMOSCEN

• Shuts down CGM oscillator circuit


Reset Control

MCU Reset Sources:

• Power-on Reset Module (POR)

• External Reset Pin (RST)

• Illegal Opcode Reset

• Illegal Address Reset– Caused by an opcode fetch from an illegal address

• Low-Voltage Inhibit Module (LVI)

• Computer Operating Properly Module (COP)

WRITE:

READ: POR PIN COP ILOP ILAD 0 LVI 0

RESET: 1 0 0 0 0 0 0 0

Reset Source Bit cleared by Reading SRSR or Power On Reset

SRSR

SIM Reset Status Register• The SRSR records the cause of the last reset sequence. (One and only one bit will be set!)


•Voltage on VDD changes from logic zero to logic one

•Internal reset signal is asserted–Issues–All internal clocks to CPU and Modules are held inactive for 4096 CGMXCLK clock cycles–Allows for stabilization of oscillator–RST pin is driven low during stabilization of oscillator

•Power On Reset(POR) bit in SIM reset status register is set and all other bits in register are

cleared.

Power On Reset

PORRST

OSC1

CGMXCLK

CGMOUT

RST

IAB

4096CYCLES

32CYCLES

32CYCLES

$FFFE $FFFF


Power-On Reset Flow

PORPulse

Vdd

Oscillatorbegins operating

Internal clocks held Lowfor 4096 CGMXCLK

clock cycles

RESET pin is driven low Reset pin is

released.


•Internal reset signal can be generated by pulling RST* pin low

•PIN bit of the SIM reset Status Register (SRSR) is set if:

–RST* held low for a minimum of 67 CGMXCLK cycles

–PIN Bit Set Timing:

POR/LVI Resets 4163 = (4096 +64 + 3) Cycles

All Other Resets 67 = (64+3) Cycles

External Pin Reset

RST

IAB PC VECT H VECT L

CGMOUT


Internal Resets

Illegal Opcode Reset

• Occurs when CPU decodes instruction not in opcode map

Illegal Address Reset

• Occurs when CPU tries to fetch an instruction from an address not in defined

memory map

Low Voltage Inhibit Reset

• LVI indicates VDD dropped below preset limit

• Reset remains for 4095 CGMXCLK clock cycles after VDD is restored

– Allows clock to stabilize

Computer Operating Properly Reset

• COP indicates it’s timer has expired– Timer must be periodically reset

• System protection, prevents runaway processors

ILLEGAL ADDRESS RSTILLEGAL OPCODE RST

COPRSTLVI

POR

INTERNAL RESET


Internal Reset Timing

IRST

RST RST PULLED LOW BY MCU

IAB

32 CYCLES 32 CYCLES

VECTOR HIGH

CGMXCLK


Internal Reset Flow

Internal Reset Signalis issued

RST is actively driven low for 16 bus cycles

Internal reset signal is asserted for 16*

additional bus clocks

RST pin is tested

RST pin low indicates that an

external reset has occurred

RST pin high indicates that an

internal reset occurredand the appropriate

internal reset bit is set

*This is longer for LVI Reset


Interrupts

68HC08 can process up to 128 separate resets/interrupts

On-chip peripheral modules generate maskable interrupts

• Recognized only if interrupt mask bit clear

• Indicated by an interrupt status flag, also

All interrupts are prioritized

SIM module

• Receives all interrupts

• Performs arbitration

• Passes highest priority interrupt on to CPU


68HC708XL36 InterruptSources and Priorities

Local GlobalFunction Mask Mask Priority Vector Address

Resets (6/1) No None 1 $FFFE - $FFFF

Software No None 2 $FFFC - $FFFDInterrupt

IRQ1 Yes I-bit 3 $FFFA - $FFFB

PLL Interrupt Yes I-bit 4 $FFF8 - $FFF9

DMA Yes I-bit 5 $FFF6 - $FFF7Interrupts (3/1)

Timer Yes I-bit 6 $FFEC - $FFF5Interrupts (5/5)

SPI Interrupts (2/2) Yes I-bit 7 $FFE8 - $FFEB

SCI Yes I-bit 8 $FFE6 - $FFE7Interrupts Yes I-bit 9 $FFE4 - $FFE5(8/3) Yes I-bit 10 $FFE2 - $FFE3

IRQ2/Keyboard Yes I-bit 11 $FFE0 - $FFE1


SIM Exercise

Write a code sequence that determines what the last reset was and then calls an appropriate subroutine that

implements a reset recovery scheme.

The details of the called routines is not important.

Given:* Reset service/recovery caller

ORG $FE01SRS RMB 1

JMPTBL FDB PONRCVY FDB PINRCVY FDB COPRCVY FDB ILOPRCVY FDB ILADRCVY

FDB LVIRCVY


Additional Information- Low Power Modes -

WAIT Mode Control

• SIM stops CPU system clock

• Peripheral clocks continue to run

• Clears I-bit in CCR

• Exit conditions– Non-masked external interrupt– Any non-masked internal interrupt

• Module must also be active– Any Reset


Additional Information- Low Power Modes -

STOP Mode Control

• SIM Counter is reset and system clocks are disabled

• SIM disables clock generator outputs (CGMOUT and CGMXCLK)– CPU and Peripherals are stopped

• Clears I-bit in CCR

• Exit conditions– Non-masked external interrupt– External Reset only

• Recovery time is selectable– normal delay 4096 CGMXCLK cycles or– If SSREC = 1 in MOR(masked option register) delay 32 CGMXCLK cycles

* Ideal for applications using canned oscillators not requiring long start-up times


Additional Information- Break Status and Control -

RESET: 0

1. Writing a logic zero clears SBSW

WRITE:

READ: SBSWSBSR RESERVED RESERVED

NOTE1

SIM Break Status Register (SBSR

• SIM Break Stop/Wait (SBSW) status bit

– Useful in applications requiring a return to a wait or stop mode after exiting from a

break interrupt

1 = Stop mode or wait mode was exited by break interrupt

0 = Stop mode or wait mode was not exited by break interrupt


Additional Information- Break Status and Control -

RESET: 0

WRITE:

READ:SBFCR RESERVED BCFE

SIM Break Flag Control Register (SBFCR)

* Enables software to clear status bits by accessing status registers while the MCU is in a

Break state

• SIM Break Clear Flag Enable bit

– To clear status bits during the break state, the BCFE bit must be set

1 = Status bits clearable during break

0 = Status bits not clearable during break


Additional Information- Stabilization Delay -

Mask Option Register (MOR)

• Short Stop Recovery– Selects either a long or short clock stabilization delay is to be used

when exiting STOP

1 = Short stabilization delay (32 CGMXCLK clocks)• For CAN Oscillator - off Board

0 = Long stabilization delay (4096 CGMXCLK clocks)• On-board Oscillator

RESET: UNAFFECTED BY RESET

WRITE: MOR

READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD


Register Summary

RESET: UNAFFECTED BY RESET

WRITE: MOR

READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD

WRITE:

READ: POR PIN COP ILOP ILAD 0 LVI 0

RESET: 1 0 0 0 0 0 0 0

Reset Source Bit cleared by Reading SRSR or Power On Reset

SRSR


SIM Exercise Solution* Reset service/recovery caller

ORG $FE01SRS RMB 1

Reset LDHX #JMPTBL ;Load base address of Jump table LDA SRS ;Read Reset Status Register CMP #$80 ;LVI Reset? BEQ DONE ;If so branch AIX #2 ;Offset = 2 CMP #$40 ;External Reset? BEQ DONE ;If so branch AIX #2 ;Offset = 4 CMP #$20 ;COP Reset? BEQ DONE ;If so branch AIX #2 ;Offset = 6 CMP #$10 ;ILOP Reset? BEQ DONE ;If so branch AIX #2 ;Must be ILAD Reset, Offset = 8DONE JSR ,X • • • •JMPTBL FDB LVIRCVY FDB PINRCVY FDB COPRCVY FDB ILOPRCVY FDB ILADRCVY

Date post:	19-Jan-2016
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System Integration Module MTT48 5 - 1 Motoola SYSTEM INTEGRATION MODULE (SIM)

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