System Level ESD: A New Focus Charvaka Duvvury IEEE...

1 Tutorial DD110: ESD Basics to Advanced Protection Design – Duvvury 2016

System Level ESD: A New Focus

Charvaka Duvvury

IEEE Seminar

July 2017

ESD Issues (35 years)

1978 1983 1988 1993 1998 2000 2008

Basic ESD Control

Static Materials

Advanced Control

Basic RF/HSS Exploratory

System Efficient Design

Physics/ Modeling Tech. Optimization

ESD Control

Device/ Design

On-Chip Design

System Level Focus

2016

Advanced

PCB Design

Polymers

Hig

h S

peed

Desig

ns

3

3 Tutorial DD110: ESD Basics to Advanced Protection Design – Duvvury 2016 3

ESD for Component System

FAB Areas Wafer

Handling

IC Assembly

& Test

End Customer

Operations

PCB Assembly &

Test

•Ionizers•Static Handling

•Ionizers•Grounding

• System level ESD protection

•Shielding•Ground Pre-runs

ESD Protected Areas ESD Exposed Areas

Antenna Diode Protection

IC On-chip Protection

System Protection On-chip/off-chip

Case & Grounding Protection

IC components and End Systems need separate but equally important with effective protection

strategies

Industry Council 2014


Electrostatic Discharge (ESD)

IC level ESD Q-Test Standards Systems level ESD Test Standards

• Human Body Model (HBM): ANSI ESDA/JEDEC JS-001

• Charged device model (CDM): ANSI ESDA/JEDEC JS-002

• IEC 61000-4-2

• ISO 10605 (automotive)

• Cable discharge events (CDE) (company specific test specs)



HBM Versus IEC

4kV-HBM(schematic)

4kV-GUN

4kV-HBM(schematic)

4kV-GUN

4kV-HBM(schematic)

4kV-GUN

Time t [ns]

Cu

rre

nt I

[A]

Discharge current thru a 2-Ohm load

C = 100 pF, R = 1500 Ohm

• System level ESD gun test has to be

performed under powered conditions

• For powered systems there are two

failure mechanisms

- Destructive fail

- Functional/Operational fail

• Improving the component ESD levels

will not solve this issue

• There is no clear correlation of system

level performance to the HBM

robustness

4 kV HBM is not the same as 4 kV IEC!


Note the extreme initial

I(peak) due to the direct

capacitive coupling with the

gun tip


Automotive Design ESD Stress Requirements

6


ESD Failure Modes

CDM HBM IEC

Component Damage System Damage

Much more focus is needed to prevent ESD damage to

electronic systems H. Gossner


Year

Tech

no

logy

no

de

2 µm

250 nm

1 µm

65 nm

32/28 nm

22/14 nm

1992 1998 2004 2008 20121988

LDD diffusion

ESD↓: Increased junction power

dissipation

Silicided diffusionESD ↓ : Non-uniform bipolar currents

<200 nm gate lengthsESD ↓ : Channel heating

Strain engineeringESD ↑: Reduced junction power

dissipation

Ultrathin GOX and highK dielectricsESD ↓ : Low GOX breakdown

FINFETESD ↓ : Local selfheating of fins

Device Scaling and Technology Effects


Impact on ESD @10-20 GB/Sec

1.2 1.8 3.3 5 7 10

65

90

130nm

Core VDD

IC Operating

Area

IC Reliability

Area

15V

V

ESD Design Window VFHBM

3kV

2kV

45

4

1kV

•Closing of the ESD Design Window to <1kV HBM

•Severe impact also on CDM

JMESD

BVOXESD

1.0

32 22

[140]


Series Resistor Influence on CDM

0

2

4

6

8

10

0.1 10 1000

Series Resistor (Ohms)

CD

M P

ass

Cur

rent

(A

)

65nm-15GBs

45nm-15GBs

45nm-25GBs

Data Rates Vs. Max CDM Current for 45nm

Achievable CDM current levels are limited between 2-5 Amps depending on the circuit

speed requirement

VSS

VDD

I/O Pad

ReceiverDriver

D4

D3

R1

FET

CDM Clamp

Trigger

Circuit

VSS

VDD

I/O Pad

ReceiverDriver

D4

D3

R1

FET

CDM Clamp

Trigger

Circuit


IMPACT ON HIGH SPEED DESIGNS D

ata

Rat

es

(Gb

/s)

0 100 200 300 400 5000

20

40

60

80

Loading Capacitance (fF)

>2kV

<1kV

>1kV

Expected HBM Performance

• Data Rates are influenced by the ESD loading capacitance

• For >20 Gb/S, 2kV HBM and 500V CDM are not possible to achieve

• Capacitive loading of ESD protection for high speed serial (HSS) link design is limited

to ~ 100 fF.

Dat

a R

ate

s (G

b/s

)

0 100 200 300 400 5000

20

40

60

80

Loading Capacitance (fF)

>500V

<250V

<350V

Expected CDM Performance


Package and IO Speed Impact on CDM

Data Rates, Tech. Node and Package Size all will have impact on achievable CDM

0

100

200

300

400

500

600

100 500 1000 2000 3000

CD

M (

V)

Number of BGA/LGA Pins

15GB-45nm

25GB-45nm

15GB-22nm

25GB-22nm

Old CDM Levels

New CDM Levels

[140]

13 Tutorial DD110: ESD Basics to Advanced Protection Design – Duvvury 2016 13 Industry Council 2015

Technology Impact on CDM: 22nm with 125V Spec

10 100 1000 10000

25 2500 250

DIP QFP TQFP BGA

750V

NUMBER OF PINS

PACKAGE AREA MM 2

500V 400V 300V 250V

1

400V 300V 250V

250V 400V 300V

High Speed Designs:

Stress Voltage @2A

BGA LGA BGA

<125 <150V RF Designs:

Stress Voltage @1A 200V 250V

500V

Advanced Digital Designs:

Stress Voltage @4A 500V

Digital Designs:


200V <150V

200V <150V <125V

10 100 1000 10000

25 2500 250

DIP QFP TQFP BGA

750V

NUMBER OF PINS

PACKAGE AREA MM 2

500V 400V 300V 250V

1

400V 300V 250V

250V 400V 300V

High Speed : Stress Voltage @2A

BGA LGA BGA

<125 <150V

RF Designs:

Stress Voltage @1A 200V 250V

500V

Advanced Digital :


Digital Designs: Stress Voltage @6A 200V

200V <150V

200V <150V <125V

Pa

ck

ag

e

De

sig

n

HS

S

RF

D

igit

al IO

Many high speed designs will just pass 125V CDM


System Level ESD

– Charged Human

– Charged Human with a Metallic Tool

– Charged cables (Charger, Headset, USB, HDMI,..)

– Charged Products themselves

What are some sources of System ESD Events?

How is Event Transmitted to System

– Direct contact to a system I/O

– Direct contact to a system’s case

– Arc through a vent hole or seam to a circuit board

– Pickup of EM radiation from arc by system


What is a System?

IC Component

IC Component IC Component

System with External IC

Pins

System with Internal IC

Pins

A system consists of embedded ICs and other electronic components to form a

consumer/automotive/military/medical product that can be exposed to various random uncontrolled

severe ESD events with unspecified waveforms

Handling under safe

ESD control methods

only A System can be exposed to all sorts of uncontrolled ESD

events

1-1kV 1-35kV

C. Duvvury


What is a System Event?

C. Duvvury

An ESD event enters a system: • It can be coupled directly into a port on any signal, power or ground line,

induced into circuit paths from currents flowing on a chassis surface, or

radiated into a product.

• ESD currents flowing on printed circuit track, through ground or power plane

will cause E and H fields to be developed and unwanted voltages to be

generated.

• The likely discharge path (lower impedance, higher capacity) at the system

level creates a more severe strike pulse than is likely to be generated by

(higher impedance, lower capacity) ESD protected tools and skilled operators

in a controlled environment.


System level ESD

•Electrostatic charges accumulate on a human body primarily through tribo-charging.

•A charged human discharging through a metallic tool such as a screw-driver into or close to an electronic system is considered a system level ESD event.

•This model is often called a Human Metal Model (HMM) as opposed to the Human Body Model (HBM) commonly used in the component (IC) level ESD testing.

C. Duvvury


ESD directly into the system

ESD close to the system

ESD On Systems

ESD

Electric and magnetic

fields produced by ESD

couple to the system in

multiple ways, causing

failures.

ESD field coupling through external

vent hole

The IEC 61000-4-2 Test

Method is used to

represent a changed

human holding a metal

object to discharge


Overvoltage spikes on supplies

Charging / discharging of large value capacitors directly into

system pins

Long charged cables connecting directly into system pins

A system being supplied with energy before its connection to

ground (connection of a board into a system plug contacts supply

before ground)

System Related Failures

C. Duvvury


ESD Discharge to a System

Soft Fails Hard Fails Industry Council 2015


More soft failures •The operating state being altered, such as a television receiver

suddenly switching to a different channel etc.

lights flashing unexpectedly;

•An automobile braking system operating without input from the

driver;

•Incorrect or improper data being displayed on a monitor or

screen

•An input device, such as a computer keyboard or device keypad,

locking up and not responding to key strokes from the user C. Duvvury

Source Mike Hopkins


Categories of soft fails

•Data incorrectly written to or read from memory

•A hard disk drive that is detected and automatically corrected by

the equipment’s error correction software

•Data incorrectly written to or read from memory or a hard disk

drive that is not corrected by the equipment’s error correction

software;

•Equipment suddenly turning off without any overt power down

command issued; C. Duvvury


System level ESD vs. Component level ESD

Parameter System level ESD – IEC Contact Component level ESD HBM

Event example Charged human discharging through a metallic

tool to a system

Charged human discharging through the skin to

a component (IC)

Model IEC system level ESD Human Body Model (HBM)

Environment End customer’s normal operation Factory assembly

Standard example

Test

IEC 61000-4-2 (Powered)

ISO 10605 (Unpowered)

JS-001 (Unpowered only)

R-C network

Peak current 3.75 A / kV 0.7 A / kV

Typical requirement 8 KV 2 KV

Rise time 0.7 ~ 1 ns 2 ~ 10 ns

Pulse width ~50 ns 150 ns

Failures Soft and Hard Hard

Application PC, Cell phone, Modem, etc… IC

Tester examples KeyTek Minizap, Noiseken ESS2000 KeyTek Zapmaster MK4, Thermo

330 Ω

150 pF To EUT

1500 Ω

100 pF To DUT

The two tests are distinctly different and serve different purposes

Courtesy: Jae

Park, TI


Component and System Level ESD Do Not Correlate

4kV-HBM(schematic)

4kV-GUN

4kV-HBM(schematic)

4kV-GUN

4kV-HBM(schematic)

4kV-GUN

Time t [ns]

Cu

rre

nt I

[A]

Discharge current thru a 2-Ohm load

C = 100 pF, R = 1500 Ohm

Even 4 kV HBM is not same as 4 KV IEC!

There is no correlation between HBM and IEC

The requirements for IEC test are often 8kV

Duvvury 2015


Air discharge: To all insulating parts of the case To keys To touch screen

Contact discharge To metal parts of the case To Ground shield of connectors NOT to connector pins ( e.g. D+/D- of USB)

Operational conditions: As typically used Pluggable devices connected to power line Mobiles w/ and w/o charger Headsets attached

Test Conditions IEC 61000-4-2

Courtesy of Mike Hopkins



IC

PCB

Protection

diodes for

system level

ESD

IC pins with

normal ESD

PCB internal

connections

IC pins

with

normal

ESD

PCB

pins

IC

PCB

Protection

diodes for

system level

ESD

IC pins with

normal ESD

PCB internal

connections

IC pins

with

normal

ESD

PCB

pinsIC

PCB

IC pins with

normal ESD

PCB internal

connections

System

level

robust

IC pins

PCB

pinsIC

PCB

IC pins with

normal ESD

PCB internal

connections

System

level

robust

IC pins

PCB

pins

IEC Protection Approaches

Common strategy with PCB

protection Inherently robust IC pins

(on-chip protection far beyond 2 kV

HBM)

On-chip IEC protection is not ideal; increases pad capacitance and

degrades high speed performance


bus

conn

ecto

r

Printed

Circuit

BoardIC

IC

IC

IC

bus

conn

ecto

r

Printed

Circuit

BoardIC

IC

IC

IC


Differentiation of Internal Vs. External Pins Circuit Board System

Internal External Stress Access to External Pins

• As identified here all the external pins are stressed with the IEC pulses

• What is the interaction to the corresponding interface pins?


What are the problems for an On-Chip System Protection Strategy?

• Misconception

- Is necessarily a cheaper solution than off-chip design

- A single IC can cover protection for the whole system

• Added IC level costs

- ~30% increase in area

- Need for a larger package

- Increased design cycle time

• Uncertainty

- No information on other components on the board

- How the test would be done

- To design for surviving the worst-case IEC stress

- Additional system protection measures may be needed

Industry Wide Challenge


IO Area Impact from On-Chip System ESD

Designs

• On-Chip solutions for System Level ESD occupy large areas and not guaranteed

to work effectively

• Off-chip solutions using SEED provide consistent and effective strategies and

avoid IO chip functional problems from radiated fields

Gossner/Duvvury


Impact from On-Chip System ESD Design

ESD and EMI spread into the system creating

secondary issues

ESD and EMI are guided out of the system

keeping noise isolated

On-Chip Solution Off-Chip Strategy



System Efficient ESD Design

The design of overall system protection requires

understanding of the “Residual Pulse” going into the

IC pin with external interface


ESD Testing Models – System Level ESD

International Electro-technical Commission (IEC)

0

5

10

15

20

25

30

35

0 20 40 60 80 100

Time (ns)

IIEC

(A)

HBM-likeCDM-like

150 pF

+ -

VIEC 330 W

DUT

Equivalent Circuit

8 kV

Tutorial DD110: ESD Basics to Advanced Protection Design – Duvvury 2016


IEC pulse source model ESD pulse model with target peak currents

Example [x] L=4 µH

C=20

pF

R=

120

Ohm

R=

330

Ohm

C=

110 pF

R=1 MOhm

C=10 pF

V

step

Vcharge

R=

36 Ohm Zap

GND

Switch

R=

36 Ohm

*Switch:

R1=1 Gohm

V1=0V

R2 =1 Ohm

V2=1.0 V

*Vstep:

Vlow=0V

Vhigh=1 V

Delay= 1 ns

Rise= 100 ps

1 kV

H. Gossner ESDA Tutorial


System-Efficient ESD Design (SEED) Concept

External

TVS

IC IEC

clamp

PCB With Components

External Component Response

Characterization linked to the IC Pin’s

Transient Characteristics

•Utilizes the existing component level ESD as a starting point for design

•For an efficient system protection design, the IC pin breakdown characteristics play a critical role

•Effective IEC protection design can be achieved for any IC pin that interfaces with the external world


Evaluation Board (Reference Platform)

Form Factor representative of a Smart Phone Application

Board C. Duvvury


SPICE Methodology Overview

TLP model

IC ESD cells

TVS

IC Failing Limits

It2 (slow transient)

Ip (fast transient)

[S] parameters

or Electrical Model

for “Passives”


-5 0 5 10 15-10 20

-5

0

5

-10

10

Voltage [V]

Cur

rent

[A]

Model Description: TVS Model

Model fit TLP data

Positive & Negative

Quadrant

Snap-back region

excluded


IC ESD protection Cells Model

38

2 4 6 8 100 12

1

2

3

4

0

5

V [V]

I [A]

-6 -4 -2 0 2 4 6 8 10 12-8 14

-6

-4

-2

0

2

4

6

-8

8

V [V]

I [ A

]

usb2_otg_dm

ID

Model fit TLP data

Positive & Negative

Quadrant

Snap-back region

excluded


1E7 1E8 1E91E6 3E9

-80

0

80

160

240

-160

320

Freq , Hz

Ohm

s

mag(Zeq)

real(Zeq)

imag(Zeq)

1E6

1E7

1E8

1E9

1E5

3E9

2.00

4.00

6.00

8.00

0.000

10.0

Freq,Hz

Ohm

s

mag(Zc2)

mag(Zc1)

mag(Zc3)

Model Description : CFB & Capacitors

CFB

C3(4.7μF)

C2(1μF)

C1(0.1μF)

120Ω/100MHz

[S] Parameters Files



mag(Znm)

mag(Zom)

mag(Zlm)

10.0k 100.k 1.00M 10.0M 100.M 1.00G1.00k 10.0G

1.00

10.0

100.

100.m

600.

freq, Hz

Zom

, Zn

m &

Zlm

[O

hm] mag(Znm)

mag(Zom)

mag(Zlm)

Model Description : CMF

~2 Ω

~10 nH

.

Beyond a frequency, CMF start to act as a transformer : load seen at the

primary is defined by load of the secondary



Model Description : CMF

CMF is almost transparent for differential signals

Attenuation of the IEC pulse trough the increase of Insertion Impedance


Simulated Current Waveform at IC pins

Slide 42

Transient simulation

+8kV at D- Connector pin

Additive contribution of each elements

Suppression of the First IEC Peak by the PCB 42


• Troubleshooting to Determine the Cause of Failures

- Hard Failures

- Soft Failures

• New Technologies for Determining Root Cause of Failures

- Susceptibility Scanning

- New Software Methods

- System Specific Test Boards

C. Duvvury

Tools


Basic Vs Extended SEED

Basic SEED Conducted discharge leads to damage

Extended SEED Covers also soft fails due to low injected currents and EM radiation


Simulations must include analysis of the PCB trace elements

Needs additional EM scanning tools


Polymer Devices for ESD Applications?

• Polymer voltage suppressors (PVS): At high fields breakdown in the small spaces between the conducting particles creates a low resistance path in the polymer.

• The polymer films are laminated between electrodes and processed into devices using processes similar to printed circuit boards.

• PVS devices are always bidirectional snapback devices. • The polymer films can also be incorporated into connectors to provide built in

protection. • These devices offer very low capacitance, making them very attractive for high

speed signal lines where any extra capacitance will degrade signal integrity.


DSP and Microprocessors Internal Pin Examples with no System level ESD concern

• Serdes: 20 GB/sec at 20nm

• DDR:2.3G at 28nm

External Pin Examples that need high attention

• USB and HDMI - External

• RF Antenna low tolerance to capacitance

Industry Council


USB1

12MB

USB1.1

48MB

USB2

480MB

USB3

5GB

2004 2001 1995 2011

USB Roadmap

5V

3.3-5V

3.3V

1.8V

130nm 90nm

65 to

28nm

28nm

Includes

compatible port for

UBS2


ESD Association Working Groups on SEED

1. Development of enhanced TVS SEED Model

• Project team: MST, NEXPERIA, Intel

• Goal: model transient behavior of TVS diode

• Achievement: successful modelling of low cap snapback TVS device

2. Assessment of SEED modelling and simulation using USB 3 board (WG26)

• Project team: MST, NEXPERIA, Intel

• USB 3 board modified to place TVS and other discrete elements

board available in ww18

• Next steps:

• Functional test of board

• S-parameter extraction

• Selection of discrete elements for test (TVS diodes, resistors, caps)

• Call for WG activities: start of assessment at different labs by end of June


<100MB

1.8GB

2.4GB

>3.4GB

2011 2008 2005 2012

HDMI Projections

28nm 28nm 32nm 65nm

•Composite

•S-Video

5.4GB

2015

28nm

•Display Ports


Automotive Trends

• Next 5 years technology feature in the sub-100nm range.

• The chip area required for system level ESD protection is not able

to shrink

• Increase of logic density and signal bandwidth

• System level robustness may be required for certain pins (GPIO,

ADC inputs) with external PCB-level protection

Industry Council


IC Package Trends • Sytem-in-Package (SiP) needs to carefully match all IC and

product interfaces - includes EMC/ESD compatibility issues

• May not be possible to separate noisy RF interfaces on a board

from other sensitive interfaces

• More complex for Systems on Chip blocks

• EMC/ESD simulations are needed to optimize design

Industry Council


PCB Trends • Board technologies evolve along with new material and joint

technologies.

• Traditional board technologies and novel IC and Systems on Chip

technologies may bring challenges for the system design.

• Board 3D design with stacked components, embedded

components in PCB, System-in-Packages

Industry Council


System Trends

• Technology advances will bring more functions to electronic devices

in all product ranges.

• Advanced sensors, high speed display technologies (3D displays),

>3 GHz data transmission and optoelectronics will most likely add

system complexity.

Industry Council


Conclusions • Component level ESD is not a major issue as long as

minimum safe levels for HBM and CDM are maintained

• For system level ESD on-chip solutions are challenging and are not efficient

• For interface pins external protection is optimum as long as the board designs take into consideration the response of the external TVS and the I/O pin’s transient characteristics

• As technologies advance there will be many challenges for meeting system level ESD requirements



Acknowledgments Industry Council’s Core Members for:

this major thrust on ESD related studies

Harald Gossner

leading the Council as co-chair

Reinhold Gaertner

his analysis of the industry wide data

Pasi Tamminen and Joost Willemen

insight into the future of System Level ESD projections


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