System Level Modeling Using Matlab / Simulink and LTspice · M. Schubert System-Leve Modeling using...

lektronikabor

System Level Modeling Using Matlab / Simulink and LTspice

Prof. Dr. Martin J. W. Schubert Electronics Laboratory

Ostbayerische Technische Hochschule Regensburg

M. Schubert System-Leve Modeling using Matlab/Simulin & LTspice OTH Regensburg

- 2 -

System Level Modeling Using Matlab / Simulink and LTspice

Abstract. This communication introduces in system level behavioral modeling using Matlab / Simulink and LTspice applied to model a DC/DC buck conversion example.

1 Introduction This lesson will teach the use of Matlab / Simulink for graphical schematic entry and simulation on system level. So called model based design can translate graphical Simulink models into code (e.g. VHDL, Verilog, C) for embedded application. Model-based design steps are [wiki]: 1. model a plant, 2. analyze and synthesize a controller for the plant, 3. simulate the plant and controller, 4. integrate all these phases by deploying the controller Application example is a DC/DC buck converter. Switch mode conversion of DC voltages is important for efficient power conversion in the wide range of tiny sensor nodes up to high-voltage lines in the 500 KV range. Furthermore DC/DC conversion is an excellent example for mixed analog/digital system design and control. As resistive devices inevitably cause energy losses by converting electrical energy to heat, power conversion with minimal losses requires energy storage in and recovery from capacitors and inductors. On the other hand, this configuration tends to oscillate, so that control engineering aspects have to be carefully considerd. This document will use linear and time-invariant (LTI) systems, which are typically modeld in Laplace variable s with s=jω=2πf and will then be translated to z domain. In this notation, an inductor L has the impedance sL and a coapcitor C the impedance 1/sC. Documentation about linear feedback loops as LTI systems is offered in [xxx]. The organization of this document is as follows:

Chapter 1 introduction,

Chapter 2 offers some mathematical LTI system modeling of a DC/DC buck converter,

Chapter 3 introduces related Matlab / Simulink modeling and simulation,

Chapter 4 introduces related LTspice modeling and simulation,

Chapter 5 draws relevant conclusion and

Chapter 6 offers some references.


- 3 -

2 Modeling 2.1 Modelbased Design V-Model [1]and Model-Based Design [MDB] often come together. MBD comes with many different definitions, where we will look closer at the Wikipedia definition [MDB] here:

1. modeling a plant, 2. analyzing and sysnthesizing a controller for the plant, 3. simulating the plant and controller, and 4. integrating all these phases by deploying the controller.

In this communication the plant (also termed process) is made of linear devices like resistor (R), inductor (L) and capacitor (C) combined with nolinear devices like diodes and switches. Goal is to develop and linear and time-invariant [LTI] model in Laplace variable s of the plant and verify it with Spice against the model made with devices. For this model in s we will then compute optimized parameters for a PID controller and simulate the control loop with both, Spice and Matlab.


- 4 -

2.2 Schematic Models

(d) Control loop stabillizing lowpass / oscillator

Fig. 2.2: Generation of core voltages for an FPGA: (a) PWM signal filtered by (b) RLC lowpass with (c) real and complex poles, (d) control loop: Process=p(uin), inference = q(iL). A DC/DC buck converter consist basically of a RLC lowpass smoothing a PWM signal as illustrated in Fig. 2.2(a). High efficiency requires to minimize resistive losses by generator output impedance Rg, inductor’s wire resistance Rw and equivalent serial resistor (ESR) RC of the capacitor. For modeling we use driver resistor RD = Rg+Rw. Modeling the process as transfer function PTF(s) allows for usage within a control loop according to Fig. 2.2(d) and optimization of PID control paramteters with Matlab/Simulink.


- 5 -

2.3 Mathematical Modeling

2.3.1 Plant and Inference Time-Continuous Transfer Functions

The RLC circuit in Fig. 2.2(b) consists of resistors, capacitors and inductors. As all these devices are linear (sinusoidal input delivers sinusoidal output with same frequency) and time-invariant (impulse response does not change with time), the circuit can be expressed as LTI (linear and time-invariant) model using Laplace variable s=jω=2πf, with f being frequency. The impedances of a capacitor C and an inductor L are modeled in Laplace domain as

1/CZ sC and LZ sL , respectively. A multiplication with s in Laplace domain

corresponds to a differentiation in time domain. As the RLC circuit in Fig. 2.2(b) contains two different energy storage devices, namely capacitor C and inductor L., it can be modeled as second order transferfunction (TF). It is also referred to as bi-quadratic TF, as it features 2nd order polynomials for both numerator and denominator. In Laplace domain the RLC lowpass in Fig. 2.2(b) can be modeled with transfer functions PTF and QTF. In (2.1) and (2.1) we model the load resistor RL as load conductor GL = 1/RL to avoid problems with infinite RL. PTF(s) is termed process or (by control engineers also) plant transfer function. In Fig. 2.2 it describes the behavior of RLC lowpass’ output voltage p as a function of its input voltage u.

( ) out

in

UPTF s

U

2

1

1 ( ) (1 )C

D L C D D C L L C L

CR s

R G R R R R G C G L s R G LC s

, (2.1.1)

QTF(s) is the inference (slangy quarrel) transfer function. In Fig. 2.2 it describes the spectral behavior of output voltage q as a function output load current IL.

out

L

UQTF

I 2

(1 )(1 / )

1 ( ) (1 )D C D

D L C D D C L L C L

R sCR sL R

R G R R R R G C G L s R G LC s

. (2.1.2)

As linear superposition principle holds for LTI systems, the total output quantity y (also labeled Uout in Fig. 2.2) can be computed as y=p+q. Ansatz

0

( )L

out

in I

UPTF s

U

2

0 1 2

20 1 2

p p p

p p p

a a s a s

b b s b s

and

0

( )in

out

L U

UQTF s

I

20 1 2

20 1 2

q q q

q q q

a a s a s

b b s b s

delivers (2.1.3)

0 1pa 1p Ca C R 2 0pa

0 1p D Lb R G 1 ( )p C D D C L Lb R R R R G C G L 2 (1 )p C Lb R G LC

(2.1.4)

0q Da R 1 ( )q C Da R R C L 2q Ca R LC

0 0q pb b 1 1q pb b 2 2q pb b


- 6 -

2.3.2 Controller Transfer Function

Controller engineers model PID controllers typically as

( )

( )

C sQTF

E s

2I I P I

P D

K K K s K sK K s

s s

(2.2.1)

with KP, KI, KD being proportional, integral and derivative control parameters. Additional Pole ωp1 : In practical applications infinite integrator amplification is often not possible, so the we have an unintentional pole ωp1 in the integral part, like KI/(s+ωp1) limiting its maximum amplification to KI/ωp1. Additional Pole ωp2 : For control stability we frequently need also a pole for the derivative part, so that KDꞏs becomes

2

221 /1

pD D

pp

sK K

ss

(2.2.2)

The total controller transfer function evaluates with ωp1=0 to

22 2 2

22 2

( ) ( )( )

1 / 0I p I P p P D pI

P Dp p

K K K s K K sK sCTF s K K

s s s s

Ansatz 2

0 1 22

0 1 2

( ) c c c

c c c

a a s a sQTF s

b b s b s

delivers

(2.2.3)

0 2c I pa K 1 2c I P pa K K 2 2c P D pa K K

0 0cb 1 2c pb 2 1pb

DC amplification according to (2.2.3) is CTF(s=0) = ac0/bc0 → ∞. In reality, the maximum controller amplification is limited, e.g. by the DC amplification of an operational amplifier. Parameter bc0 can be used to model a realistic DC amplification by bc0 = ac0 / CTF(s=0) = KI ꞏωp2 / ωp1. (2.2.4) Table 2.2.2: Matlab’s parameter designations and symbols for controller parameters

Matlab parameter designations Matlab symbol Author’s symbol Proportional controller parameter KP KP Integral controller parameter I KI Derivative controller parameter D KD Filter coefficient N ωp2


- 7 -

2.3.3 Translation to Time-Discrete Transfer Functions

Time-continuous model 2nd order model in time and frequency domain written as

0 1 2 0 1 2b y b y b y a x a x a x and 2

0 1 22

0 1 2

( )a a s a s

TF sb b s b s

, (2.3.1)

Respectively, can be approximately translated to the time-discrete model

0 1 1 2 2 0 1 1 2 2n n n n n nc y c y c y d x d x d x and 2

0 1 22

0 1 2

( )d d z d z

TF zc c z c z

(2.3.2)

with xn-k = x(tn – kꞏTs) and yn-k = y(tn – kꞏTs), tn actual time point and Ts sampling period Ts = 1/fs. Typically, we divide the time-discrete model by c0 to get c0=1, because this avoids the division by c0, as the computation of the new value yn is obtained from

0 1 1 2 2 1 1 2 20

1n n n n n ny d x d x d x c y c y

c . (2.3.3)

The equation is realized by the 2nd order time-discrete filter illustrated in Fig. 2.3.3. The accurate relationship

ssTz e 1

ln( )s

s zT

(2.3.4)

can be approximated linear as 11

s

zs

T

(2.3.5)

or bi-linear after Tustin as 1

1

2 1

1s

zs

T z

. (2.3.6)

Fig. 2.3.3: Schematic of a time-discrete filter.


- 8 -

3 Matlab / Simulink Behavioral Modeling 3.1 Computating Variables into Matlab Workspace File DCDCbuck_pcb00.m is a Matlab file with device data for a non-existing DCDCbuck board No. 00 to declare and compute required device parameters. Groups will get a boards with numbers >0, measure its particular device data to simulate, model and finally program it. Listing 3.1 Matlab file DCDCbuck_pdb00.m declaring & computing device parameters % File DCDC_buck_pcb00.m % ********************** % By M. Schubert, 19.Mar.2019 % % RLC Lowpass parameters Rg=150e-3; Rw=50e-3; RD=(Rg+Rw); L=43e-6; % Inductor with wire resistor Rw C=680e-6; RC=50e-3; % Capacitor and its Equivalent Serial Resistor (ESR) RL=1e6; GL=1/RL; % Load resistor: Measurement device input impedance % RLC lowpass transfer function paramters ap0=1; ap1=C*RC; ap2=0; bp0=1+RD*GL; bp1=(RC+RD+RD*RC*GL)*C+GL*L; bp2=(1+RC*GL)*L*C; aq0=-RD; aq1=-(RC*RD*C+L); aq2=-RC*L*C; bq0=bp0; bq1=bp1; bq2=bp2; % RLC lowpass selfmade transfer functions PTF_s = [0 2, ap0 ap1 ap2, bp0 bp1 bp2]; %RLC lowpass Process TF: Uout/Uin QTF_s = [0,2, aq0 aq1 aq2, bq0 bq1 bq2]; % RLC Quarrel: Uout/(-ILoad) % RLC lowpass Matlab transfer functions TFP_s = tf([ap2 ap1 ap0], [bp2 bp1 bp0]); %RLC lowpass Process TF: Uout/Uin TFQ_s = tf([aq2 aq1 aq0], [bq0 bq1 bq2]); % RLC Quarrel: Uout/(-ILoad) % % Controller Settings oRder=2; % set oRder if oRder==0; R=oRder; KP=1; CTF_s=[0,R, KP, 1]; %KI=0; KD=0; wn2=inf; % for Matlab LTI system elseif oRder==1; R=oRder; KP=1; fI=2e2; KI=2*pi*fI; CTF_s=[0,R, KI KP, 0 1]; wn2=inf; elseif oRder==2; R=oRder; KP=1; fI=2e2; KI=2*pi*fI; fD=30e3; KD=1/(2*pi*fD); wn2=inf; CTF_s=[0,R, KI KP KD, 0 1 0]; else % Parameters from Matlab/Simulink optimiziation R=2; KP=0.1931; KI=794.4; Kd=9.89666e-06; wn2=50690; CTF_s=[0,R, KI KP KD, 0 1 1/wn2]; % control TF as selfmade LTI system TFC_s = tf([KD KP KI], [1/wn2 1 0]); % controler TF as Matlab LTI system TFC_z = c2d(TFC_s,Ts); % s->z with Matlab functions, sampling interval Ts end; % % DAC specification if exist('Tclock') ~= 1; fclock=50e6; Tclock=1/fclock; end; pwm_period=330; Ts=Tclock*pwm_period; fs=1/Ts; % sampling fcequency Vcc=3.3; Udamin=0; Udamax=Vcc; Ndamin=0; Ndamax=pwm_period; delta1=(Udamax-Udamin)/(Ndamax-Ndamin); bda=[Udamin Udamax]; % upper and lower bounds of output fprintf('DAC: PWM_period=%i bits, Uoutmin=%d, Uoutmax=%d, delta1=%d \n',... pwm_period, Udamin, Udamax, delta1); % % ADC and DDC specification Uadmin=0; Uadmax=4.095; Nadmin=0; Nadmax=4095; alpha1=(Nadmax-Nadmin)/(Uadmax-Uadmin); bad=[Nadmin Nadmax]; fprintf('ADC: Uinmin=%d, Uinmax=%d, Nadmin=%d, Nadmax=%d, alpha1=%d \n',... Uadmin, Uadmax, Nadmin, Nadmax, alpha1); %


- 9 -

3.2 Time-Continuous Simulink Simulation (a) Simulink model of the control loop (b) Simulink Scope

Fig. 3.2.1: Time-continuous model DCDCbuck_tc.slx with workspace of DCDCbuck.m To start working with Simulink, … Start Matlab, e.g. with double-click left on file DCDCbuck_pcb00.m. Clear the workspace with command clear all. Type command simulink into the Matlab Command Window. → Simulink window opens. To get started with Simulink… Click on icon Feedback Controller → a window named untitled opens. Select File > Save > DCDCbuck_tc.slx > Save (we use “_tc” for time continuous) Close all Matlab windos. You should now find file DCDCbuck_tc.xls in your working directory. Optimization of Time-Continuous PID Controller Parameters In your MS Windows working directory double-click left on file DCDCbuck_tc.slx. →

Simulink Model Window entitled DCDCbuck_tc will open In Model Window DCDCbuck_tc > Icon: Library Browser → Simulink Library Browser

opens. Click on the green Run button → something simulates but we cannot see anything. To get an oscilloscope clock on Library Browser icon → Simulink Library Bowser opens. In Simulink Library Bowser window > press left mouse button on Scope and drag it into

the DCDCbuck_tc model window near its right edge. Press left mouse button on the Scope’s input connector indicated by a '>' sign and draw a

wire to the output of the Plant. To move schematics elements such as wires define a box around them holding left mouse

button while drawing the box diagonal, release mouse button and drag the selected wire. Double click left on the Scope in the model window → a new scope screen window opens. Click on Run button again, either in the Scope window or in the model window. You

should see an oscillating step response now. Save the model and quit Matlab. Open file DCDCbuck_tc.xls again → you are nearly at the point where you left Matlab. All

you need to do click Run button again. Note control parameters with an accuracy of 4 decimal places:

P = , I = , D = , N = ,


- 10 -

Handling the Simulink Scope is essential to observe your simulation. We want ot observe 3 voltages on the oscilloscope. Delete the wire to the Scope input. Drag from Simulink Library Browser > Signal Routing the 2-input Mux icon into your

model window directly before the Scope input. Connect Mux output and Scope input with a wire. Double-click left on the Mux icon and select Number of Inputs to 3 > OK. Connect wires (i) reference to upper Mux entry, (ii) control input to medium Mux input

and (iii) measured output to lower Mux input. Click Run to see the three traces on the Scope’s screen window. Try Tools > Zoom In | X | Y | Out and Try Zoom > Pan. Unzoom (click left on icon with 4 arrows in 4 directions) Use Tools > Measurements > Trace Selection > Measured Output and > Peak Finder To implement your own model DCDCbuck_tc.slx … Click on the Plant icon in the DCDCbuck_tc model window and then Delete on your

keybord to delete it. In model window click on Library Browser → Simulink Library Browser opens. In the Library Browser > Simulink > Continuous Drag icon Tansfer Fcn into the model window at the place of the deleted plant and use left

mouse button to drag the wires to the respective connectors of the Plant. Run the model again. It should delver a step response with some voltage overshoot. Click on the transfer function model to see its name Transfer Fcn and rename it to Process. Double click left onto the Process model: A window entitled Block Parameters: Process

opens. Change in subwindow Numerator coefficients string "[1]” → "[ap2 ap1 ap0]" and in

subwindow Denominator coefficients string “[1 1]" → "[bp2 bp1 bp0]". > Apply > OK.

The icon entitle Process has a red frame and inscription ( )

( )

num s

den s.

Take the edges of the Process icon and increase it until you see its inscription similar to 2

2 1 0

22 1 0

p p p

p p p

a s a s a

b s b s b

. If necessary increase model window and drag wires fit get it.

The Process icon still has a red frame. Click Run button to get the error message that tells us, that parameters ap# and bp#, #=0,1,2, are not yet defined.

Go to the Matlab window and run file DCDCbuck_pcb00.m. Observe the variable that are now created in the Workspace window. Variables ap#, bp#, #=0,1,2, should be amoung them and Simulink has access to this workspace.

After creation of ap#, bp#, #=0,1,2, click into Simulink model window again and click Run button. The red frame around Process icon shuld disappear an we get a simulation result.

The voltage overshoot of the controller is unrealistic. Limit it to 0…3.3V: Select Simulink Library Borwser > Simulink > Discontinuities, drag icon Saturation into you model and place it after the controller. Open icon and Upper limit: 3.3 and Lower limit: 0.

Complete wiring.


- 11 -

Label wire after Saturation: click left on wire, click on "…" over wire > Enable Data Logging. In the Property Inspector (right in model window) set: Signal name: u. → Run.

To optimize the control parameters … Double-click left on the Controller box. Double-click left on the icon entitled PID(s). Are you an expert to optimize PIC control parameters? If not click on Tune… and Matlab

will do it. PID Tuner window opens. Wait until optimization is ready and hit Update button. Close Tuner window and Run the model again. With optimized control parameters we cannot see details any more. To adjust simulation parameters … Double-click left on the Reference box. Set Step time to 100e-6 (i.e. 100 μs) and Final value to 4e-3 (i.e. 4 ms) > Apply > OK. Run the model again. Simulaton time of 2s is still too long, isn’t it? Simulation > Model Configuration Parameters > Stop time → 4e-3 > Apply > OK. Run the model again. Use Zoom function in the Scope’s screen window to observe details. To end the session and clean up … Quit Simulink and Matlab. Set Step time to 100e-6 (i.e. 100 μs), Initial value: 0, Final value: 1, Sample time: 0 > OK. Save your model file (*.slx). Delete Simulin Cache file (*.slxc) and directory .\slprj. Exercise 1: Add a load current to the output of the the circuit in Fig. 2.2(b) and include it into the Simulink model such, that IL := 1A if 2ms ≤ t ≤ 3ms, 0A otherwise. Exercise 2: Change System as shown in Fig. 3.2.2: Simulation from 0-5ms, input x steps up at 100μs from 0 → 2.7V and steps down to 1.2V at 2ms. A load current pulse of IL=1A occurs from 3-4ms. Oscilloscope measures IL at a 4th channel.

Fig. 3.2.2: System extension: Step from 0 to 2.7V at 100μs, step down to 1.2V at 1.5ms, implement a current puls IL=1A from 3-4ms.


- 12 -

Solutions to the exercises:

Using a Callback Button in Simulink Up to now, we hve to oben the Simulink model and run the appropriate Matlab code to get the desired parameters as workspace viriables. We will now place the Matlab source coede within the Simulink model. Simulink Library Browser > Simulink > Dashboard: Drag Callback Button into your

Simulink model. Single-click left mouse button on the Callback Button → it gets a blue frame. Copy Matlab code in the Property Inspector window under keyword ClickFcn. By default

you should be in index tab Parameters. Single-click left mouse button somewhere in the Simulink model → Callback button gets

grey Single-click left mouse button on the Callback button → button gets a blue frame and

Matlab code within Property Inspector window becomes visible. Single-click left mouse button on Callback Button again for longer time (some seconds). When you see the Matlab code was executed and variables appear in the workspace → run

Simulink model.


- 13 -

3.3 Time-Discrete Simulink Simulation with Quantization

Fig. 3.3: PID controller made time-discrete, ADC and DAC included We use the configuration as shown in Fig. 3.2.2 and change it from a time-continuous to a time-discrete controller. Transition to a time-discret controller Copy your latest file DCDCbuck_tc.slx → DCDCbuck_td.slx. Open DCDCbuck_td.slx and check if it runs correctly. Then delete the PID(s) Controller

icon. Fetch a new controller icon PID(z) from the Simulink Library, however this time from

Simulink > Discrete, not from Simulink > Continuous. Place and wire it at the position of the deleted PID(s) controller icon.

Run the model. It should simulate but the results will most probably be unsatisfactory. Open the PID(z) Controller icon, set Sample Time to pwm_period*Tclock. (These

variables are declared in the Matlab workspace by file DCDCbuck_pcb00.m, whereas pwm_period is the number of clock cycles of the PWM DAC and Tclock = 1/fclock is the clock period, which is 20ns = 1/50MHz for the DE1-SoC board.)

Click on Tune… → Update Block in the PID tuner → OK for PID(z) controller. Recall the control parameters with an accuracy of 4 decimal places for the time continuous

controller: P = , I = , D = , N = , .......... ........... .......... ..........

Note control parameters with an accuracy of 4 decimal places for the time-discrete controller: P = , I = , D = , N = , .......... ........... .......... ..........

Switch back and forth between “Continuous Time” and “Discrete Time”. What expression replaces the Laplace variable s in the time-discete model?: s = .............. Remark: Sampling period Ts = pwm_period*Tclock. Click OK to close the controller icon.

Run the simulation again. Result should be similar as for the time-continuous simulation.


- 14 -

In time-discrete systems we wil typically need A/D and D/A converters. Value-discretization is referred to als quantization. Quantize Model A quantizer with smallest step Δ can be modeled as

( / )quantizedy round x

Model PWM DAC as Quantizer in the Forward Branch Incorporate a Quantizer from Simulink Library Browser > Simulink > Discontinuities

between controller and saturation block. Click on the Quantizer icon and set Quantization interval: Vcc / pwm_period, corresponding to 10mV for pwm_period=330 and VCC = 3.3V. Run the model. (shouldn’t be much difference.)

Optimzie the controller parameters P, I, D, N. Does the quantization change much? .............................................................

Run the model: Big changes with respect to previous, analog model? ...............

Remark: The control unit optimization handles the quantizer as unity gain. .......... Model ADC as Quantizer in the Feedback Branch Incorporate a Quantizer with Quantization interval: 1e-3 into the feedback branch, i.e. with

input y and output wire labeled v. Remark: The DE1-SoC board uses the LTC2308 [xxx] ADC which translates 4.095V into a digital 12-bit signal, i.e. to the integral numbers 0-4095. This corresponds to 1mV/bit.

Optimzie the controller parameters P, I, D, N. Does the quantization change much .............................................................

Run the model: Big changes with respect to previous, analog model? ...............

Save this model as DCDCbuck_td.sli along with Matlab file DCDCbuck_pcb00.m. Model-Based Design as offered for Matlab/Simulink can translate the time-discrete transfer functions as PID(z) of controller directly into code, e.g. VHDL, Verilog, C.


- 15 -

3.4 Time-Discrete Simulation Modeling A/D and D/A Converters

Fig. 3.4.1: PID controller made time-discrete, DAC, ADC and DDC included We use the configuration as shown in Fig. 3.3 and change the quantizers to A/D and D/A converters. D/A Converter (DAC) Modeling A D/A converter (DAC) with integral input number NDAC,in and output voltage UDAC,out can be modeled as

2 3, 0 1 , 2 , 3 , ...DAC out DAC in DAC in DAC inU N N N

If the DAC is linear in a signal processing sense, then Δk = 0 for k ≠ 1 with Δ1 being the amplification of the DAC:

, 1 ,DAC out DAC inU N .

PWM DAC Converter Modeling DACs that have to spend power with high efficiency are typically realized as pulse-with modulators (PWM), that switch between two voltage sources Usmin and Usmax, representing the minimum and maximum of the sample, respectively. Depending on digital input Ns, = NDACin, the modulator sets Ns output bits to Usmax and (pwm_period - Ns) bits to Usmin, when 0 ≤ Ns ≤ pwm_period. Consequently, the average sample voltage is

max mins H s Ls

s

U T U TU

T

with high-state period TH = NsꞏTclock, low-state period TL = (pwm_period - Ns)ꞏTclock and sampling period Ts = TH + TL. In Fig. 3.4.2(a) pwm_period = 8, TH = 3ꞏTclock and TL=5ꞏTclock.


- 16 -

Fig. 3.4.2: Using pulse width modulation (PWM) for digital-to-analog conversion (DAC) The sampling interval of a DAC output sample is Ts = Tclock ꞏ pwm_period fs = fclock. / pwm_period. with clock frequency fclock = 1/Tclock and sampling frequency fs = 1/ Ts. This is illustrated in Fig. 3.4.2 with pwm_period = 8. PWM is used for highly efficient output performance, as power dissipated in the switch is PV = US*IS, with US being the voltage across and IS the current through the switch. When the switch is ON or OFF, either voltage US or current IS is close to zero, respectively. Consequently, power dissipated in the switch is significantly lower than the average power transported to the load, thus yielding high efficiency. Modeling the PWM DAC in the Forward Branch with Matlab The PWM DAC in out model’s forward banch converts integral numbers from 0…330 to voltages from 0…VCC = 3.3V. It has an amplification of Δ1 = 3.3V/330bit = 0.01V/bit. To model it: Change the step size of the DAC from Vcc / pwm_length = 3.3/330 = 0.01 to 1. Incorporate the amplifier from Simulink Librry Browser > Math Operations > Gain with

gain delta1 = Δ1 behind the DAC as illustrated in Fig. 3.4.1. Check for delta1 in the Matlab workspace, it should be 0.001. Run the model again. Unsatisfied? This is, because the loop gain was multiplied by factor Δ1 = 0.01. Tune the PID controller again and run the model. Note control parameters with an accuracy of 4 decimal places for the time-discrete

controller: P = , I = , D = , N = , .......... ........... .......... ..........

Compare these paramters with those before including the Δ1-attenuator. ...........................................................


- 17 -

Run the model. What do you observe ........................................................... ...........................................................

A/D Converter (ADC) Modeling An A/D converter (ADC) with input voltage UADCin and integral input number NADCout can be modeled as

2 30 1 2 3 ...ADCout ADCin ACDCin ADCinN round U U U

If the ADC is linear in a signal processing sense, then αk = 0 for k ≠ 1 with α1 being the amplification of the ADC:

, 1 ,DAC out DAC inU round N .

For transfer function modeling rounding is omitted delivering a simple amplifier as ADC model:

, 1 ,DAC out DAC inU N .

Modeling the ADC in the Feedback Branch with Matlab The A/D converter (ADC) in the feedback branch was modeled as as quantizer. This is not

realistic, because its converts voltages from 0…4.095V to integral numbers from 0…4095, as it can output integral bits only. Consequently, it must have an amplification of α1 = 4095bits/4.095V = 1000/V.

Change step size of the ADC to 1. Incorporate the amplifier with gain alpha1 = α1 before the ADC as illustrated in Fig. 3.4.1. Check for alpha1 in the Matlab workspace, it should be 1000. Run the model again. Unsatisfied? This is amongst other things, because the loop gain was lowered by a factor

1000. Tune the PID controller again and run the model. Note control parameters with an accuracy of 4 decimal places for the time-discrete

controller:. P = , I = , D = , N = , .......... ........... .......... ..........

Compare these paramters with those before including the α1-attenuator. ...........................................................

Run the model again. Unsatisfied? Most probably … ..........


- 18 -

Modeling the Preceding Digital-to-Digital Converter (DDC) with Matlab The loop works excellent meahnwhile, but most probably you won’t see it. Notation: In the following we use lower case letters for tranisent variables like x, y, e, v… plotted over time axis, and capital letters for their spectral transfer functions plotted over frequency axis, e.g. X, Y, E, V… . The latter are modeled in Laplace vairiable s for time-continuous systems, e.g. X(s), and in z for time-discrete systems, e.g. X(z). Techniques to translate transfer functions from s → z will be introduced later. Intuitively it is obvious, that something is wrong when the input difference point of the feedback loop computes a difference e = x – v with x being the set point with range 0…3.3V and v the process variable with range 0…4095 mV. Formally we find that a feedback loop consisting of a feed forward branch F and feedback branch B behaves as

1

1FBF

STFFB B

.

The integral part of the PID controller has the task of providing high static amplification to yield the loop behavior B-1. In the DC/DC-buck controller example feedback branch B is B = α1 = 1000bit/V, so that the closed-loop behavior is ~1/α1 yielding a gain of 1V/1000bit. Conseqeuntly, the digital-to-digital converter (DDC) preceeding the loop must compensate for the feedback network B with same transfer function as B, i.e. the DDC must feature an amplification of w/x = α1 = 1000 with w beint the input voltage in mV, so that e = w - v is computed as difference between both w and v in mV. Modeling the Preceding DDC with Matlab Fetch an amplifier from Simulink Library Browser and set its Gain value to α1 = alpha1 in

the workspace and name it DDC. Place it before the feedback loop to compute w = α1ꞏw and e = w - v as shown in Fig. 3.4.1. Tune the PID controller again. Any change? Explain the phenomenon. ........................................................... ...........................................................

Run the model again. Satisfied? ..........


- 19 -

4 System Level Modeling and Simulation using LTspice 4.1 Introduction: Spice Analyzes

4.1.1 About Spice

SPICE (Simulation Program with Integrated Circuit Emphasis) was presented as Spice1 in 1973 by the University of California, Berkely (UCB), with FORTRAN. Today, the code for vesion 3f5 is available in C with textual (ASCII) input. It is the kernel to many commercial simulators adding schematics entry. From nowadays point of view it is an extreme low-level tool suitable to simulate circuits with basic electronic devices such as transistors and resistors as mathematical models. However, there are some features that make it suitable for high-level simulation also: (i) behavioral sources with user-defined mathematical models, and (ii) the possibility to simulate LTI models defined in Laplace variable s. This makes Spice interesting to use it for Systel level models with easily added detailed components. Spice is capacble of simulating some digital devices but is not very suitable as digital simulator. 4.1.2 Spice Analyzes

Fig. 4.1.2: Spice analyzes


- 20 -

Spice offers several analyzes. In the ASCII input deck of Spice directives begin with a dot. Text after a semi-colon is comment.

.OP (operting point) Static computation of voltages and currents at time t=0. Capacitors are handled as electrical interruption and inductors as electrical short ciruits.

.DC DC investigation plotted over a voltage or current range, it can be seen as assembly of several operating points for several source voltages or currents.

.AC Small signal analysis over frequency axis, which is typically logarithmic. After computation of an operating point (OP) the circuit is linearized in this OP before an LTI model is computed with capacitors having the impedance XC = 1/(sC) and inductors XL = sL, whereas s=jω j2πf with f being the frequency.

.TF (transfer function). A quite unknown analysis corresponding to .AC at f=0.

.TRAN Large signal analysis over time starting from an operating point as t=0. Several Spice versions are available and several of them available for free. Most free versions have limitations. LTspice has no limitations but its library contains devices of Linear Technology (LT) only, and since LT is a part of Analog Devices (AD) also devices of AD.


- 21 -

4.2 Verify LTI Models of RLC Lowpass with LTspice Subchapter 4.2. is concerned with modeling the plant (or process) of the control loop as well as the D/A converter (DAC) driving it. Pcb00 is a non-existing theoretical board similar to boards plb##, ## = 01…22, used in the practical training. Circuits and contents of this chapter are: A1_RLC_d_pcb00_devices: RLC lowpass model using devices (RLC_d) A2_RLC_d_pcb00_parameterized: Parameterizing devices A3_RLC_d_pcb00_subckt: Modularization using subcircuits A4_RLC_ds_pcb00: RLC lowpass model adding RLC_s. A5_RLC_dsz_pcb00: RLC lowpass model adding RLC_z. A6_RLC_PWM_dsz_pcb00: Behavioral PWM-DAC model (PWM). A7_RLC_PWM_FET_dsz_pcb00: adding realistic Power-FET models. B1_DCDCbuck_pcb00_s: Control loop with controller modeled in s plane. B2_DCDCbuck_pcb00_sz: Control loop with controller modeled in z plane also. 4.2.1 RLC Lowpass Using Devices (RLC_d)

Assemble schematic as shown in Fig. 4.2.1 (a), perform transient and AC analysis, save both schematic and plot and respective files *.asc and *.plt.

(a)

(b) (c)

Fig. 4.2.1 (a) Schematic, (b) transient and (c) AC analysis 10 Hz-1 MHz, 100 points/decade


- 22 -

4.2.2 Parameterizing Devices

Fig. 4.2.2: Same result as in Fig. 4.2.1 with constants assigned in .param directive. Load current controlled by voltage controlled current source with transconductance G=1A/V.

We will now parameterize the device parameters. So they are no more noted as numbers but as constants in curly braces {}. Furthermore, it is easier when we replace the load current source in Fig. 4.2.1 by a voltage controlled current source with transconductance Gm=1. This translates a voltage of x Volts applied at its input into a current of x Amperes at its output. In Fig. 4.2.2 this current souce is named iLoad and is driven by voltage source i_ctrl.


- 23 -

4.2.3 Modularization using Subcircuits

Fig. 4.2.3: Same result as in Figs. 4.2.1 and 4.2.2 with Wave generator and RLC lowpass modeled as scucircuits.

Creating a subcircuit LTspice menu bar: File > New Schematic; File > Save As… <name>.asc, ** Create circuit in *.asc file File > New Symbol; File > Save As… <name>.asy ** must be same names Draw > Rect (> draw a rectangle) Draw > Line (> draw lines for external connectors) Draw > Text (> place box label into the box) Edit > Attributes > Attribute Window > Instname > OK (> place “InstName” over the box) Edit > Attributes > Edit Attributes > Value (> add the instance name) Edit > Add Pin/Port > Label > (I/O signal names); Offset > 20; Justification > (select bound.) Characteristic initial of subcircuits is letter X. Paramters are accessible within the subcircuit when they are ot overridden there.


- 24 -

4.2.4 RLC Lowpass Using Time-Continuous Transfer Function RLC_s.

Create subcircuit RLC_s, model within it the RLC lowpass behavior as linear superposition of transfer functions PTF(s) and QTF(s) and verify it against the device-based model. (a) Additional subcircuit RLC_s included in top-level circuit

(b) Subcircuit RLC_s

Fig. 4.2.4: Same result as in Fig. 4.2.1 with constants assigned in .param directive. PTF(s): Process transfer function of the plant To model the process transfer function PTF(s) use voltage-controlled voltage source (Spice label letter E), name it Plant, input is u versus grond and output named p to model the transfer function according to (2.1.1) as amplification Laplace.=(ap0+ap1*s+ap2*s**2)/((bp0+bp1*s+bp2*s**2)


- 25 -

whereas s**2 stand for s2. As the coefficients ap#, bp# , #=0,1,2, are still undefined at this point, we declare them with a Spice directive according to (2.1.3) as .param ap0=1 ap1=C*RC ap2=0 bp0=1+RD*GL bp1=(RC+RD+RD*RC*GL)*C+GL*L bp2=(1+RC*GL)*L*C

Simulate and compare output ps to circuit output yd. Should be nearly identical. However, the inference transfer function QTF sill missing. QTF(s): Infrence transfer function of the plant To model the inference transfer function QTF(s) copy (F6) the voltage-controlled voltage source named Plant, rename it to Inference. Input is the load current computed from IL = (UipLoad - UimLoad)/1Ω. Output qs models load current impact according to (2.1.2) as Laplace.=(aq0+aq1*s+aq2*s**2)/((bq0+bq1*s+bq2*s**2) As the coefficients aq#, bq# , # = 0,1,2, are still undefined at this point, we declare them with a Spice directive according to (2.1.4) as .param aq0=-RD aq1=-(RC*RD*C+L) aq2=-RC*L*C bq0=bp0 bq1=bp1 bq2=bp2 Linear superposition for LTI models allows for combination of PTF(s) and QTF(s) Use a behavioral voltage source (Spice initial letter BV), name it TF_s, name qutput ys and model its function as V=V(ps)+V(qs) Simulate and compare output ys to circuit output y. The results obtained with devices and with Laplace transfer function should be very similar. (Small deviations due to round-off noise are unavoidable.).


- 26 -

4.2.5 RLC Lowpass Modeled as Time-Discrete Transfer Function RLC_z

Create subcircuit RLC_z, model within it the RLC lowpass behavior as linear superposition of transfer functions PTF(z) and QTF(z) and verify it against the device-based model. Fig. 4.2.5: Same result as in Fig. 4.2.1. (a) Additional subcircuit RLC_z included in top-level circuit

(b) Schematics: Top: process transferfunction PTF(z), Bottom: inference transfer function QTF(z) and their linear superposition by summation.

(c) Process Transfer function PTF(z)

(d) Inference transfer function QTF(z) + sum

Fig. 4.2.5: RLC lowpass model: (a) schematics, (b) and (c) LTspice behavioral model.


- 27 -

Using sampling interval Ts = pwm_periodꞏTclock with example values pwm_period=330, Tclock = 1/fclock = 1/50MHz = 20ns delivers fs = 1/Ts = 1/6600ns 152 KHz. Substitution of s according to Tustin’s (2.3.6) delivers for translation of 2nd order transfer function in s → z

xd0 = 2210 22 ss fafaa , xd1 = 220 222 sfaa , xd2 = 2210 22 ss fafaa

0xc = 2

0 1 22 2s sb b f b f , 1xc = 2

0 22 2 2 sb b f , 2xc = 2

0 1 22 2s sb b f b f

To get c0=1 we compute 0/x xk kc c c and 0/x x

k kd d c for k=0,1,2.

This procedure must be done for the coefficients of both process and inference transfer functions, PTF and QTF, respectively. In Fig. 4.2.4 (b), (c) digital flipflops symbolized as multiplication with z-1 are realized as delay Ts. Simulation of the model TF(z) with delays realizing flipflops as delay z-1 should deliver same results as with devices and TF(s). The advantage of using delays for modeling z-1 is that the capability of AC analysis is preserved.


- 28 -

4.2.6 Using Different Analysis Modi of Spice

An operating point (directive .OP) is required before any other simulation can start. It is the computati of voltages and currents in a static situation at time 0. It is computed implicitely and prited to the log-file when directive .OP is set. A DC simulation (directive .DC) consist basically of many operation point with varying static voltages and/or currents. It can be used e.g. to find a good starting condtin fot transient or AC simulation. A transient Spice simulation (directive .TRAN) is a simulation of large signal models versus time, as shown in Fig. 4.2.1(a). Large signal models can respect non-linearities. An AC simulation (directive .AC), also called called Bode diagram, frequeny response or spectral response is computed over frequency. After computing the operating point for an AC simulation the circuit is linearized in the operating point to a so-called small-signal model. It illustrates the input/output amplitude ratio and phase shift assuming a settled response to a constant input frequency f. The frequency response of a circuit is obtained by setting s=jω for time-continuous transfer functions or ssTz e → sj Tz e for time-discrete transfer functions, whereas ω=2πf with frequency f. Amplitude and phase diagrams are computed from transfer function TF as |TF(s=jω)| and |angle(TF(jω))|, respectively, with angle being the arcus tangens of imaginary divided by real part of TF. When considering frequency responses we must keep in mind Nyquist / Shannon cirteria: fs/2 is the maximum frequency that can be represted with sampling frequency fs. The consequences are: Approximated models TF(z) translated from s → z become increasingly inaccurate when f → fs/2.

TF( sj Tz e ) is periodic in fs , and |TF(z)| is symmetric with respect to all frequencies mꞏfs/2 for any integral number m. (This symmetry is hardly seen in Bode diagrams due to the logarithmic frequency axis.)

Exercise:

Compute transient step responses and frequency responses (Bode diagram) of the RLC lowpass for different resistor values, e.g. Rg from 180mΩ → 180μΩ. (You can undo this later with F9) How can we associate peaking in the spectral response with oscillations in the transient response? ........................................................... ..........................................................


- 29 -

4.2.7 Behavioral PWM-DAC model.

(a) PWM module included in circuit.

(b) Puls-width modulator

Fig. 4.2.7: Voltage u driving the RLC circuit is realized as pulse-width modulated signal Create subcircuit named PWM, build a pulse-width modulator within it and create RLC-lowpass driving voltage u as pulse-widht modulated (PWM) signal. Check how subcircuits RLC_d, RLC_s and RLC_z react on inputs u and level. We’ll see that time-discrete model comes to its limits with PWM input. AC mode doesn’t make sense with PWM.


- 30 -

4.2.8 Behavioral PWM-DAC Model with Detailed Power-FET Models.

(a) Additional FETbuffer included.

(b) Modeling the Buffer output with realistic power-FET models. Udummy can be used to short circuit the FET buffer.

Fig. 4.2.8: Voltage u driving the RLC circuit is realized with power MOSFET buffers. A particular strength of Spice si the availability of sophisticated device libraries. In Fig. 4.2.8(b) Ufets is driven with models of commercialy available power MOSEFTs. Exchanging the signals names Ufets and Udummy allows to short circuit the FET circuit. Even though the FET driver model does not drive the time-discrete model RLC_z, the avialablity of the FETs within the circuit makes the simulation of yz noisy. The simulator seems to approach its limits.


- 31 -

4.3 Modeling the DC/DC Buck Converter with LTspice

4.3.1 Modeling the Controller in s

(a) Complete circuit.

(b) DAC realization

(c) ADC Realization (d) Controller Realization

Fig. 4.3.1: DC/DC Control loop with PID controller transfer function CTF(s) modeled in s. Fig 4.3.1(a) illustrates how to model the complete control loop. Fig 4.3.1(b): The DAC was realized a factor 1/100. PWM and FET-buffer were omitted. Fig 4.3.1(c): The ADC was realized as factor 1000. The ADC in the feedback branch must be compensated for by an amplifier (here an ADC) as the ADC feedback branch. Fig 4.3.1(d): The PID controller was modeled as transfer function in s. The PID parameters computed with Matlab/Slimulink were not optimal for this Spice simulation.


- 32 -

4.3.2 Modeling the Controller in z

(a) Controller STF(z) included into the model.

Fig. 4.3.2: PID control loop with controller selectable

in s or z.

(b) Realization of controller STF(z)

Fig. 4.3.2(a) illustrates the complete feedback loop model with selectable controller. If DAC input is cs or cz, the Laplace or z-domain controller model is used, respectively. In this simulation the time-discrete controller was found to generate less noise, but the RLC circuit model should be made with devices or as Laplace transfer function. Fig. 4.3.2(b) illustrates the realization of controller subcircuit CTF_z. Again, a second order model in z is realized with delays like a finite state mechine with 3 controlled sources.


- 33 -

5 Conclusions Mathematical behavioral system-level modeling of a DC/DC buck conveter was presented along with a Matlab/Simulink a LTspice model of it. Key advantages of the Matlab/Simulink model: Easy to build, meaningful schematic diagram and unequaled computation of PID control prameters. Key advantage of the Spice circuit simulator is its combination of system modeling (using behavioral sources) toghether with easy incorporation of detailed device models, e.g. Power-FET switches. Problematic with Spice are poor digital modeling capabilities, TF(z) must be made with delays, that are problematic so simulate. Key skills with Simulink: Build, modify and check a system model with Simulink: Fetch elements from the Simulink library browser and place them in the model. Use constants, workspace variables and callback buttons in a Simulink model. Compute optimized PID control parameters. Use cursor to read exact time/value data in an oscillogram The advantage of using delays for modeling z-1 is that the capability of AC analysis is preserved. Key skills with LTspice: Build, modify and check a system model with LTspice: Build a simple circuit with devices (e.g. RLC lowpass). Use parametrized device parameters with .param statement Use Laplace transfer function model STF(s) with given parameters a#, b#, #=0..2. Use behavioral source bv Run predefined transient and AC simulations. Use cursor to read exact time/value data from a plot

6 References [1] V-Model [1] release 2.1, published by Deutsche Bundeswehr on 6. June 2017, available: http://weit-verein.de/v-

modell-xt-neues-release-2-1/ .

[2] Agile methods, available https://en.wikipedia.org/wiki/Agile

[3] Scrum, available https://en.wikipedia.org/wiki/Scrum

[4] Kanban boards, available: https://en.wikipedia.org/wiki/Kanban_board

[5] LTspice, available: https://de.wikipedia.org/wiki/LTspice

[6] TINA, available: https://en.wikipedia.org/wiki/TINA_(program)

[7] Simulink, available: https://en.wikipedia.org/wiki/Simulink

[8] Matlab, available: https://en.wikipedia.org/wiki/MATLAB

[9] ModelSim, available: https://en.wikipedia.org/wiki/ModelSim

[10] Quartus II, available: https://en.wikipedia.org/wiki/Altera_Quartus

[11] DE2 Development and Education Board User Manual, Terasic Technologies, available: http://www.ece.tufts.edu/~hchang/ee129-f06/project/project2/DE2_UserManual.pdf

[12] AME1117, available: http://pdf.datasheetcatalog.com/datasheet/ame/ame1117.pdf

[13] SysML, available: https://en.wikipedia.org/wiki/Systems_Modeling_Language

Date post:	05-Sep-2019
Category:	Documents
Upload:	others
View:	10 times
Download:	1 times

System Level Modeling Using Matlab / Simulink and LTspice · M. Schubert System-Leve Modeling using...

Documents