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System-On-a-Programmable-Chip (SOPC)
Implementation of the Silicon Track Card (STC)
Thesis Defense By
Arvindh-kumar LalamDepartment of Electrical and Computer Engineering
Florida A&M University – Florida State University
College of Engineering
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Outline
DZERO Experiment Silicon Track Card (STC) SOPC Implementation and Validation Content Addressable Memory (CAM) Hit-Filter Implementation using a CAM Results and Conclusions
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Proton Anti-proton Collision
Study the properties of known particlesEg. ‘top’ quark
Look for the unknown
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
DZERO (D0) Experiment The DZERO Experiment is
conducted in Tevatron Collider, at Fermi National Acceleration Laboratory
proton & anti-proton are made to
collide at high velocities in the TeVatron collider
The beams cross every 132 nsThe TeVatron
Collider
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
D0 DetectorFiber Tracker
Fiber Tracker (CFT) Identifies trajectory
information - “tracks”
Silicon Tracker Silicon Tracker (SMT)
Contains Silicon charge collectors - “strips”
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Particle tracks
Cross-section of Fiber Tracker (CFT)
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
D0 Trigger
L1 Framework
L1CAL
L1CFT
L1Muon
L1FPD
CAL
FPS/CPS
CFT
SMT
Muon
FPD
L2Cal
L2Ps
L2Muon
L2STT
L2CFT
Level 3L2Global
Trigger
Detector
Level2Level 1
SMT
L2CFT
preprocess SMT datafind clusters
associate clusters with L1CTT tracks
fit trajectories
L1CFT
L3
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
The Level_2 STT
SMT
L2CFT
preprocess SMT datafind clusters centroids
associate clusters with L1CTT tracks (finds hits)
fit trajectories
L1CFTSTC
TFC
FRC(roads)
L3
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
D0 Trigger -
CFT A Layer
CFT H Layer2 mm road
centroids
“clusters” : Groups of strips
SMT Layers“Si” strips
“centroid”: Centroid of a cluster
“road” : Track information translated for the STC
“hit” : A centroid that falls in a road
hits
STC
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
STC - Functionality Reformats received “strip” data Finds “Clusters” and their “centroids” Identifies “hits”
Stores intermediate data for debugging Implements a contention scheme
Several STCs function simultaneously Operates at PCI 33 MHz
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
STC - Main Data PathControl Lines Main Control
Data Lines
Handshake Signals
Control Lines
Hits
Downloaded Parameters
Control Logic
Hit FilterStrip Reader
Roads from FRC
SMT Data
Centroid Finder
L3 Buffers
To L3
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Control Logic and Channels
. . . .
Control and Feedback Signals
SMT Data(strip information)
Control Logic
Channel 0(STC0)
Channel 1(STC1)
Channel 7(STC7). . . . . .
7 . . . 1 0
To rest of L2STT
Control Logic designed at BU acts as an interface Each Control Logic controls 8 Channels (STCs) STC receives SMT data directly from SMT “commom data bus” is used to download hits
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
System-On-a-Programmable-Chip (SOPC) Discrete PCB components? SOPC
Altera APEX II EP2A90 7M gates: 1.5Mbits
SRAM Xylinx Virtex E XC2V10000
10M gates: 3.4 Mbits SRAM
Altera APEX 20KE EP20K600EBC652-1X Accommodates 1 STC
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
SOPC - Advantages
The circuit can be fit into a single device Occupies smaller area on the board Board-design interconnects are less complex Internal propagation delays are predictable
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Computer Aided Design Tools
Entry and Functional Simulations: Quartus II,
Active HDL 4.2 Entry in VHDL/Schematics
Synthesis: Quartus II, Synopsys FPGA Express Simulation and Configuration: Quartus II
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
SOPC Implementation of STC
Control Logic BU
Silicon Track Card FAMU-FSU COE
Used Test memory
space to store test
vectors of SMT data
Prototype Testing Board
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
SOPC Implementation - Hit download
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
SOPC Implementation - Result
Contention is successfully resolved
Channel Hits Trailers Hit-wordsSTC0 7 1 8STC1 2 1 2
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
STC - ResourcesDevice Family
Chip Logic Elements
Memory bits
Pins
FLEX
(CPLD)
EPF10K100EBC356-1
4,340 (83%) 10,532 (21%) 257 (94%)
EPF10K200EGC599-1
2,941 (29%) 79,424 (80%) 466 (99%)
EFF10K200SFC484-1
1,860 (18%) 10,692 (10%) 292 (79%)
Total 10,361 96,612 829
APEX
(SOPC)
EP20K600EBC 652-1X
6,744 (27%) 105,828 (33%) 262 (53%)
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
1
3
2
Found
Encoded AddressData
100
111
001
000
00
01
10
11
DataAddress
4 x 3 CAM with Encoded Output
Content Addressable Memory(CAM)
001
1 -
10 -
100
111
001
000
- 010
0 -
X -
100
111
001
000
100
111
001
000
- 100
1
00
- 011
0 -
X -
A memory like RAM and FIFO Takes data as input and provides the location Output can be “encoded” or “unencoded” A “found” signal is used to signal presence of
data
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Address(binary)
Data represented in the CAMEquivalent
Worddecimal binary
00 1 0 0 0 1 0 0 0 1
01 2, 30 0 1 0 0 0 1 1
0 0 1 d
10 4, 5, 6, 7 0 1 0 00 1 0 10 1 1 00 1 1 1
0 1 d d
11 0, 4, 8, 12 0 0 0 00 1 0 01 0 0 01 1 0 0
d d 0 0
Don’t-cares can be used to represent multiple digital words
A don’t-care (d) represents both ‘1’ and ‘0’ CAMs that accommodate don’t-cares are called
Ternary CAMs Eg: APEX CAM
Don’t cares
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
APEX CAM
1
4
2
Found
Encoded AddressData
0001
001d
01dd
dd00
00
01
10
11
DataAddress1100
1 -
11 -
0001
001d
01dd
dd00
- 1001
0 -
X -
0001
001d
01dd
dd00
0001
001d
01dd
dd00
- 0100
1
10, 11
Memory blocks of Altera’s APEX chip can be used as a Ternary CAM
The data can be stored in two ways During power-up (using an .mif file) During run-time
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Previous Hit Filter Receives roads and centroids Internally stores roads Uses ‘hit-match’ modules to find if a centroid
falls in the roads When a centroid falls in a road, it is a hit Each ‘hit-match’ generates a bit ‘1’ for hit
address-upper centroid address-lower
21…11 10 ... 0Upper Address Lower Address
Road Word
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Previous Hit Filter – Block Diagram
Comparator Module
46 “hit-match” modules in parallel
11
centroid
46
comparator word Hit-
Format(Encoder) 32
hit
22
road word
road select
6
Contains 46 ‘hit-match’ modules Each of the centroids is checked in all roads The locations of ‘1’s are encoded to generate a hit-word Hit-format, designed in VHDL, uses Finite State Machine Hit-format module sequentially searches for hits.
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Hit Filter – CAM-only model
Uses memory blocks instead of a combinational circuit (comparator)
Set of all the words existing between the road boundaries is called a “road-set”
Each road-set can be minimized to 12 words by using don’t cares
“road-sets” of each road are stored in the memory
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Actual road-set
10 0 0 0 0 0 1
20 0 0 0 0 1 00 0 0 0 0 1 1
30 0 0 0 1 0 00 0 0 0 1 1 1
40 0 0 1 0 0 00 0 0 1 1 1 1
50 0 1 0 0 0 00 0 1 1 1 1 1
60 1 0 0 0 0 00 1 1 1 1 1 1
71 0 0 0 0 0 01 0 1 1 1 1 1
81 1 0 0 0 0 01 1 0 1 1 1 1
91 1 1 0 0 0 01 1 1 0 1 1 1
101 1 1 1 0 0 01 1 1 1 0 1 1
111 1 1 1 1 0 01 1 1 1 1 0 1
121 1 1 1 1 1 1
Minimized Road-Set
1000 0000001.
.
1000 1111110
Minimized road-set
0 0 0 0 0 0 1
0 0 0 0 0 1 d
0 0 0 0 1 d d
0 0 0 1 d d d
0 0 1 d d d d
0 1 d d d d d
1 0 d d d d d
1 1 0 d d d d
1 1 1 0 d d d
1 1 1 1 0 d d
1 1 1 1 1 0 d
1 1 1 1 1 1 0
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
CAM-only model – Implementation
Road-setGenerator
11
centroid
11
Road-set word
CAM
found
22
road
Control signals
10
location
Hit create
32
hit
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
CAM-only Model - Functionality
Storing roads The road-set is minimized by using the “don’t cares” The minimized road-set is stored in an APEX CAM The CAM needs 50 clock cycles to store each road-set
Checking for hits Each of the centroids is given as input to the CAM If the centroid is found in the road-set, CAM returns
all the encoded locations. CAM takes only two clock cycles to find the location of
first hit
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Hit Filter – With New Encoder
Uses previous comparator block and a new “hit-word generator” block
The locations of ‘1’s in the comparator word are encoded using a CAM
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Hit Filter – Implementation
Comparator Module
46 “hit-match” modules in parallel
11
centroid
46
comparator word Hit-Word
Generator(Encoder) 32
hit
22
road word
road select
6
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
CAM as Encoder
1
4
2
Found
Encoded AddressData
d d d 1
d d 1 d
d 1 d d
1 d d d
00
01
10
11
DataAddress0001
1 -
00 -
d d d 1
d d 1 d
d 1 d d
1 d d d
- 0000
0 -
X -
d d d 1
d d 1 d
d 1 d d
1 d d d
d d d 1
d d 1 d
d 1 d d
1 d d d
- 1001
1
00, 11
ddd13
dd1d2
d1dd1
1ddd0
0123
4 x 4 Encoder Map
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Hit Filter Encoder Map45 44 43 ................................33 32 31 30 29 28 26...............................3 2 1 0
30 - - - 0
14 - - - 0
30
--
-0
d d d d d . . d d d d 1
d d d d d . . d d d 1 d
d d d d d . . d d 1 d d
d d d . . . . . . d d d
1 d d d d . . d d d d d
d 1 d d d . . d d d d d
d d 1 d d . . d d d d d
d d d . . . . . . d d d
31 x 31 CAM30...0
d d d . . . . . . d d d
d d d . . . . . . d d d
d d d . . . . . d d d
30
29
282
62
5...
.....
....
.....
.....
.4
32
10
d d d . . . . . d d d
d d d . . . . . d d d
d d d . . . . . d d d
d d d . . . . . d d d
d d d . . . . . d d d
d d d . . . . . d d d
d d d . . . . . d d d
d d d . . . . . d d d
d d d . . . . . d d d
14
--
-0
454
443
.....
.....
.....
....
.....
.....
...3
33
231
d d d d d . . d d d d d
d d d d d . . d d d d d
d d d d d . . d d d d d
d d d d d . . d d d d d
d d d d d . . d d d d d
d d d d d . . d d d d dd d d . . . . . d d 1
d d d . . . . . d 1 d
d d d . . . . . 1 d d
1 d d . . . . . d d d
d 1 d . . . . . d d d
d d 1 . . . . . d d d
15 x 15 CAM14...0
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . . . .
. . . . . . . . . . . . .
. . . . . . . . . . . . .
. . . . . . . . . . . . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
15 x 15 Encoder Map
31 x 31 Encoder Map
46 x 46 Encoder Map
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Hit-Word Generator
5
6
46
Comparator Word
HIT GENERATOR
CAM 31x31
CAM 15x15
31
15
32
HITControl Signals
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Hit Filter Results
6 roads(consecutive)
6 roads(distributed)
46 roads
Sequential search(contains comparator)
6 46 46
CAM only 270 * 310 * 2070*
With CAM block in hit-word generator
(contains comparator)6 46 46
* This depends on the upper and lower words of the road. The quoted figures correspond to the worst possible case.
Number of clock cycles required for storing road information
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Hit Filter Results
6 roads(consecutive)
6 roads(distributed)
46 roads
Sequential search(contains comparator)
32 150 232
CAM only 10 10 50
With CAM block in hit-word generator
(contains comparator)10 10 50
Number of clock cycles required for finding hits
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
STC Results
STC 6 consecutive roads
46 roads 6 distributed roads
Event1 Event2 Event1 Event2 Event1 Event2
Previous 4.878s 15.0s 16.48s 76.03s 11.636s 51.78s
Upgraded 4.03s 6.909s 5.242s 19.06s 4.03s 6.909s
% decrease in time taken
17% 54% 68% 75% 65% 87%
Event 1 : SMT data for a simple event Event 2 : SMT data for a complex event
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Conclusions
SOPC implementation was successfully verified
The upgraded STC shows an improvement of upto 87%
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Future Work
The number of roads Hit-Filter can accommodate can be increased
FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering
Acknowledgements National Science Foundation and the US Department of
Energy. Boston University
Faculty: Heintz, Narain, Popkov Engineers: Earle, Hazen Students: Kevin, Zabi
Florida State University – Physics Faculty: Adams, Prosper, Wahl Postdocs: Tentindo-Repond
Florida A&M University – Florida State University COE Faculty: Perry Students: Lolage, Meyers, Roper, Saunders
Altera, Aldec, Synopsys