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Advanced Techniques of Higher Performance Signal Processing
Partitioning Data Acquisition Systems
Dave Kress
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2
Today’s Agenda
The dilemmas of system architecture and partitioning
Analog vs. digital signal processing
The perils of sampling
Digital vs. digital
Where to put all the processing functions Gain Sampling Filtering Multiplexing Special analog processing Isolation
3
Analog to Electronic Signal Processing
SENSOR (INPUT)
DIGITAL PROCESSOR AMP CONVERTER
ACTUATOR (OUTPUT)
AMP CONVERTER
4
… in the Beginning …
There was a sensor, mechanical driver, stylus, recording medium, playback stylus, and mechanical amplifier – it worked
5
… and Then We Added Electronics …
6
Current Day Integrated Functions
Audio codecs
SoundMAX® computer audio codecs
I/O ports
Mixed-signal front ends: modems, communications, CCD imaging, flat panel displays
Transmit and receive signal processors
Direct conversion radio
Energy metering
Video encoders/decoders, codecs
Touchscreen digitizers
Analog microcontrollers (high performance ADCs, DACs, and ARM µP core and flash memory)
Blackfin® DSPs with on-board ADCs and DACs
Motion sensors with embedded ADCs
7
The Dilemmas of Partitioning
Why Digitize at All?
Analog vs. Digital Processing Filtering Linearization Detection
Multiplexing Multiple amplifiers, filters, converters Simultaneous sampling
Signal Control Gain ranging vs. high resolution Compression Filtering
8
Analog and Digital Domains Why Convert to Digital? Analog signals are continuous and provide the entire signal
Digital signals capture only a portion of the signal
Why digitize? Improved signal analysis potential More robust storage More accurate transmission Higher order filters implemented with less cost
Development objective of sampled data systems is to minimize effect of the sampling process
9
Analog vs. Digital Design
Analog Design Advantages Simpler and quicker to implement Lower power Analog systems don’t crash and need reboot
Disadvantages Difficult to change once in production – or at a customer Limited scale
Digital Design Advantages Changeable without hardware modification More filtering capability and scale Not sensitive to temperature
Disadvantages Initial software design takes longer More complex hardware Requires ADC that determines the SNR
10
Digital vs. Digital Design FPGA vs. DSP FPGA Pros Deliver higher performance through very high parallelism Flexible I/O to support high-speed analog interfaces Low fixed costs Quick design turns for hardware changes
FPGA Cons Higher power in redundant logic Higher cost at volume
DSP Pros Programming is simpler – many libraries and third-party support companies Higher speed for straight processing
DSP Cons Fixed hardware structure Limited scale for parallel processing
11
The Costs of Digitizing Signals
You need to learn sampling theory
The input signal will be compromised – the goal is to determine what’s acceptable
The input signal needs to be filtered
Signal reconstruction will require another data converter
12
Many Types of Sampled Data Systems
Analog-to-Digital Converters
Digital-to-Analog Converters
Sample-and-Hold Amplifiers
Peak Detectors
Comparators
Switched Cap Filters
Samples a Continuous Signal
Domain Conversion Analog to digital Digital to analog Continuous time to discrete time Continuous frequency to discrete
frequency
Sampling Rate Continuous, discontinuous
13
Sampled Data System: Sampling and Quantization
LPF OR BPF
N-BIT ADC DSP N-BIT
DAC
LPF OR BPF
fa
fs fs
t
AMPLITUDE QUANTIZATION DISCRETE
TIME SAMPLING
fa
1 fs
ts=
14
RESOLUTIONN
2-bit
4-bit
6-bit
8-bit
10-bit
12-bit
14-bit
16-bit
18-bit
20-bit
22-bit
24-bit
2N
4
16
64
256
1,024
4,096
16,384
65,536
262,144
1,048,576
4,194,304
16,777,216
VOLTAGE(10V FS)
2.5 V
625 mV
156 mV
39.1 mV
9.77 mV (10 mV)
2.44 mV
610 µV
153 µV
38 µV
9.54 µV (10 µV)
2.38 µV
596 nV*
ppm FS
250,000
62,500
15,625
3,906
977
244
61
15
4
1
0.24
0.06
% FS
25
6.25
1.56
0.39
0.098
0.024
0.0061
0.0015
0.0004
0.0001
0.000024
0.000006
dB FS
– 12
– 24
– 36
– 48
– 60
– 72
– 84
– 96
– 108
– 120
– 132
– 144
*600nV is the Johnson Noise in a 10kHz BW of a 2.2kΩ Resistor @ 25°C
Remember: 10-bits and 10V FS yields an LSB of 10mV, 1000ppm, or 0.1%.All other values may be calculated by powers of 2.
Quantization: The Size of a Least Significant Bit (LSB)
15
Practical Resolution Needs for Data Converters
Instrumentation Measurements Sensor resolution/accuracy of 0.5% = 1/200 8 bits equivalent to 1/256 -- digitizing will lose information 10x sensor resolution = 1/2000 -- 12 bits is 1/4096 Allows discrimination of small changes Can also be driven by display requirements
Dynamic Signal Measurements Audio systems need better than 0.1% distortion at 5% of full scale Equivalent to 1/20,000 -- 16 bits is 1/65,536
16
Ideal ADC Sampling 3 Different Frequencies, Sampled the Same
17
Ideal ADC Sampling Once Sampled, Information Is Lost
18
Baseband Antialiasing Filter Requirements
A
DR
f s
f a f s - f a
fs 2
STOPBAND ATTENUATION = DR TRANSITION BAND: fa to fs - fa CORNER FREQUENCY: fa
Antialias Filter Prevents Aliasing
Contributes to Dynamic Range
Antialias Filter Objectives Brick Wall (Steep/Deep Rolloff) Linear Passband Linear Phase
19
A Key Partitioning Question—Where to Filter?
Analog Filtering Hardware oriented—generally fixed design
Digital Filtering Software oriented—offers more flexibility
20
Purposes of Filtering
Noise Reduction Typically low-pass
Discrimination and Selection RF detection – channel separation Extracting small signals from noise
Signal Enhancement Music
Filter Complexity Derives from the Requirement
21
Types of Filters
Types of Analog filters Active More common at lower frequencies
Passive More common at higher frequencies
Types of Digital filters IIR (infinite impulse response) Based on analog filters More computationally efficient
FIR (finite impulse response) Can be linear phase More computationally intensive Can provide more power and flexibility
Digital filtering requires digitizing—which requires an analog anti-aliasing filter before the analog-to-digital converter
22
Comparing Analog and Digital Filters
Analog No computational limitations
to limit high frequency operation Subject to component drift
and accuracy Simpler circuit Unlimited dynamic range Basically no latency
Digital Computations must be
completed in sampling time— limits real-time operation Not subject to component
drift and accuracy More complex circuit Requires antialiasing filter,
ADC, DSP, DAC, and reconstruction filter
Dynamic range limited by converter resolution Much higher latency (delay) Some filter functions can only
be done digitally
23
Analog vs. Digital Filter Frequency Response Comparison
Digital Filtering
Throughput Considerations for Digital Filters
A digital biquad is a second-order recursive linear filter containing two poles and two zeros
Determine how many biquad sections (N) are required to realize the desired frequency response
Multiply this by the number of instruction cycles per biquad for the DSP and add overhead cycles
The result (plus overhead) is the minimum allowable sampling period (1 / fs) for real-time operation
26
Comparison Between IIR and FIR Filters
Sigma-delta ADC -- the multi-purpose part
Sigma-delta ADCs span the analog and digital world
Provide customized filtering and high-resolution data conversion
The core of digital audio processing
28
29
Sigma-Delta ADC - First-Order Modulator
∑ ∫ +
_
+VREF
–VREF
DIGITAL FILTER AND DECIMATOR
+
_
CLOCK Kfs
VIN N-BITS
fs
fs
A
B
1-BIT DATA STREAM
1-BIT DAC
LATCHED COMPARATOR (1-BIT ADC)
1-BIT, Kfs
SIGMA-DELTA MODULATOR
INTEGRATOR
Sampled Data System: Sampling and Quantization
31
Simplified Frequency Domain Linearized Model of a Sigma-Delta Modulator
∑ ANALOG FILTER H(f) = 1
f ∑
X Y
+
_
X – Y 1 f
( X – Y ) Q = QUANTIZATION NOISE
Y = 1 f
( X – Y ) + Q
REARRANGING, SOLVING FOR Y:
Y = X f + 1
+ Q f f + 1
SIGNAL TERM NOISE TERM
Y
32
Oversampling, Digital Filtering, Noise Shaping, and Decimation
fs 2
fs
Kfs 2
Kfs
Kfs Kfs 2
fs 2
fs 2
DIGITAL FILTER
REMOVED NOISE
REMOVED NOISE
QUANTIZATION NOISE = q / 12 q = 1 LSB ADC
ADC DIGITAL FILTER
Σ∆ MOD
DIGITAL FILTER
fs
Kfs
Kfs
DEC
fs
Nyquist Operation
Oversampling + Digital Filter + Decimation
Oversampling + Noise Shaping + Digital Filter + Decimation
A
B
C
DEC
fs
Data Acquisition Subsystem Configuration
Multiplexing Multiple preamps Multiple anti-alias filters Multiple ADCs
Gain Adjustable gain per channel PGA vs. high resolution ADC
Simultaneous Sampling Multiple signals correlated in time
Noise Reduction/Antialiasing Filter Placement
Special Analog Processing
Isolation
33
Data Acquisition Subsystem Configuration Multiplexing Multiplexing is done to reduce system cost by using fewer ADCs ADC is fast enough to handle all channels in sequence ADC errors are the same for all channels
Multiplexing issues Settling time after switching channels Multiplexer impedance may compromise signal Final buffer amplifier may be needed Multiplexer switching transients
Correlated sampling may require a faster solution How close in time sampling needs to be done Nyquist theory determines how often each signal needs to be sampled Total signal throughput rate Simultaneous sampling at lower rates Simultaneous conversion at higher rates
34
Sample-and-Hold Function Required for Digitizing AC Signals
ADC ENCODER
TIMING SAMPLING CLOCK
SW CONTROL
ANALOG INPUT
SAMPLE
HOLD
SAMPLE
C
ENCODER CONVERTS DURING HOLD TIME
SW CONTROL
N
Input Frequency Limitations of Non-Sampling ADC (Encoder)
N-BIT SAR ADC ENCODER CONVERSION TIME = 8µs
EXAMPLE: dv = 1 LSB = q dt = 8µs N = 12, 2N = 4096 fmax = 9.7 Hz
v(t) = 2N
2 sin (2π f t )
dv dt
2N
2 2π f cos (2π f t ) =
dv dt max
= 2(N–1) 2π f
dv dt max
2(N–1) 2π q fmax =
fs = 100 kSPS
ANALOG INPUT N
dv dt max
qπ 2N fmax =
q
q
q
Simple ADC Multiplexing—AD7298
8 inputs plus temp sensor and single track/hold
37
TEMPSENSOR
12-BITSUCCESSIVE
APPROXIMATIONADC
INPUTMUX
T/H
VDD GND
PD/RST
SCLKDOUTDINCS
VDRIVE
VIN7
VIN0
CONTROLLOGIC
SEQUENCER
VREF
BUFREF
AD7298
0875
4-00
1
TSENSE_BUSY
Simultaneous Sampling—AD7606 8 Track/Hold Inputs Sampled Together
V1V1GND
RFB1MΩ
1MΩ RFB
CLAMPCLAMP SECOND-
ORDER LPFT/H
V2V2GND
RFB1MΩ
1MΩ RFB
CLAMPCLAMP SECOND-
ORDER LPFT/H
V3V3GND
RFB1MΩ
1MΩ RFB
CLAMPCLAMP SECOND-
ORDER LPFT/H
V4V4GND
RFB1MΩ
1MΩ RFB
CLAMPCLAMP SECOND-
ORDER LPFT/H
V5V5GND
RFB1MΩ
1MΩ RFB
CLAMPCLAMP SECOND-
ORDER LPFT/H
V6V6GND
RFB1MΩ
1MΩ RFB
CLAMPCLAMP SECOND-
ORDER LPFT/H
V7V7GND
RFB1MΩ
1MΩ RFB
CLAMPCLAMP SECOND-
ORDER LPFT/H
V8V8GND
RFB1MΩ
1MΩ RFB
CLAMPCLAMP SECOND-
ORDER LPFT/H
8:1MUX
AGND
BUSYFRSTDATA
CONVST A CONVST B RESET RANGE
CONTROLINPUTS
CLK OSC
REFIN/REFOUT
REF SELECT
AGND
OS 2OS 1OS 0
DOUTADOUTB
RD/SCLKCS
PAR/SER/BYTE SELVDRIVE
16-BITSAR
DIGITALFILTER
PARALLEL/SERIAL
INTERFACE
2.5VREF
REFCAPB REFCAPA
SERIAL
PARALLEL
REGCAP
2.5VLDO
REGCAP
2.5VLDO
AVCCAVCC
DB[15:0]
AD7606
0847
9-00
1
38
Full High Speed Dual Sampling—AD9643 2 Complete Sampling ADCs at 170 MHz
14
14
REFERENCE
SERIAL PORT
SCLK SDIO CSB CLK+ CLK– SYNC
1 TO 8CLOCKDIVIDER
AD9643
VIN+A D0±
D13±
DCO±
OR±
PDWN
OEB
VIN–A
VIN+B
VCM
VIN–B
NOTES1. THE D0± TO D13± PINS REPRESENT BOTH THE CHANNEL A
AND CHANNEL B LVDS OUTPUT DATA.
AVDD AGND DRVDD
0963
6-00
1
.....PARALLELDDR LVDS
ANDDRIVERS
PIPELINE14-BITADC
PIPELINE14-BITADC
39
Positioning the Noise Reduction Filter to Reduce the Effects of the Op Amp Noise
ADCs often have very high input bandwidths, usually greater than fs/2 Low distortion drive amplifiers typically have high bandwidths Placing a simple LPF or BPF placed between the amp and the ADC is
an excellent noise reduction technique Filter output impedance must be able to drive ADC The output capacitor of the filter absorbs some of the ADC input
transient currents. 2.40
f F I L T E R
AMP
AMP
LPF OR BPF
LPF OR BPF
A DC
A DC
f F I L T E R f s
f s
f C L
f C L
f ADC
f ADC
(A)
(B)
Amp noise integrated over amp BW or ADC BW, whichever is less
Amp noise integrated over filter noise bandwidth only
Where to Put the Gain?
Partitioning question about using PGA vs. high resolution ADC
PGA with wide-range gain steps can extend effective resolution of ADC Provides fine resolution Not an exact solution unless gain ranges are perfectly matched Nonlinearity induced between ranges
Not as popular with advent of higher resolution ADCs
Still useful in certain applications
41
ADC Multiplexing with Programmable Gain— AD7194 16 inputs plus temp sensor and programmable gain amplifier
Accommodates sensors with widely varying signal levels
42
DVDD DGND REFIN1(+) REFIN1(–)
AIN1/P3AIN2/P2
AIN3/P1/REFIN2(+)AIN4/P0/REFIN2(–)
AINCOM
AD7194
SERIALINTERFACE
ANDCONTROL
LOGIC
REFERENCEDETECT
TEMPSENSOR
DOUT/RDY
DIN
SCLKCS
MCLK1 MCLK2
CLOCKCIRCUITRY
AVDD AGND
AIN5
AIN16
Σ-ΔADCPGAMUX
0856
6-00
1
AVDD
AGND
Special Analog Processing and Special Cases
Certain sensors require specialized analog processing to extract precise measurements Thermocouples—cold-junction compensation Wide-dynamic-range photodiodes—signal compression Linearization
Some sensors require precision tuning per unit—others can be tuned together
Calibration and replacement issues
Digital options—store adjustment coefficients in software
Isolation Analog or digital Power isolation
43
Thermocouples
Thermocouples require cold-junction compensation Traditionally done with specialized amplifiers with internal temperature sensors Newer techniques use high-accuracy temperature sensors and A-D converters
to allow compensation at the processor
Thermocouple non-linearity is non-linear Difficult to construct analog compensation Digital systems use look-up tables
Detailed analysis in the Low-Level Signal Acquisition session
44
High Accuracy Multichannel Thermocouple Measurement Solution (CN0172)
45
Log Amplifiers
Signal compression Many applications must capture signals over a very wide dynamic range Radio antennas capturing broadcast signals Photomultipliers and photodiodes capture light signals over a very wide range
To process and use these signals, they need to be compressed to a much smaller range
Logarithmic amplifiers Log amplifiers compress signals over ranges of as much as 120db – a million
to one -- to a normal range of 1 to 10 volts Accuracy is typically 0.1 to 0.5 dB -- 1 to 5%
Digital compression alternative Programmable gain amplifier combined with high-resolution ADC Can achieve range out to 120dB Limited at very high frequencies
Log Amp Transfer Function
IDEALACTUAL
SLOPE = VY
2VY
VY
IDEALACTUAL
VYLOG (VIN/VX)
+
- VIN=VX VIN=10VX VIN=100VX INPUT ONLOG SCALE
VOUT = VY log10
0
VINVX
IDEALACTUAL
SLOPE = VY
2VY
VY
IDEALACTUAL
VYLOG (VIN/VX)
+
- VIN=VX VIN=10VX VIN=100VX INPUT ONLOG SCALE
VOUT = VY log10
0
VINVX
Log Amplifier Accuracy
5
4
3
2
1
–4
–5
500MHz
100MHz
10MHz
–3
–2
–1
0
–80 –70 –60 –50 –40 –30 –20 –10 0 10 20
ERRO
R(d
B)
INPUT LEVEL (dBm)
AD8307 covers 80dB with 0.5dB accuracy
AD8307 six-decade RF power measurement
TO
ANTENNA
VP
604Ω
100kΩ1/2W
NC
2kΩ
VR12kΩ
INT ±3dB
51pF
51pF
0.1µF
NCOUTPUT
LEAD-THROUGH
CAPACITORS,1nF
1nF
NC = NO CONNECT
+5V
VOUT
AD8307INP VPS ENB INT
INM COM OFS OUT
8 7 6 5
2 3 4150Ω INPUTFROM P.A.
1µW TO1kW
22Ω
Oversampled SAR ADC with PGA Achieving Greater Than 125 dB Dynamic Range (CN0260) Dynamic gain ranging
Faster than high-resolution sigma delta
Sampling rate up to 2.5MSPS
50
Oversampled SAR ADC with PGA Achieving Greater Than 125 dB Dynamic Range (CN0260)
51
Where to Put the Isolation?
Isolation is used to galvanically separate systems Safety in patient monitoring High-voltage systems Remove high common-mode noise
Most commonly done at the digital level ADC converter signal to digital Transmitted across digital isolators
Providing power to isolated circuits needed
High-voltage amplifiers suitable in some motor control or power control systems
More detail in the Data and Power Isolation session
52
500 V Common-Mode Voltage Current Monitor (CN0218)
53
AD8212
54
Bidirectional Isolated High-Side Current Sense with 270 V Common-Mode Rejection (CN0240)
Novel Analog-to-Analog Isolator Using an Isolated Sigma-Delta Modulator, Isolated DC-to-DC Converter, and Active Filter (CN0185)
55
Reverse Partitioning Smarter peripheral devices sensing local conditions
Make local decisions to off-load main processor
Reduce programming load
Automatic gain control
Power control
56
Reverse Partitioning—AD5755 Quad 16-bit DAC for 4–20 mA industrial signaling
Dynamic power control for thermal management
On-chip diagnostics
57
AD5755
AVSS–15V AGND
AVDD+15V
AVCC5.0V
DVDDDGND
LDACCLEAR
SCLKSDIN
SYNCSDO
FAULT
DC-TO-DCCONVERTER
POWERCONTROL
INPUTSHIFT
REGISTERAND
CONTROL
STATUSREGISTER
POWER-ONRESET
REFERENCEBUFFERS
DACREG A
INPUTREG A
VREF
WATCHDOGTIMER
(SPI ACTIVITY)ALERT
REFOUT
REFIN
AD1
AD0
DAC A1616
SWA VBOOST_A
GAIN REG AOFFSET REG A
R1
R2 R3
RSET_A
VOUT_A
IOUT_B, IOUT_C, IOUT_D
RSET_B, RSET_C, RSET_D
+VSENSE_B, +VSENSE_C, +VSENSE_DVOUT_B, VOUT_C, VOUT_D
IOUT_A
+VSENSE_A
–VSENSE_A
DAC CHANNEL B
DAC CHANNEL A
DAC CHANNEL CDAC CHANNEL D
SWB, SWC, SWD VBOOST_B, VBOOST_C, VBOOST_D
7.4V TO 29.5VREG
VSEN1 VSEN2
+
0730
4-00
1
VOUTRANGE
SCALING
30kΩ
Flexible 4-Channel Analog Front End for Wide Dynamic Range Signal Conditioning (CN0251) This circuit has it all
Multiplexing front-end
Multiplexer buffer
Instrumentation amplifier for CMRR
Anti-alias filter
Funnel amplifier to fit ADC range
Internal programmable gain amplifier Gain ranges trimmed and matched
Sigma-delta ADC provides noise shaping
58
Flexible 4-Channel Analog Front End for Wide Dynamic Range Signal Conditioning (CN0251)
59
D3V3DGND
DGND AGND
–IN
IA
RGRG*
*OMIT RG FOR G = 1
RG+IN
+VS
VOUT
REF
–VS
AD8226
ADP1720
–OUTVN
VP
+OUT
NC
+IN 0.4x
–IN 0.8x
+IN 0.8x
–IN 0.4x
–VS
+VS1kΩ
1.25kΩ 100Ω
100kΩ
100Ω1.25kΩ
1kΩ
AD8475
1.25kΩ
1.25kΩ
MCLK1
NC
MCLK2
P0/R
EFIN
2(–)
P1/R
EFIN
2(+)
DVDD DGND
REF
IN1(
+)
REF
IN1(
–)
AIN2AIN1AIN3AIN4AINCOM
BPDSW
AGND
AD7192TEMP
SENSOR
AVDD
AGND
DOUT/RDY
DIN
SCLKCS
SYNC
P3P2
AVDDAGND
Σ-ΔADCM
UX
DOUT
DIN
SCLKCS
SYNC
P3P2
ADG1409S1A
S4B
DA1nF
IN OUTGND
1nF
10nF
4.02kΩ
4.02kΩ
DB
S4A
S1B
VS1A
VS4B
VS4A
VS1B
1-OF-4DECODER
A0GND A1
VDD
+15VA
EN VSS
–15VA
–15VA
+5VA330µH @ 100MHzA4V096
+5VA
+15VA
0.1µF
10nF
10nF
1µF
0.1µF
0.1µF
10µF
0.1µF
+15VA
+5VA
VOCM VOCM
ADR444
AD8475
VIN VOUTGND
+15VA
A4V096
PGA
D3V3
D3V3
DGND
1µF
0.1µF0.1µF
SERIALINTERFACE
ANDCONTROL
LOGIC
CLOCKCIRCUITRY
1035
1-00
1
2
1
1
27
6
45
8
3
4
10
12
18 19 15 16
23
24
3
4
5
617
9 1 2 7 8
25
2120
11131410
98
3
7
5
6
Tweet it out! @ADI_News #ADIDC13
What We Covered
The dilemmas of system architecture and partitioning
Analog vs. digital signal processing
The perils of sampling
Digital vs. digital
Where to put all the processing functions Gain Sampling Filtering Multiplexing Special analog processing Isolation
60
Tweet it out! @ADI_News #ADIDC13
Visit the Flexible 4-Channel Analog Front End for Wide Dynamic Range Signal Conditioning (CN0251) in the Exhibition Room
This flexible signal conditioning circuit is for processing signals of wide dynamic range, varying from several mV p-p to 20 V p-p. The circuit provides the necessary conditioning and level shifting and achieves the dynamic range using the internal programmable gain amplifier (PGA) of the high resolution analog-to-digital converter (ADC).
61
Image of demo/board
This demo board is available for purchase: www.analog.com/DC13-hardware
Tweet it out! @ADI_News #ADIDC13
FMComms1 Demo @ Exhibition Hall
New partitioning concepts for radio
Ubuntu Linux on ZC702
FMComms1 on FMC
HDMI Display and USB Keyboard/Mouse
Full Transmit and Receive
62
Image of demo/board
This demo board is available for purchase: www.analog.com/DC13hardware