Systematic Design of Operational Amplifiers -...

Willy Sansen 10-05 061

Systematic Design of Operational Amplifiers

Willy SansenKULeuven, ESAT-MICAS

Leuven, [email protected]


Table of contents

• Design of Single-stage OTA

• Design of Miller CMOS OTA

• Design for GBW and Phase Margin

• Other specs: Input range, output range, SR, ...

Ref.: Sansen : Analog design essentials, Springer 2006


Single-stage CMOS OTA : GBW

12

3

VDD

VSS

vOUT

CL

M1 M2

M3 M4

M7

+-

IBv v

Av =ro

if ro2 = ro4 = ro

gm1 2

BW = 1

2π (CL+Cn1)ro2

GBW = 2π (CL+Cn1)

gm1


CMOS OTA : Maximum GBW

vOUT-

CL

+-

IBv v

GBW = 2π CL

gm1

vOUT+

gm1 =

GBWmax = 2π CL

1

IB

IB

IB = 10 µA CL = 1 pF GBWmax ≈ 10 MHz

VGS1-VT

VGS1-VT

FOM = GBW.CL

IB= 1000

CL

[8]

[800]

0.2 V

MHzpF/mA


Single stage CMOS OTA : fnd

12

3

VDD

VSS

vOUT

CL

M1 M2

M3 M4

M7

+-

IBv v

GBW = 2π (CL+Cn1)

gm1

fnd = gm3

2π Cn2

Cn2 ≈ 2CGS3+ CDB3+ CDB1

≈ 4 CGS3

fnd ≈ fT34


Simple CMOS OTA : fnd

12

3

vOUT

M1 M2

M3 M4

M5

+-

Cn2fnd =

gm3

2π Cn2

-90o

0o

Av

f

f

fnd 2fnd

2x

PM = 90o - arctan + arctan ≈ 85oGBWfnd

GBW2 fnd

2x


Single stage CMOS OTA : Design 1

GBW = 100 MHz for CL = 2 pF

Techno: Lmin = 0.35 µm; K’n = 60 µA/V2 & K’

p = 30 µA/V2

IDS ? W ? L ?

gm = GBW 2π CL = 1.2 mS

IDS = gm VGS-VT

2 = gm10 = 0.12 mAVGS-VT = 0.2 V

WL =

IDSK'(VGS-VT)2 =100

Lp = Ln = 1 µmWp = 100 µm; Wn = 50 µm

GAIN !


Table of contents






Miller CMOS OTA

12

34

5

VDD

VSS

vOUT

CL

M1 M2

M3 M4

M5

M6

M7

+- Cc

1 : B

vv

Cn1

Two nodes

with highImpedance

causetwo poles

split by Cc

1 4

RL


Miller CMOS OTA : small-signal

12

34 vOUT

ZLM1 M2

M3 M4 M6

+-Ccvv

Cn1

go24 Cn1gm1 CLn4 = 10.2 pFgLo6

1 4Cc

gm6

GBW= 1MHzCL = 10 pF

gm1 = 7.5 µSgo24 = 0.03 µS

gm6 = 246 µS

Cn1 = 0.37 pF

Cc = 1 pF

RL = 10 kΩ

gLo6 = 120 µS

IDS1 = 1.1 µA IDS6 = 25 µA


Miller CMOS OTA : GBW

12

34

5

vOUT

CL

M1 M2

M3 M4

M5

M6

M7

+- Cc

1 : B

vv

Cn1

RL GBW = 2π Cc

gm1

fnd ≈ gm6

2π CLn4

Av1 = go24

gm1

gLo6

gm6

BW = 2π Av2Cc

go24

1Cn1

Cc1+

Av2 =


Miller CMOS OTA : poles and zero

1k 1M Hz

1k 1M

1pF

0.1pF

Cc

|Av|10fF

1

10

100

1000

f

f

fd

fnd

fz

Av0

Cct Av2

Cn1≈Cct

BWGBW

Pole splittingstarts at

0.1

but is sufficientfor Cc = 1pF

≈ 20 fF

Cc = 1pF

Cc = 0

fz = 2π Cc

gm6


Table of contents






Miller CMOS OTA: Design plan

GBW = 100 MHz and CL = 2 pFGBW = 2π Cc

gm1

fnd ≈ gm6

2π CLn4

1Cn1

Cc1+

Two equations forThree variables gm1, gm6 and Cc ?!?

Solution : choose gm1 or gm6 or Cc !!!


What is wrong with

choosing Cc = 1 pF ?


Miller CMOS OTA: Design vs Cc

GBW = 2π Cc

gm1

gm6

2π CLn4

11.3

3GBW ≈

Choose Cc ≈ 3 Cn1

gm6

Ccgm1≈ 4 CL

GBW = 100 MHz and CL = 2 pF

Choice Cc = 1 pF gives gm1 = 0.6 mS and gm6 = 4.8 mS

Choose Cn1 < Cc < CL


Miller CMOS OTA: Design vs Cc

Cc

gm1

gm6

gm6min

gm

Ccopt

gm6min =

3 GBW (2π CL)

≈ 4 CL


0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

0.01 0.1 1 10 100

1 MHz Miller CMOS OTA: Design vs Cc

gm6

pF Cc

2gm1

mS

gmtot

Cn1 ~ gm6

Cn1 ct

Cn1 = 0.4 pF

GBW = 1 MHz

CL = 10 pF

Cn1 = 0.4 pF

K’ = 20 µA/V2

VGS-VT = 0.2 V

L = 10 µm


Miller CMOS OTA : Design vs IDS6

gm6

Area M6

Area Cc

gm6min

Area gm6min =

3 GBW (2π CL)

gm6opt ≈ 1.3 gm6min

+ 30 %


Miller CMOS OTA : Design vs IDS1

gm1

Area M6

Area Cc

Area

CL


Optimum design for high speed Miller OTA - 1

CGS = kW k = 2 10 -11 F/cm

GBW =2π Cc

gm1

fnd =2π CL

gm6

1 + Cn1/Cc

1

CL = α Cc α ≈ 2

Cc = β Cn1 = β CGS6 β ≈ 3

fnd = γ GBW γ ≈ 2

GBW =fnd

2π CL

gm6

γ (1 + 1/ β)

1γ

=

CL = α Cc = α β Cn1 = α β CGS6 = α β kW6 W6 if CL


Optimum design Miller for high speed OTA - 2

gm =W

L 1 + 2.8 104 L /VGST

17 10-5

W, L in cm

L in cm

Elimination of CL yields

GBW =2π kW6

gm6

α β γ (1 + 1/ β)

1

1 + 2.8 104 L6 / VGST6

8.5 106GBW =

2π L6

1

α β γ (1 + 1/ β)

1

GBW is not determined by CL, only by L (and VGST) !!fT is also determined by L !!!

fT6


Optimum design Miller for high speed OTA - 3

If VGST = 0.2 V, vsat takes over for L < 65 nm (If 0.5 V for L < 0.15 µm)

fT =1L 1 + 2.8 104 L / VGST

1.35

L in cmfT in MHz

Substitution for fT yields

GBW =α β γ (1 + 1/ β)

fT6

GBW is not determined by CL, only by fTfT is determined by L (and VGST) !!!

2πCGSfT =

gm


Maximum GBW versus channel length L

VGS-VT ≈ 0.2 VGBWGHz

0.1

1

10

1 µm100 nm10 nm L

K’

vsat α ≈ 2β ≈ 3γ ≈ 2or 16 x

GBW ≈fT6

16


Design optimization for high speed Miller OTA

• Choose α β γ

• Find minimum fT6 for specified GBW• Choose maximum channel length L6 (max. gain)

for a chosen VGS6-VT

• W6 is calculated from CL ,

and determines IDS6• Cc is calculated from CL through α

• gm1 and IDS1 are calculated from Cc

• Noise is determined by gm1 or Cc


Design Ex. for GBW = 0.4 GHz & CL = 5 pF

• Choose α β γ 2 3 2 • Minimum fT6 for GBW = 0.4 GHz fT6 = 6.4 GHz• Maximum channel length L6 L6 = 0.5 µm

for a chosen VGS6-VT = 0.2 V• L6 is taken to be the minimum L• W6 is calculated from CL , W6 = 417 µm

and determines IDS6 (K’n = 70 µA/V2) IDS6 = 2.3 mAand determines Cn1 (k = 2 fF/µm) Cn1 = 0.83 pF

• Cc is calculated from CL through α Cc = 2.5 pF • gm1 and IDS1 are calculated from Cc IDS1 = 0.63 mA


Optimum design Miller for low speed OTA

GBW =α β γ (1 + 1/ β)

fT6

GBW is not determined by CL, only by fTfT is determined by L and i !!!

=fTfTH

i (1 - e - i )

fTH = 2 µ kT/q2π L2

≈ i for small i


Design optimization for low speed Miller OTA

• Choose α β γ

• Find minimum fT6 for specified GBW• Choose channel length L6 (max. gain), which gives fTH6

• Calculate i6• W6 is calculated from CL ,

and determines IDST6 and IDS6

• Cc is calculated from CL through α

• gm1 and IDS1 are calculated from Cc

• Noise is determined by gm1 or Cc


Design Ex. for GBW = 1 MHz & CL = 5 pF

• Choose α β γ 2 3 2 • Minimum fT6 for GBW = 1 MHz fT6 = 16 MHz• Maximum channel length L6 L6 = 0.5 µm

gives fTH6 fTH6 = 2 GHz• Inversion coefficient i is i = 0.008 • W6 is calculated from CL , W6 = 417 µm

and determines IDST6 (K’n = 70 µA/V2) IDST6 = 0.33 mAand determines IDS6 IDS6 = 2.7 µA

and determines Cn1 (k = 2 fF/µm) Cn1 = 0.83 pF• Cc is calculated from CL through α Cc = 2.5 pF • gm1 and IDS1 are calculated from Cc IDS1 = 1.6 µA


Table of contents




• Other : SR, Output Impedance, Noise, ...


Miller CMOS OTA: Specifications 1

1. Introductory analysis1.1 DC currents and voltages on all nodes1.2 Small-signal parameters of all transistors

2. DC analysis2.1 Common-mode input voltage range vs supply Voltage2.2 Output voltage range vs supply Voltage2.3 Maximum output current (sink and source)



3. AC and transient analysis3.1 AC resistance and capacitance on all nodes3.2 Gain versus frequency : GBW, …3.3 Gainbandwidth versus biasing current3.4 Slew rate versus load capacitance3.5 Output voltage range versus frequency3.6 Settling time3.7 Input impedance vs frequency (open & closed loop)3.8 Output impedance vs frequency (open & closed loop)



4. Specifications related to offset and noise4.1 Offset voltage versus common-mode input Voltage 4.2 CMRR versus frequency4.3 Input bias current and offset4.4 Equivalent input noise voltage versus frequency4.5 Equivalent input noise current versus frequency4.6 Noise optimization for capacitive/inductive sources4.7 PSRR versus frequency4.8 Distortion



5. Other second-order effects5.1 Stability for inductive loads5.2 Switching the biasing transistors5.3 Switching or ramping the supply voltages5.4 Different supply voltages, temperatures, ...


M C O : Other specifications

o Common-mode input voltage range

o Output voltage range

o Slew Rate

o Output impedance

o Noise


Miller CMOS OTA

12

34

5

VDD

VSS

vOUT

CL

M1 M2

M3 M4

M5

M6

M7

+- Cc

1 : B

vv

GBW = 1 MHzCL = 10 pFRL = 10 kΩ

RL

gm1 = 7.5 µSIDS1 = 1 µA

gm6 = 246 µSIDS6 = 25 µA

Cc = 1 pF

go24 = 0.03 µS


Miller CMOS OTA : CM Input Voltage Range

0 1V 2V 3V 4V

-2V

0V

-3V

1V

-1V

2V

3V

VDD = |VSS|

VDD

VSS VICMmin

VICMmax

VICM

VICM

±2.5V


Miller CMOS OTA : Output Voltage Range

0 1V 2V 3V 4V

-2V

0V

-3V

1V

-1V

2V

3V

VDD = |VSS|

VDD

VSS VOUTmin

VOUTmax

VOUT

VOUT

±2.5V

Rail-to-rail output if no RL

4

VDD

vOUT

CL

M5

RL


Miller CMOS OTA : Slew Rate - 1

12

34

5

VDD

VSS

vOUT

CL

M1

M3 M4

M5

M6

M7

+

- Cc

1 : B

v

v

RL

Switch input :

> 1

-v > 0

IB1

IB1

∆VOUT

Cc

SR = ∆t

IB1

SR =



vOUT

vIN

vOUT

vIN

t t

t t

VOUTmax

4TmaxVOUTmax ≈

4 fmax

SR

SRSR

SR

SR≈ 4

VOUTmaxfmax

SR

SR



0 0.2M 0.4M 1MHz0.6M

VOUTmax ≈4 fmax

SR

0.8M

0.5

1

1.5

2

0

VOUTVp

f

SR = 2.2 V/µs


Design for GBW or SR ?

IDS1gm1

SR GBW

= 4πIDS1

gm1=

2VGS1-VT

IDS1

gm1=

qnkT

ICE1

gm1=

qkT

ICE1gm1

= q

kT(1 + gm1RE)

≈ 0.1 ... 0.3 V for MOST (si)

≈ 30 … 50 mV for MOST (wi)

≈ 26 mV for Bipolar trans.

≈ ... 0.5 V with RE

x10

Solomon, JSSC Dec 74, 314-332


High SR by gm reduction

Ref. Schmoock, JSSC Dec.75, 407-411

VDD

VSS

vOUT

CL

M1 M2

M5 M6

v+v-

IB IB

n : 11 : n

M3 M4

2π GBW

SR

= x (n+1)


External vs internal Slew Rate

1

4

VDD

VSS

vOUT

CL

M4

M5

M6

Cc

IBIDS5 Cc

IB

SRint =

IDS5

CLSRext = is larger !

gm6

Ccgm1

= 4 CL = IDS5

IDS1IDS5

CL≈ 2

2IDS1

Cc


Slew Rate and settling

tSlew

tTOT = tSlew + t0.1

vOUT

vIN

t

tSR

t0.1

0.1 % tSlew =

t0.1 =

SRVOUTVOUT

ln (1000) ≈ 7

2π BW7


Miller CMOS OTA Output Impedance

12

34

5

VDD

VSS

ZOUT

CL

M1 M2

M3 M4

M5

M6

M7

+- Cc

1 : B

vv

GBW = 1 MHzCL = 10 pF

RL

gm1 = 7.5 µSIDS1 = 1 µA

gm6 = 246 µSIDS6 = 25 µA

Cc = 1 pF

go24 = 0.03 µS

ZOUTCL


Miller CMOS OTA : Output impedance ZOUT

f

ZOUT

1/gm6 ≈ 4 kΩ

1/go56 ≈ 0.5 MΩ

GBWfzfd

Av20

Av10Av

closed loop

fz =2πCc

go24

fz ≈ 4.8 kHz

with CL

fnd

open loop


Miller CMOS OTA : Noise density 1

go24 Cn1

gm1vin

gLo6

1 4

Cc

gm6vn1

vOUT

vneq

vin vn1

dvin12

dvin12 dvin2

2

dvin22

≈ 4kT df4/3gm1

≈ 4kT df2/3gm6

CL


Miller CMOS OTA : Noise density 2

fndGBW

dvin12

f

dvneq22

dvneq22 =

dveq2

dvin22

|Av1|2

Av10 = go24

gm1Av102

fz

fz =2πCc

go24

Dominant on linear frequency scale !

4kT df2/3gm6


Miller CMOS OTA : Integrated Noise

GBWπ2

GBWn

f

A ∫vnieq2 =

dvnieq2

1 + (f/ GBW) 20

∞

GBWvnieq

2 = 4kT GBW π2=

=kTCcCc = 1pF vRs= 74 µVRMS

1

4/3gm1

vnieq2 4

3

∫ dx1 + x 2

0

∞π2=


Noise density vs integrated noise

BW BWn

f

A

∫vni2 =

dvni2

1 + (f/ BW) 20

∞=

4kT3Cc

dvni2 = 4kT df

Noise density (V2/Hz) ~ 1/gm (or RS)

Integrated noise (VRMS) ~ 1/Cc

4/3gm


CMOS Miller OTA layout

IN+IN-

IB

VDD

VSS

OUT

GBW = 1 MHz

CL = 10 pF

SR = 2.2 V/µs

VDD = 5 V

ITOT = 27 µA

370 MHzpF/mA


Miller CMOS OTA : Exercise

GBW = 50 MHz for CL = 2 pF : use min. IDS6 !

Techno: Lmin = 0.5 µm; K’n = 50 µA/V2 & K’

p = 25 µA/V2

CGS = kW (= CoxWL) and k = 2 fF/ µm

VGS -VT = 0.2 V

Find gm6 IDS6 W6 Cn1 = CGS6 Cc gm1 IDS1 dvineq

2 vinRMS


Conclusion : Table of contents





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