€¦ · Table of Contents CHAPTER TITLE PAGE 3 BIOS SETUP MENUS 3.1 Introduction 3-1 3.2 Software...

© 1994 XYCOM, INC.

Printed in the United States of America Part Number 74688-002A

XVME-678/688 VMEbus PC/AT Processor Module PIN 74688-002A

XYCOM 750 North Maple Road Saline, Michigan 48176-1292 734-429-4971 (phone) 734-429-1010 (fax)

XYCOM REVISION RECORD

Revision Description Date

A Manual Released 7/94

Trademark Information

Brand or product names are registered trademarks of their respective owners.

Copyright Information

This document is copyrighted by Xycom Incorporated (Xycom) and shall not be reproduced or copied without expressed written authorization from Xycom.

The information contained within this document is subject to change without notice. Xycom does not guarantee the accuracy of the information and makes no commitment toward keeping it up to date.

Part Number: 74688-002A

Address comments concerning this manual to:

xycom Technical Publications Department 750 North Maple Road Saline, Michigan 48176

TABLE OF CONTENTS

CHAPTER TITLE PAGE

1 INTRODUCTION

1.1 Product Features 1-1 1.2 Manual Structure 1-2 1.3 XVME-678/688 Board Operational Description 1-3 1.3.1 80386SX or 486SLC/e Central Processing Unit (CPU) 1-4 1.3.2 DRAM 1-4 1.3.3 Floppy Drive Controller 1-4 1.3.4 Hard Drive Controller 1-4 1.3.5 Graphics Controller 1-5 1.3.6 110 Ports 1-5 1.3.7 VMEbus Master Interface 1-5 1.3.8 Keyboard Controller 1-5 1.4 Specifications 1-6

2 INSTALLATION

2.1 Introduction 2-1 2.2 Jumpers 2-2 2.2.1 VGA Jumpers (J3, J5) 2-4 2.2.2 EPROM/Flash Jumper (J1) 2-4 2.2.3 IRQ12 Jumper (J8) 2-4 2.2.4 Battery and Test Jumpers (J2, J4) 2-5 2.3 Switch Settings 2-5 2.4 Connectors 2-6 2.4.1 VMEbus PI Connector 2-8 2.4.2 VMEbus P2 Connector 2-9 2.4.3 Floppy Drive Connector (P4) 2-10 2.4.4 IDE Hard Drive Connector (P5) 2-11 2.4.5 Keyboard Connector (P6) 2-12 2.4.6 Auxiliary Connector (P7) 2-12 2.4.7 COM2 Serial Port Connector (P8) 2-12 2.4.8 COM 1 Serial Port Connector (P9) 2-13 2.4.9 VGA Connector (PlO) 2-13 2.4.10 Parallel Port Connector (JKl) 2-14 2.4.11 Speaker Connector (17) 2-14 2.4.12 PXTI Connector 2-15 2.4.13 PATI Connector 2-16 2.5 Installing the XVME-678/688 into a Backplane 2-17 2.6 Adding Extended BIOS 2-20 2.7 Installing DRAM 2-22 2.8 Installing an Optional Intel 80387SX Math Co-processor 2-25

Table of Contents

CHAPTER TITLE PAGE

3 BIOS SETUP MENUS

3.1 Introduction 3-1 3.2 Software Control and Initial Setup 3-1 3.3 BIOS Main Menu 3-2 3.3.1 BIOS Setup Menu 3-3 3.3.2 VMEbus Master Setup Menu 3-8 3.3.3 Solid State Disk Setup Menu 3-11 3.3.4 Extended BIOS Features Menu 3-13 3.3.5 System Information Menu 3-16 3.3.6 Diagnostics Menu 3-16 3.3.7 Format Fixed Disk Menu 3-23

4 PROGRAMMING

4.1 Introduction 4-1 4.2 XVME-678/688 Memory Maps 4-1 4.2.1 DRAM 4-7 4.2.2 EPROM 4-8 4.3 Accessing VMEbus Memory Space Using the

Real Mode Window 4-9 4.3.1 EPROM 4-9 4.3.2 VMEbus lACK Space 4-9 4.3.3 VMEbus Short 110 Space 4-10 4.3.4 VMEbus Standard Address Space 4-11 4.4 VMEbus Master Interface 4-12 4.5 Shadow RAM Option 4-14 4.6 110 Port Addresses 4-15 4.6.1 Control Register 1 4-17 4.6.2 Auxiliary Interrupt 4-18 4.6.3 Status Register 1 4-18 4.6.4 Status Register 2 4-19 4.6.5 VMEbus HI Address 4-19 4.6.6 Control Register 2 4-19 4.6.7 Control Register 3 4-20 4.6.8 Control Register 4 4-20 4.6.9 Control Register 5 4-21 4.6.10 Control Register 6 4-21 4.7 Interrupts 4-22 4.7.1 Auxiliary Maskable Interrupts (AMIs) 4-22 4.8 Byte-Swapping 4-26 4.8.1 Byte-Ordering Schemes 4-26 4.8.2 Address Consistency 4-27

ii

CHAPTER

4

5

4.8.3 4.9 4.10

5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.3 5.3.1 5.3.2 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.5 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.6 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6

TITLE

PROGRAMMING (continued)

Numeric Consistency System Resource Function CMOS RAM

XVME BIOS FUNCTIONS

XVME BIOS Functions Miscelleneous Functions Identify XVME Model Get Real Mode Window Physical Segment Get LED Configuration Set LED Configuration Get Flash BIOS Write Configuration Set Flash BIOS Write Configuration Real Mode Window (RMW) Functions Get Real Mode Window Configuration Set Real Mode Window Configuration

XVME-678/688 Manual July 1994

PAGE

4-28 4-30 4-31

5-1 5-4 5-4 5-5 5-6 5-7 5-8 5-9

Auxiliary Non-maskable Interrupt (ANMI) Functions Get ANMI Group Configuration

5-10 5-10 5-11 5-12 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-18 5-19 5-21 5-22 5-23 5-24 5-25 5-25 5-26 5-27 5-28 5-30 5-32

Set ANMI Group Configuration Get ANMI Mask Set ANMI Mask Get ANMI Status Clear ANMI VMEbus Master Functions Get VMEbus Master Configuration Set VMEbus Master Configuration Get VMEbus Ownership Configuration Set VMEbus Ownership Configuration Get VMEbus Ownership Status Wait for VMEbus Ownership to be Granted VMEbus Interrupt Handler Functions Get VMEbus Interrupt Group Configuration Set VMEbus Interrupt Group Configuration Get VMEbus Interrupt Mask Set VMEbus Interrupt Mask EnablelDisable Specific VMEbus Interrupts Get VMEbus Interrupt Status

iii

Table of Contents

CHAPTER

5

A B C D

5.6.7 5.6.8 5.7 5.7.1

FIGURE

1-1

2-1 2-2 2-3 2-4 2-5

3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13

4-1

iv

TITLE PAGE

XVME BIOS FUNCTIONS (continued)

Determine Highest Priority Pending VMEbus Interrupt 5-33 Acknowledge VMEbus Interrupt Via Real Mode Window 5-34 VMEbus System Resource Functions 5-35 Get System Resource Flag 5-35

APPENDICES

VMEbus CONNECTOR/PIN DESCRIPTIONS QUICK REFERENCE GUIDE EXTENDED VGA MODES BLOCK DIAGRAM, ASSEMBLY DRAWING, AND SCHEMATICS

LIST OF FIGURES

TITLE PAGE

XVME-678/688 Board Block Diagram 1-3

XVME-678/688 Jumper and Switch Locations 2-3 XVME-678/688 Connector Locations 2-7 XVME-678/688 Board Front Panel 2-19 DRAM Installation 2-24 80387SX Math Co-processor Installation 2-25

Main Setup Menu 3-2 BIOS Setup Menu 3-3 VMEbus Master Setup Menu 3-8 Solid State Disk Setup Menu 3-11 Extended BIOS Features Menu 3-13 System Information Menu 3-16 Advanced Diagnostics Menu 3-17 Advanced Diagnostics Test Menu 3-18 Diskette Drive Menu 3-20 Fixed Disk Menu 3-21 Parallel Port Test Menu 3-22 Serial and Parallel Loopback Connections 3-22 Format Fixed Disk Menu 3-23

1 Mbyte Memory Map (as seen by the CPU) 4-2

FIGURE

4-2 4-3 4-4 4-5 4-6 4-7 4-9 4-10 4-11 4-12 4-13 4-14

TABLE

1-1

2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16

3-1

4-1 4-2 4-3


LIST OF FIGURES (continued)

TITLE PAGE

2 Mbyte Memory Map (as seen by the CPU) 4-3 4 Mbyte Memory Map (as seen by the CPU) 4-4 10 Mbyte Memory Map (as seen by the CPU) 4-5 16 Mbyte Memory Map (as seen by the CPU) 4-6 EPROM Memory Map 4-8 BERR Mapped Onto IOCHCK* 4-12 BERR, SYSFAIL, and ABORT Switch Mapped on IRQI04-24 Auxiliary Non-maskable Interrupt Structure 4-25 Byte-Ordering Schemes· 4-26 Maintaining Address Consistency 4-27 Maintaining Numeric Consistency 4-28 Reset Structure 4-30

LIST OF TABLES

TITLE PAGE

XVME-678/688 Module Specifications 1-6

XVME-678/688 Jumper Options 2-4 XVME-678/688 SWI Switch Settings 2-5 PI Pinouts 2-8 P2 Pinouts 2-9 Floppy Drive Connector 2-10 IDE Hard Drive Connector 2-11 Keyboard Connector 2-12 Auxiliary Connector 2-12 COM2 Serial Port Connector 2-12 COM1 Serial Port Connector 2-13 VGA Connector 2-13 Parallel Port Connector 2-14 Speaker Connector 2-14 PXT 1 Pinouts 2-15 PAT 1 Pinouts 2-16 Bank and SIMM Size 2-22

Error Codes 3-26

110 Address Map 4-15 110 Addresses Unique to the XVME-678/688 4-16 CMOS RAM Address Map 4-32

v

Chapter 1 - INTRODUCTION

1.1 PRODUCT FEATURES

The XVME-678/688 VMEbus PCI A T processor modules are designed to combine the high-performance and ruggedized packaging of the VMEbus with the broad application software base of the IBM PCI AT standard. These 6U, double-high modules require a single VMEbus slot, are fully AT -compatible, and support all standard PCI AT software.

The XVME-688 features a low-power CMOS design with an 80386SX processor running at 25 MHz. The XVME-678 features a Cyrix 486SLC/e running at 25 MHz. The 486SLC/e provides an internal 1 Kbyte cache, a 486SX-compatible instruction set, and a 80386SX pin out.

Both modules offer the following features:

• 25 MHz 80386SX microprocessor (XVME-688) or 25 MHz 486SLC/e (XVME-678) • 0, 1, or 4 Mbytes of DRAM

-SIMM sockets for memory expansion up to 16 Mbytes DRAM -Zero wait state page interleaved DRAM accesses with 60 nsec DRAMs

• Shadow RAM option for System and VGA BIOS • Super VGA graphics controller with 512 Kbytes of DRAM • Floppy disk controller • High-performance IDE hard disk controller • A socket for an 80387SX math co-processor • VMEbus master interface • VMEbus interrupt handler • Programmable interrupt enable • Programmable bus request and bus grant levels • VMEbus slot 1 functions • Real mode window, allowing VMEbus Short I/O and Standard address space locations to be

accessed while processor is in real mode • Two RS-232C serial communication ports • Centronics-compatible parallel port • PS/2-compatible keyboard port • PS/2 AUX port for PS/2-compatible mouse or trackball • VMEbus SYSFAIL switch

1-1

Chapter 1 - Introduction

1.2 MANUAL STRUCTURE

The chapters in this manual are organized in the following manner:

Chapter One Module Description: functional and environmental specifications, module structure, VMEbus compliance information, and blo.ck diagram

Chapter Two Installation: system requirements, jumper and switch settings, connector pinouts, and procedures for installing the XVME-678/688 into a backplane, installing SIMM memory onto the XVME-678/688, adding extended BIOS. and installing the optional math coprocessor

Chapter Three BIOS Setup Menus: descriptions of menu-driven BIOS utilities

Chapter Four Programming: information required to program the module, including memory maps, I/O maps, and interrupt information

Appendix A VMEbus Connector/Pin Description: VMEbus signals, connectors, pin numbers and their descriptions

Appendix B Quick Reference Guide: default jumper settings, tables, and graphs

Appendix C Extended VGA Modes: information about extended video modes

Appendix D Block Diagrams, Assembly Drawings, and Schematics

1-2

XVME-6781688 Manual July 1994

1.3 XVME-678/688 BOARD OPERATIONAL DESCRIPTION

Figure 1-1 shows the logical arrangement of the XVME-678/688 board.

VGA CONTROLLER

BUFFERS

SCATSX

DRAM

ATbus

DRAMSIMM SOCKETS (4)

t..-c ---'{ --~----,

80386SXI 486SLC/e

PROCESSOR

80387SX MATH CO-PROCESSOR

FLOPPY IDE

VMEbus MASTER

INTERFACE

Figure 1-1. XVME-678/688 Board Block Diagram

1-3


1.3.1 80386SX or 486SLC/e Central Processing Unit (CPU)

The XVME-688 uses an 80386SX microprocessor to provide operational capabilities. The XVME-678 uses a Cyrix 486SLC/e that provides a 486SX-compatible instruction set with a 1 Kbyte internal cache. These 25 MHz CPUs can access up to 16 Mbytes of DRAM.

1.3.2 ])1lAJ\I

The XVME-678/688 uses Dynamic Random Access Memory (DRAM) configured in a page interleave mode with 0 wait-state operation. The 1, 4, and 16 Mbyte versions of the XVME-678/688 are two-way interleaved, while the 2 and 10 Mbyte versions have no interleaving.

The XVME-678/688 comes factory-configured with 0, 1, or 4 Mbytes of DRAM. Additional DRAM can be installed in 2, 10, and 16 Mbyte configurations. Refer to section 2.7 for more information.

1.3.3 Floppy])rive Controller

The XVME-678/688 floppy drive controller can support up to two PC/AT-compatible floppy drives. These drives can be any combination of 360 Kbytes, 720 Kbytes, 1.2 Mbytes, and 1.44 Mbytes.

1.3.4 Hard ])rive Controller

The XVME-678/688 uses the IDE interface for the hard drive controller. This 16-bit interface provides complete hardware-level compatibility to the IBM PC/AT hard drive controller. Two drives can be connected to the interface by daisy chaining the ribbon cable and setting one drive as the master and one as the slave. (This requires setting jumpers on the drive. Consult your drive manual for more information. )

1-4

CAUTION The IDE ribbon cable should not exceed 18 inches. Otherwise, errors may occur and data may be corrupted.

Most IDE drives should never be low-level formatted. Check your IDE drive manual for formatting procedures.

1.3.5 Graphics Controller


The XVME-678/688 VGA graphics controller supports all IBM VGA, EGA, CGA, and MDA modes to the register level. The VGA adapter supports Super VGA up to 1024 x 768 with 16 colors. The VGA BIOS is 8 bits. Shadowing the BIOS through the BIOS Setup Menu (see Chapter 3 for more information) significantly increases system performance.

The VGA controller supports IBM modes 0-13H (hex) as well as other modes. See Appendix C for a complete list of supported modes.

1.3.6 I/O Ports

The XVME-678/688 has two RS-232C serial ports and one IBM PC/AT style Centronics-compatible parallel port. These ports are controlled in the BIOS Setup Menu which allows the ports to be disabled or enabled from software. Interrupts are enabled or disabled by setting bits in 110 registers (refer to Chapter 5).

1.3.7 VMEbus Master Interface

The VMEbus master interface allows the 80386SX CPU to become a master or interrupt handler on the VMEbus. The XVME-678/688 master interface is invoked whenever the 80386SX accesses the VMEbus Standard, Short 110, or lACK address spaces. All accesses to the VMEbus are through the Real Mode Window.

1. 3.8 Keyboard Controller

The XVME-678/688 keyboard controller is PS/2 compatible and supports not only the PS/2 keyboard, but also provides an auxiliary input port for a PS/2-compatible mouse, trackball, etc.

1-5


1.4 SPECIFICATIONS

Table 1-1 contains the functional specifications for the XVME-678/688.

1-6

Table 1-1. XVME-678/688 Module Specifications

SPECIFICATION

Mechanical Processor

XVME-688 XVME-678

Processor Speed

AT-bus Speed

Math Co-processor (optional)

Graphics Controller

Floppy Disk Interface

Hard Disk Interface

PS/2 A UX Port

Serial Ports (2)

Parallel Port

Power Requirements +5 V @ 1.9 A typ., 2.7 A max.

SIMM Memory Configuration SIMM Sites Memory Configurations Memory Accepted Memory Speed Required

DESCRIPTION

80386SX· 486SLC/e

25 MHz

10 or 8.33 MHz

80387SX

VGA analog output Max. resolution: 1024 x 768, 16 colors

PC/AT-compatible: supports two drives-360 Kbyte, 720 Kbyte, 1.2 Mbyte, and 1.44 Mbyte capacities

IDE controller: supports two drives

Compatible with PS/2 mouse

RS-232C

Centronics compatible

+ 12 V @ 2 rnA max.

-12 V @ 1 rnA max.

4 Up to 16* Mbytes 256Kx9, IMx9, or 4Mx9 60 nsec, 0 wait states 80 nsec, 1 wait state

* 0, 1, and 4 lv1bytes of DRAM are available as factory-configured options.


Table 1-1. XVME-678/688 Module Specifications (continued)

SPECIFICATION

Environmental

Temperature Operating Non-operating

Humidity

Altitude Operating Non-operating

Vibration Operating

Non-operating

Shock Operating

Non-operating

VMEbus

DESCRIPTION

0° to 65° C (32° to 149°F) -40° to 85°C (-40° to 185°F)

5 to 95 % RH, non-condensing

Sea level to 10,000 ft. (3048 m) Sea level to 50,000 ft. (15240 m)

5 to 2000 Hz .015" peak to peak displacement 2.5 g max acceleration .030" peak to peak displacement 5.0 g max acceleration

30 g peak acceleration, 11 msec duration 50 g peak acceleration, 11 msec duration

Complies with VMEbus Specification IEEE 1014 A24/AI6:DI6/D08(EO) Master R(0-3) Bus Requester Interrupt Handler IH(I)-IH(7) SYSCLK and SYSRESET Driver SGL Arbiter ROR Option Form Factor - Double (6U), 233.35 mm x 160 mm (9.2" x 6.3")

1-7

Chapter 2 - INSTALLATION

2.1 INTRODUCTION

This chapter provides the information necessary to configure the XVME-678/688 VMEbus PC/AT Processor Module. It also provides information on installing the XVME-678/688 into a backplane, adding extended BIOS to the XVME-678/688, adding DRAM memory in SIMM sockets, and installing an optional math co-processor.

WARNING If the battery is disabled in your system, please do the following: Upon enabling, your module must be powered up for a minimum of 30 seconds. Failure to follow this procedure may result in premature battery failure.

WARNING XVME-678/688 CPU modules with functional revision levels of 4.1 or higher (functional revision levels and part numbers are located on a label on the PI connector) feature a 16-bit compatible PC/104 expansion site. This PC/104 expansion site requires a new version of the XVME-956 Modular I/O Carrier Module. If the CPU module's functional revision level is 4.1 or higher, use the XVME-956/12 (part number 70956-012). If the functional revision level is less than 4.1, use the XVME-956/2 (part number 70956-002). Do not use the XVME-956/2 on a CPU module with functional revision levels of 4.1 or higher as this may cause damage to both modules.

In addition, the XVME-956/402 SCSI Expansion Module has been updated. The XVME-956/412 must be used with XVME-678/688 modules that have a functional revision level of 4.1 or higher. Use of the XVME-956/402 with the new CPU modules will damage the SCSI Expansion Module and the CPU.

Please contact Xycom's Customer Service Department at 1-800-289-9266 for assistance.

2-1

Chapter 2 - Installation

NOTE The XVME-678/688 module obtains power from both the VMEbus PI and P2 backplanes. However, only PI is necessary for proper operation.

2.2 JUMPERS

All of the jumpers on the XVME-678/688 are shipped in the correct positions. The unit will function as required with no modifications.

NOTE Jumpers only need to be modified when disabling VGA or replacing the BIOS EPROM with Flash RAM devices.

Jumper locations on the XVME-678/688 module are shown in Figure 2-1. The jumpers are described in Table 2-1.

2-2

~J3

SA

~J2 SA

~J1


Figure 2-1. XVME-678/688 Jumper and Switch Locations

2-3


Table 2-1. XVME-678/688 Jumper Options

Jwnper Position Function Section Reference

11 A.t Sets EPROM or Flash RAM to non-writable + 5V 2.2.2 B Sets Flash RAM to + 12V

12 A.t Enables battery 2.2.4 B Disables battery

13 A.t IRQ9 is driven by VGA controller 2.2.1 B IRQ9 is not driven by the VGA controller

J4 A.t Test jumper that supplies V cc to OSC 2.2.4 B Test jumper that disconnects V cc from OSC

J5 A.t Enables VGA 2.2.1 B Disables VGA

J8 A.t IRQ12 driven for auxiliary port 2.2.3 B IRQ12 not driven for auxiliary port

.t indicates default settings

2.2.1 VGA Jwnpers (J3, J5)

Jumper J5 enables the VGA BIOS and Xycom Setup when positioned to A (default) or disables the VGA BIOS and XYCOM Setup when positioned to B.

Jumper 13 should be set to A (default) for IRQ9 to be driven by the VGA, or to B for IRQ9 not to be driven by the VGA.

2.2.2 EPROM/Flash Jwnper (Jl)

Jumper 11 sets EPROM and Flash RAM devices to a non-writable +5V when positioned to A (default). When positioned to B, 11 sets Flash RAM devices to + 12V.

2.2.3 IRQ12 Jwnper (J8)

Jumper J8 allows the PS/2 auxiliary port to drive IRQ12 when positioned to A (default). When positioned to B, the PS/2 port does not drive IRQI2.

2-4


2.2.4 Battery and Test Jwnpers (J2, J4)

Jumper J2 enables the XVME-678/688 on-board battery when positioned to A (default), and disables the battery when positioned to B. This jumper should remain positioned to A. To disable the battery, position switch 6 of SWI to open (see Section 2.3). See WARNING in Section 2.1 regarding a disabled battery.

Jumper J4 is a test jumper that supplies Vcc to OSC. This jumper must always remain positioned to A.

2.3 SWITCH SETTINGS

The XVME-678/688 has one eight-position switch, SWI. This switch allows critical options, which are not software accessible, to be enabled in a common area. Figure 2-1 on page 2-2 shows the switch location. The settings and their functions are shown in the table below.

Table 2-2. XVME-678/688 SWI Switch Settings

Position Setting Function

1 Open VME SYSRESET* is not driven on the VMEbus at power-up. Closedvi' VME SYSRESET* is driven on the VMEbus at power-up.

2 Open VME SYSRESET* is not caused by the toggle switch. Closedvi' VME SYSRESET* is caused by the toggle switch.

3 Openvi' VME SYSFAIL is not driven on the VMEbus. Closed VME SYSFAIL is driven on the VMEbus.

4 Open VME system resource function is disabled. Closedvi' VME system resource function is enabled.

5 Openvi' Not user configurable. Must remain open.

6 Openvi' Disables the battery. Closed Enables the battery.

7 Openvi' Enables the keyboard. Closed Disables the keyboard.

8 Openvi' Enables color video. Closed Enables monochrome video.

vi' indicates default settings

2-5


NOTE The battery enable switch (SW6) is shipped in the OPEN position. Close this switch to allow the CMOS configuration to be retained on power-down.

2.4 CONNECTORS

The XVME-678/688 has 12 connectors:

• IDE hard drive • Floppy drive • Parallel port • COM1 and COM2 serial ports • PS/2 A UX port • VGA • Keyboard • Speaker • VMEbus P 1 and P2 • PC/l 04-compatible expansion site

The connectors must be clean, dry, and undamaged at the time of installation. Figure 2-2 on the following page shows the location of the connectors on the board.

NOTE All connector locations are labeled on the circuit card.

2-6

P10 (VGA)

1111 1111 1111 1111

1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111

1111 II

C1

tE:::E::l

JK1 (PARALLEL

PRINTER PORT)

PXT1 (XT CONNECTOR)

mm

PAT1 (AT CONNECTOR)

tE:::E::l

P9 (COM 1

SERIAL PORT)

PIN 1

tE:::E::l

P8 (COM 2

SERIAL PORT)


P7 (AUXILIARY

PORT)

P6 (KEYBOARD

PORT)

SA

tE:::E::l J 7 (SPEAKER)

r--l r--l r--l r-;:J

L-.....J --l L-.....J L.....J

~

Figure 2-2. XVME-678/688 Connector Locations

2-7


2.4.1 VMEbus PI Connector

VMEbus PI is a 96-pin DIN connector.

Table 2-3. PI Pinouts

Pin Row A Signal Row B Signal Row C Signal

1 DO BBUSY D08 2 DOl BCLR* D09 3 D02 ACFAIL* D10 4 D03 BGOIN* Dll 5 D04 BGOOUT* D12 6 D05 BGlIN* D13 7 D06 BG10UT* D14 8 D07 BG2IN* D15 9 GND BG20UT* GND 10 SYSCLK BG3IN* SYSFAIL* 11 GND BG30UT* BERR* 12 DS1* BRO* SYSRESET* 13 DSO* BRl* LWORD* 14 WRITE * BR2* AM5 15 GND BR3* A23 16 DTACK* AMO A22 17 GND AMI A21 18 AS* AM2 A20 19 GND AM3 A19 20 IACK* GND A18 21 IACKIN* SERCLK A17 22 IACKOUT* SERDAT* A16 23 AM4 GND A15 24 A07 IRQ7* A14 25 A06 IRQ6* A13 26 A05 IRQ5* A12 27 A04 IRQ4* All 28 A03 IRQ3* A10 29 A02 IRQ2* A09 30 AOI IRQ1* A08 31 -12V +5V STDBY +12V 32 +5V +5V +5V

2-8

2.4.2 VMEbus P2 Connector

VMEbus P2 is a 96-pin DIN connector.

Table 2-4. P2 Pinouts

Pin Row A Signal Row B Signal

1 N/C +5V 2 N/C GND 3 N/C N/C 4 N/C N/C 5 N/C N/C 6 N/C N/C 7 N/C N/C 8 N/C N/C 9 N/C N/C 10 N/C N/C 11 N/C N/C 12 N/C GND 13 N/C +5V 14 N/C N/C 15 N/C N/C 16 N/C N/C 17 N/C N/C 18 N/C N/C 19 N/C N/C 20 N/C N/C 21 N/C N/C 22 N/C GND 23 N/C N/C 24 N/C N/C 25 N/C N/C 26 N/C N/C 27 N/C N/C 28 N/C N/C 29 N/C N/C 30 N/C N/C 31 N/C GND 32 N/C +5V


Row C Signal

N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C

2-9


2.4.3 Floppy Drive Connector (P4)

The floppy drive connector is a 34-pin header located on the board near P8, the COM2 serial port connector. It is the interface and control connection for up to two floppy drives.

Table 2-5. Floppy Drive Connector

Pin Signal Pin Signal

1 GND 18 FDIRC* 2 FRWC* 19 GND 3 GND 20 FSTEP* 4 N/C 21 GND 5 KEY 22 FWD* 6 N/C 23 GND 7 GND 24 FWE* 8 IDX* 25 GND 9 GND 26 FTKO* 10 Mal 27 GND 11 GND 28 FWP* 12 FDS2 29 GND 13 GND 30 FRDD* 14 FDS1 31 GND 15 GND 32 FHS* 16 M02 33 GND 17 GND 34 DCHG*

2-10

2.4.4 IDE Hard Drive Connector (P5)


The IDE hard drive connector is a 40-pin header located near JK1, the parallel port. It is the control connector for any hard drive(s) interfaced with the XVME-678/688. The XVME-678/688 can control up to two hard drives from this connector.

Table 2-6. IDE Hard Drive Connector


1 RESET* 21 N/C 2 GND 22 GND 3 ID87 23 IOW* 4 SD8 24 GND 5 SD6 25 IOR* 6 SD9 26 GND 7 SD5 27 N/C 8 SDlO 28 ALE 9 SD4 29 N/C 10 SD11 30 GND 11 SD3 31 ATIRQ14 12 SD12 32 ATIOCS16* 13 SD2 33 SAl 14 SD13 34 N/C 15 SD1 35 SAO 16 SD14 36 SA2 17 SDO 37 HCSO 18 SD15 38 HCS1 19 GND 39 N/C 20 N/C 40 GND

2-11


2.4.5 Keyboard Connector (P6)

P6, a 6-pin MINI DIN connector, serves as the interface point for a keyboard. An interface cable is shipped with the XVME-678/688 so a standard PC/AT keyboard can be used.

Table 2-7. Keyboard Connector

Pin Signal

1 DATA 2 NC 3 GND 4 +5V 5 CLK 6 N/C

2.4.6 Auxiliary Connector (P7)

P7 is a PS/2-compatible, 6-pin MINI DIN connector. This port accepts a PS/2-compatible mouse, track ball, etc.

Table 2-8. Auxiliary Connector

Pin Signal

1 DATA 2 NC 3 GND 4 +5V 5 CLK 6 N/C

2.4.7 COM2 Serial Port Connector (P8)

The 9-pin D subminiature COM2 serial port connector is located on the module's front panel.

Table 2-9. COM2 Serial Port Connector


1 DCD2 6 DSR2 2 RXD2 7 RTS2 3 TXD2 8 CTS2 4 DTR2 9 RI2 5 GND

2-12

2.4.8 COMl Serial Port Connector (P9)


The 9-pin D subminiature COMI serial port connector, P9, is located on the module's front panel.

Table 2-10. COMI Serial Port Connector


1 DCDI 6 DSRI 2 RXDI 7 RTSI 3 TXDI 8 CTSI 4 DTRI 9 RII 5 GND

2.4.9 VGA Connector (PlO)

The VGA connector, P1O, is a 15-pin subminiature located at the bottom of the module's front panel.

Table 2-11. VGA Connector


1 RED 9 KEY 2 GREEN 10 GND 3 BLUE 11 N/C 4 N/C 12 N/C 5 GND 13 HSYNC 6 GND 14 VSYNC 7 GND 15 N/C 8 GND

2-13


,

2.4.10 Parallel Port Connector (JKl)

JK1 is a 25-pin female D subminiature connector located on the module's front panel.

Table 2-12. Parallel Port Connector


1 STROBE 14 AUTOFEED 2 PDOUTO 15 PERROR 3 PDOUTI 16 INIT 4 PDOUT2 17 SELIN 5 PDOUT3 18 GND 6 PDOUT4 19 GND 7 PDOUT5 20 GND 8 PDOUT6 21 GND 9 PDOUT7 22 GND 10 PACK 23 GND 11 PBUSY 24 GND 12 PE 25 GND 13 SELECT

2.4.11 Speaker Connector (J7)

17 is a three-pin header located on the board near the LEDs.

Table 2-13. Speaker Connector

Pin Signal

1 SIGNAL 2 +5V 3 N/C

2-14

2.4.12 PXTl Connector


The PC/104-compatible PXT1 is a two-row, 64-pin connector. It allows a single card expansion to XVME-678/688 without an adapter card. This interface incorporates the power that allows plug-in adapters to be free of the need for a PI or P2 connection.

Table 2-14. PXTl Pinouts

Pin Row A Signal Row B Signal

1 IOCHCHK* GND 2 SD7 RESETDRV 3 SD6 +5V 4 SD5 IRQ9 5 SD4 N/C 6 SD3 DRQ2 7 SD2 -12V 8 SD1 N/C 9 SDO +12V 10 IOCHRDY KEY 11 AEN SMEMW* 12 SA19 SMEMR* 13 SA18 IOW* 14 SA17 IOR* 15 SA16 DACK3* 16 SA15 DRQ3 17 SA14 DACK1* 18 SA13 DRQ1 19 SA12 REF* 20 SAll SYSCLK 21 SAlO IRQ7 22 SA9 IRQ6 23 SA8 IRQ5 24 SA7 IRQ4 25 SA6 IRQ3 26 SA5 DACK2* 27 SA4 TIC 28 SA3 ALE 29 SA2 +5V 30 SAl OSC 31 SAO GND 32 GND GND

2-15


2.4.13 PATl Connector

PAT1 is a two-row, 40-pin connector that allows a single card expansion to XVME-678/688 without an adapter card. This interface incorporates the power that allows plug-in adapters to be free of the need for a PI or P2 connection.

Table 2-15. PAT1 Pinouts

Pin Row C Signal Row D Signal

0 GNO GNO 1 SBHE* MEMCS16* 2 LA23 IOCS16* 3 LA22 IRQ 10 4 LA21 IRQ11 5 LA20 IRQ12 6 LA19 IRQ15 7 LA18 IRQ 14 8 LA17 OACKO* 9 MEMR* ORQO 10 MEMW* DACK5* 11 S08 ORQ5 12 S09 OACK6* 13 SOlO ORQ6 14 SOlI OACK7* 15 S012 ORQ7 16 S013 +5V 17 S014 N/C 18 S015 GNO 19 KEY GNO

2-16


2.5 INSTALLING THE XVME-678/688 INTO A BACKPLANE

This section provides the information necessary to install the XVME-678/688 PCI AT Processor Module into the VMEbus backplane.

Xycom modules are designed to comply with all physical and electrical VMEbus backplane specifications. The XVME-678/688 is a double-high, single-board VMEbus module. As such, it requires one slot with either just the PI VMEbus backplane, or with both the PI and P2 backplanes.

The XVME-955 Hard Disk/Floppy Disk Module, available from Xycom, is ideally suited for use with the XVME-678/688. It combines a high-capacity 3.5" IDE drive and a 3.5" 1.44 Mbyte micro-floppy into a unit that occupies only two double-high VMEbus slots. Ask your Xycom representative for details.

WARNING Do not install or remove any boards before turning off the power to the bus and all related external power supplies.

1. Disconnect all power supplies to the backplane and/or terminal.

2. Make sure the backplane PI and P2 connectors are accessible.

3. Verify all jumper settings.

4. If using the Intel80387SX math co-processor, install it in socket U7 of the XVME-678/688. Refer to Section 2.8 for more detailed diagrams.

5. Position SWI switch 6 to closed to enable the on-board battery.

6. Connect the floppy disk cable to P4 on the component side of the XVME-678/688 board. Refer to Figure 2-2 on page 2-6 for the location of P4.

7. Connect the IDE hard drive cable to P5 on the component side of the XVME-678/688 module. Refer to Figure 2-2 on page 2-6 for the location of P5.

8. Turn OFF power to the VMEbus cardcage and disconnect the power cable.

2-17


9. Make sure the cardcage slot that will hold the XVME-678/688 is clear and accessible. If using the XVME-678/688 in conjunction with the XVME-955 module, make sure that the two cardcage slots to the right of the XVME-678/688 (which will hold the XVME-955) are also clear.

10. Install the XVME-678/688 into the cardcage by centering the unit on the plastic guides in the slots (PI connector facing up) and pushing the boards slowly toward the rear of the chassis until the PI and P2 connectors engage. The boards should slide freely in the plastic guides.

CAUTION Do not use excessive force or pressure to engage the connectors. If the boards do not properly connect with the backplane, remove the module and inspect all connectors and guide slots for possible damage or obstructions.

11. Secure the module to the chassis by tightening the machine screw at the top and bottom of each board.

12. Connect all remaining peripherals by attaching each interface cable into the appropriate connector on the front of the XVME-678/688 board as follows: VGA cable-VGA, keyboard-KEYBD, serial devices-COM 1 and COM2, and parallel device-LPTl. Refer to Figure 2-2 on page 2-6 for locations of these connectors.

Assuming the steps in the previous sections of this chapter have been followed, the power to the VMEbus cardcage can now be turned ON.

2-18

XVME·688

(I FAIL

C)PASS ABORT

(!) RESET KEYBD

(;) AUOX •••

•• •

. •

xycom VMEbus

Figure 2-3. XVME-678/688 Board Front Panel


2-19


2.6 ADDING EXTENDED BIOS

The XVME-678/688 has one 256Kx8 EPROM that can represent the entire IBM BIOS range. The device address is the physical address which is viewed from an EPROM programmer such as a Data I/O. The system address is the address the code appears at when plugged into the EPROM site on the XVME-678/688, as addressed by the 80386SX processor.

A diagram of the XVME-678/688 and EPROM programmer addresses is shown below:

Device Address

30000-3FFFFF

20000-2FFFF

10000-1 FFFF

08000-0FFFF

00000-07FFF

System BIOS 64K

Diagnostics 64K

User Area 64K

User Area 32K

Video BIOS 32K

System Address

FOOOO-FFFFF

EOOOO-OEFFFF

DOOOO-DFFFF

CBOOO-CFFFF

COOOO-C7FFF

Adding on-board extended BIOS to the XVME-678/688 involves two major steps: programming the EPROM and setting the Extended BIOS Setup Menu.

Programming the EPROM

Before beginning, make sure your EPROM programmer supports 2-Mbit devices.

1. Remove the 32-pin EPROM from socket U8.

2. Place the EPROM into the EPROM programmer's socket.

3. Load the EPROM into the RAM of the programmer. Set the starting address at OH.

4. Remove the EPROM from the socket.

2-20


NOTE At this point, the data should be stored to a disk to protect the information in case of an error in programming.

5. Use a UV light to erase the EPROM.

6. Place your extended EPROM programmer RAM starting at location lOOOOH. The code should not exceed 64 Kbytes.

7. Reburn the EPROM with the new code. This places the new extended BIOS in the DOOO:OOOODOOO:FFFF block.

NOTE At this point, the data should be stored to a disk to protect the information in case of an error in programming.

8. Place the EPROM back into socket U8 on the XVME-678/688.

Setting the EPROM Menu

1. Power-up the XVME-678/688. After the memory tests, press < Ctrl > < Alt > < S > simultaneously to enter the Extended BIOS Menu.

2. Use the arrow keys to highlight Solid State Disk Setup and press < Enter> to select this menu.

3. Enable the on-board extended BIOS from DOOOO-DFFFF and disable the BIOS from EOOOO-EFFFF.

4. Select FlO to save the configuration, and then press < Esc> to exit the menu.

The procedure is now complete.

2-21


2.7 INSTALLING DRAM

The XVME-678/688 has four SIMM sites in which to add memory. Due to the 25 MHz CPU speed, the access time of the DRAM interface is very important. To run at 0 wait states, the SIMMs must have the following access times:

• 60 ns access time for nine chip DRAM SIMMs • 70 ns access time for three chip DRAM SIMMs

If you opt for 80 ns DRAMs, change the 0 wait state option to 1, wait state in the Setup Menu.

NOTE Three-chip memory modules are recommended to meet the VME height specifications.

The XVME-678/688 can accommodate 1, 2, 4, 10 or 16 Mbytes of DRAM, mounted on SIMM strips. SIMM strips with 256Kx9, 1Mx9, or 4Mx9 DRAM may be used. The table below lists the combinations needed for the five memory configurations. (The bank location is silk screened on the back of the board.)

Table 2-16. Bank and SIMM Size

Memory Bank 0 low Bank 0 high Bank 1 low Bank 1 high

1 Mbyte 265Kx9 265Kx9 256Kx9 256Kx9

2 Mbytes 1Mx9 1Mx9 N/A N/A

4 Mbytes 1Mx9 1Mx9 1Mx9 1Mx9



1 !I1hyte A1envry The 1 Mbyte DRAM is divided into 640 and 384 Kbyte blocks for 80386SX accesses when the Shadow RAM option is not enabled. The 640 Kbyte block resides from 000000-09FFFF; the 384 Kbyte block from 100000-15FFFF. If the shadow RAM option is enabled, the DRAM is reduced to the lower 640 Kbytes of DRAM.

Four 256Kx9 memory SIMMs are needed for the 1 Mbyte configuration.

2-22

2 Mhytes Metmry


The 2 Mbyte version has 1.64 Mbytes of DRAM divided as 640 Kbyte and 1 Mbyte blocks. The additional 384 Kbytes of DRAM are dedicated for Shadow RAM and are not relocatable. Because this configuration uses only two SIMMs, there is no interleaving. This configuration tends to be less optimal for performance than the other memory configurations.

Two IMx9 SIMMs are needed for the 2 Mbyte configuration.

4 Mbytes Metmry The 4 Mbyte version has 3.64 Mbytes of DRAM divided as 640 Kbyte and 3 Mbyte blocks. The additional 384 Kbytes of DRAM are dedicated for Shadow RAM and are not relocatable.

Four IMx9 SIMMs are needed for the 4 Mbyte configuration.

10 Mbytes Metmry The 10 Mbyte version has 9.64 Mbytes of DRAM divided as 640 Kbyte and 9 Mbyte blocks. The additional 384 Kbytes of DRAM are dedicated for Shadow RAM and are not relocatable. Because this configuration uses two SIMMs of different sizes, there is no interleaving. This configuration tends to be less optimal for performance than the others.

Two 4Mx9 SIMMs and two IMx9 SIMMs are needed for the 10 Mbyte configuration.

16 Mbytes Metmry The 16 Mbyte version has 15.64 Mbytes of DRAM divided as 640 Kbyte and 15 Mbyte blocks. The additional 384 Kbytes of DRAM are dedicated for Shadow RAM and are not relocatable.

Four 4Mx9 SIMMs are needed for the 16 Mbyte configuration.

Installation ProcedlO'e

1. Turn off power to the XVME-678/688.

2. Refer to Table 2-16 on page 2-21 and select the appropriate type of SIMMs for your memory configuration, and install them into the appropriate banks.

3. Refer to Figure 2-4 on the next page. For easiest access to the SIMM sockets, install the strips in the sockets from right to left (referenced with PI and P2 facing down). Insert the contact edge of the SIMM strip into the socket with the chips on the strip facing up. Be sure the edge of the strip is aligned in the socket. Press down firmly on the strip until it snaps into place.

2-23


I

:®

,II ~

@

Insert DRAM Module, as shown in topview@ and side view ® . Press down on DRAM Module until it snaps into place, as shown in side view ©.

Figure 2-4. DRAM Installation

To remove a strip, pull gently outward on the two metal tabs on either end of the socket. The strip should loosen in the socket and pop forward slightly for removal.

CAUTION Do not pull too hard on the metal tabs or they could snap off the socket.

2-24


2.8 INSTALLING AN OPTIONAL INTEL 80387SX MATH CO-PROCESSOR

With the power to the XVME-678/688 off, install the 80387SX math co-processor into socket U31 of the XVME-678/688, as shown in Figure 2-5. Align pin 1 of the chip with pin 1 of the socket designated for the math co-processor (U7), as shown.

Math CoProcessor

Chip Pin 1

Figure 2-5. 80387SX Math Co-processor Installation

2-25

Chapter 3 - BIOS SETUP MENUS

3.1 INTRODUCTION

This chapter contains information on running the BIOS Setup Menus on the XVME-678/688. All pertinent menu instructions are included.

Beyond the standard key codes translated by the BIOS, there are additional function keys that can be used in the BIOS Setup Program:

<Ctrl> <Alt> <S> < Ctrl > <Alt> <L>

Enter SETUP program Soft keylock

In addition, the following function keys can be used on the XVME-678 in the BIOS Setup Program if the cache is set to zero.

< Ctrl > <Alt> <-> <Ctrl> <Alt> < + >

Switch to slow CPU speed Switch to fast CPU speed

3 .2 SOFTWARE CONTROL AND INITIAL SETUP

The XVME-678/688 is equipped with the Quadtel AT Compatible BIOS System. This BIOS allows easy modification of certain characteristics of the system configuration. The parameters set during the BIOS SETUP program are stored in battery-backed CMOS RAM so that the information is retained during power-down periods. Once the BIOS is set up, it is ready to run any PCI AT software. (Consult the operating system manual for specific applications and instructions.)

Several Xycom extensions were added to the XVME-678/688 BIOS:

• ROM DOS (Solid State Disk) support • Menus for configuring Xycom value-added features • XVME BIOS Interrupt functions for access to Xycom' s value-added features

During power-up, the XVME-678/688 communicates with devices and checks its hardware configuration against the configuration information stored in the CMOS memory. The red FAIL and green PASS LEDs located on the CPU front panel come on at power-up, and after the processor has successfully completed diagnostics, the FAIL LED goes out. The PASS LED remains on as long as power is on, diagnostics pass, and the processor functions properly. If an error is detected, or parameters need to be defined, the FAIL LED remains on, and the diagnostic program prompts you to go to the SETUP program. Some errors are significant enough to abort start-up.

3-1

Chapter 3 - BIOS Setup Program

General instructions for navigating through the screens are described below:

• Arrow keys move the cursor up, down, left, and right. Press < Enter> to validate a selection. • < Esc> exits the menu. You are prompted to save any changes. • < F5 > selects the previous or smaller value. • < F6 > selects the next higher value. • < F9 > automatically configures the system with the default values. These default values are

defined by the system configuration and the values set in the Setup Menu.

NOTE Disk drives must be configured manually.

• <FlO> saves the current configuration. With the exception of time and date, the configuration is not saved until < FlO> is pressed.

3.3 BIOS MAIN MENU

The BIOS Main Menu is presented as the top level in the BIOS setup menu structure. To access the Main Setup Menu, depicted below, press < Ctrl > < Alt > < S > simultaneously after the BIOS has completed the RAM test.

Main Setup Menu Copyright 1993 by Xycom, Inc.

Setup VMEbus Master Setup Solid State Disk Setup Extended BIOS Features System Information Diagnostics

t.,1..Move Enter Select Esc Exit

Figure 3-1. Main Setup Menu

3-2

3.3.1 BIOS Setup Menu


On the Setup Menu, depicted in Figure 3-2 below, the time, date, and setup information contained in the CMOS RAM can be changed. This information is used by the System BIOS for system configuration.

Extended BIOS Setup - Copyright 1989-91 Quadtel Corporation

Current Date: [0110111988] Current Time: [00:00:00]

[ [ [ [

640]K 3072]K

96]K 288]K

System Memory Extended Memory Shadow Memory

EMS Memory

Internal COM A: Internal COM B: Internal LPT:

Diskette Drive 0: Diskette Drive 1:

[COM1, 3F8H] [COM2, 2F8H] [LPT1, 378H]

[1.44 MB, 3 1/2] [N ot Installed ]

Fixed Disk 0: Type: [None] Fixed Disk 1: Type: [None]

+-th Move F1 Help Esc Exit

F5 F6

Previous Value Next Value

Video System: Power-up Speed:

BIOS Shadow:

Wait States:

Internal Floppy: Internal IDE:

[EGA I VGA [Fast

[System in RAM] [Video in RAM] [0, All banks]

[Enabled ] [Enabled ]

System Memory Cache: [On ] AT Bus Speed: [10.0] MHz

F9 Automatic Configuration FlO Save Configuration

Figure 3-2. BIOS Setup Menu

Each of the options on the Setup Menu are described on the next few pages. Default items are underlined.

3-3


3.3.1.1 Date (01/0111988 format)

The date entry sets the real time clock for the month, day, and year. The left and right arrow keys and the enter key may be used to move from one field to the next. The numeric keys, 0-9, are used to change the field values. It is not necessary to type zeros in front of numbers.

3.3.1.2 Time (00:00:00 format)

The time entry sets the real time clock for hours, minutes, and seconds. During the power-up sequence, the time is read from the real time clock and saved in the BIOS system time.

The hour is calculated according to a 24-hour military clock, i.e., 00:00:00 through 23:59:59. The left and right arrow keys and the enter key may be used to move from one field to the next. The numeric keys, 0-9, are used to change the field values. It is not necessary to enter the seconds or type zeros in front of numbers.

3.3.1.3 Setup RAM Configuration

The RAM on the XVME-678/688 can be partitioned or allocated between system memory, extended memory, shadow memory, and EMS memory. The F9 key is used to automatically resize memory and select default memory values. The default memory configuration is 640 Kbytes system memory, 96 Kbytes shadow memory, 288 Kbytes EMS memory, and 3072 Kbytes or 15360 Kbytes of extended memory, depending on the XVME-678/688 version.

3.3.1.4 System Memory

This option should always indicate the size of conventional system memory as 640 Kbytes.

3.3.1.5 Extended Memory

This option sets the amount of extended memory in Kbyte increments. The maximum amount of extended memory is 31 Mbytes (31744 Kbytes).

3.3.1.6 Shadow Memory

This field displays the amount of shadow memory in use. The contents of this field are controlled by BIOS shadow selection. Shadow memory is used to copy the system and/or video BIOS into RAM to improve performance. The XVME-678/688 allocates for Shadow RAM in Kbytes, and this number will

3-4


be displayed on the menu. This field, which is not editable, is controlled by the BIOS shadow selections (Section 3.3.1.13). It is for reference only.

The default shipping configuration for the XVME-678/688 will have the System BIOS and the Video BIOS shadowed. Shadowing the BIOS increases system performance.

NOTE Shadow RAM is always allocated for BIOS shadow only. Disabling the BIOS shadow option will not increase the amount of system memory.

3.3.1.7 EMS Memory

This option is used to set the amount of system memory to be configured as Expanded Memory (EMS). As the amount of EMS memory increases, the amount of extended memory decreases, and vice versa.

3.3.1. 8 Internal Floppy and IDE (Disabled/Enabled)

These selections enable or disable the internal floppy and IDE hard disk drive controllers.

3.3.1. 9 Diskette Drives 0 and 1

Diskette Drive 0 Diskette Drive 1

(none/1.44MB. 31h"/360KB, 5IA"/1.2MB, 5IA"/720KB, 31;2'1) (~/1.44MB, 31;2'1/360KB, 5IA "/1.2MB, 5IA "/720KB, 31;2'1)

These fields are used to specify the types of floppy disk drives connected to the PC/AT.

3.3.1.10 Fixed Disk Drives 0 and 1

Fixed Disk 0 Fixed Disk 1

(~/l-14/l6-45/User)

(~/1-14/16-45/User)

This selection individually configures the disk drives as one of 45 drive types, a user-defined type, or not installed. All 45 drive types are displayed on the screen if Fl is pressed. If the type "User" is selected, several fixed disk parameters must be specified: number of cylinders (CY), heads (HD), sectors per track (ST), landing zone cylinder (LZ), and write precompensation (WP). Consult your fixed disk drive manual for information on any of these parameters.

3-5


3.3.1.11 Video System

There are four video adapter choices:

• EGAIVGA (Enhanced Graphics Adapter, Video Graphics Array, or any special video adapter) • 40 Color (Color Adapter, power-up in 40 column mode) • 80 Color (Color Adapter, power-up in 80 column mode) • Monochrome Adapter

This field should not be changed from its default-EGAIVGA. This allows video functions to be controlled by the video BIOS rather than the system BIOS.

3.3.1.12 Power-Up Speed

This option determines the CPU speed at boot time. Choices are Fast (25 MHz) and Normal (10 MHz).

3.3.1.13 BIOS Shadow (System in RAM/ROM, Video in RAM/ROM)

The System BIOS and the VGA BIOS may be shadowed into DRAM to increase system performance. Shadowing is the process of loading the BIOS from EPROM into DRAM after the power-up. Since the DRAM bus width is 16 bits and the EPROM is only 8 bits, opcode fetches from the DRAM have a significant increase in system performance.

3.3.1.14 Wait States

This sets the number of wait states for memory controlled by the chipset to 0 or 1.

3-6

NOTE It is recommended that automatic configuration be used to select the COM and LPT ports. Automatic configuration selects the first logical port address that does not conflict with other communication ports in your system. If the address is select manually, there is the possibility that there will be a conflict with other system devices.


3.3.1.15 Internal COM A and COM B

These selections individually set the port address that will be programmed by the BIOS for each port. There are three options:

• Off • Default for COM A COM1 (3F8h)

COM2 (2F8h) • Default for COM B

NOTE It is recommended that automatic configuration be used to select the COM and LPT ports. Automatic configuration selects the first logical port address that does not conflict with any other communication ports in your system. If the addresses are selected manually, conflicts with other devices in the system may occur.

3.3.1.16 Internal LPf (off/LPT1 at 378h/278h/3BCh)

This item selects the port address to be programmed by the BIOS for the internal LPT port. There are four options:

• Off • LPT1 at 378h • LPT1 at 278h • LPT1 at 3BCh

3.3.1.17 System Memory Cache (Off/Qn/N/A)

The system memory cache option-which refers to the XVME-678' s 1 Kbyte internal cache on the 486SLC/e-can be enabled or disabled by changing the field to ON or OFF. If the cache is disabled (OFF), the XVME-678 takes longer to perform memory accesses, degrading system performance. The XVME-688 does not support this option, so NI A is the default.

3.3.1.18 AT-bus Speed (8.33/10 MHz)

The AT -bus speed is software selectable on power-up. Bus speed can be 8 or 10 MHz.

3-7


3.3.2 VMEbus Master Setup Menu

The VMEbus Master Setup Menu, depicted in Figure 3-3 below, allows configuration of the XVME-678/688 VMEbus master interface, auxiliary non-maskable interrupts (NMIs), and the VMEbus interrupt handler.

VMEbus Master Setup - Copyright 1993 by Xycom, Incorporated

VMEbus Master Configuration: System Resources Disabled Master Interface [Disabled] VMEbus Request Level [3] Master Byte Swapping N/A VMEbus BERR Timeout N/A Master Access Mode [N on-Privileged] VMEbus Release [When done]

Auxiliary NMI Configuration: VMEbus BERR [Disabled] Abort Push Button [Disabled] VMEbus SYSF AIL [Disabled]

VMEbus ACF AIL N/A

VMEbus Interrupt Handler Configuration: L1 [Disabled] L2 [Disabled] L3 [Disabled] L4 [Disabled] L5 [Disabled] L6 [Disabled] L 7 [Disabled]

+-thMove F5 Previous Value FlO Save Configuration F6 Next Value Esc Exit

Figure 3-3. VMEbus Master Setup Menu

3.3.2.1 Master Interface (Disabled/Enabled)

Select Enabled for the system to power-up with the VMEbus master interface enabled. If disabled, the XVME-678/688 cannot access VMEbus memory or perform VMEbus interrupt acknowledge (lACK) cycles.

3.3.2.2 Master Byte-Swapping

This feature is not supported (N/A) on the XVME-678/688. It is present on the menu only for compatibility with other XVME PC/AT products-such as the XVME-674/677-that support programmable byte-swapping.

3-8

3.3.2.3 Master Access Mode (Non-Privileged/Supervisory)


This field allows the choice of Non-privileged or Supervisory accesses for VME master cycles. The access mode selection controls the AM2 signal on the VMEbus when the XVME-678/688 performs VMEbus accesses.

3.3.2.4 System Resources (Display Only)

This option displays the state of the SYSRES switch, which determines if the VMEbus system resources are provided by the XVME-678/688 or another VMEbus processor. The system resources are VMEbus Arbiter, BERR timeout, SYSCLK, and lACK daisy chain driver. These resources must be provided by the module installed in VMEbus slot 1.

3.3.2.5 VMEbus Request Level (01112/3)

This feature sets which bus request level (0,1,2,3) will be used by the XVME-678/688 when requesting use of the VMEbus. If the XVME-678/688 is providing the system resources, this selection is automatically set to 3.

3.3.2.6 VMEbus BERR Timeout

If system resources are enabled, the length of the VMEbus BERR timeout is 16 /J-S. If system resources are disabled, this option is unavailable.

3.3.2.7 Auxiliary NMI Configuration

The XVME-678/688 has both individual and group enable bits for the auxiliary non-maskable interrupts (ANMls) and auxiliary maskable interrupts (AMls). Individual ANMI and AMI bits are configured by the VMEbus master menu, but the group enable bits are left disabled and must be enabled by software (via XVME BIOS functions 21H and 51H, or by directly setting bit 4 and/or bit 7 of CONREGI-I10 port 30H) before the actual interrupts can be processed. This is because non-maskable interrupts (NMls) and IRQlO handlers must be provided by a user application or the operating system, not by the BIOS.

3-9


These options are used to define which of the following ANMIs. are enabled at power-up:

• ABORT Switch • VMEbus BERR • VMEbus SYSFAIL • VMEbus ACFAIL

Each ANMI can be enabled or disabled. All are disabled by default.

VMEbus ACFAIL is not available (N/A) on the XVME-678/688. It is listed on the menu only for compatibility with other XVME PC/AT products-such as the XVME-674/677-that support VMEbus ACFAIL.

3.3.2.8 VMEbus Interrupt Handler Configuration

This option determines which VMEbus interrupt level AMIs (1-7) can be received by the XVME-678/688. Each of the interrupt levels can be enabled or disabled. All are disabled by default.

3-10

3.3.3 Solid State Disk Setup Menu


The Solid State Disk Setup Menu, depicted in Figure 3-4 below, is used to configure the XVME-678/688 Solid State Disk (SSD) interface and the on-board extended BIOS.

Solid State Disk Setup - Copyright 1993 by Xycom, Incorporated

Solid State Disk Options: SSD Size [ 128]KBytes SSD Interface [Disabled] SSD Address [ OOO]OOOOOH Boot from SSD [Disabled] SSD Device Type [RAM ] SSD Location [VMEbus Standard ] XVME-956/l01 Device Size [l]Mbit

Onboard Extended BIOS Options: EOOOO-EFFFF Disabled DOOOO-D7FFF [Disabled] C8000-CFFF [Disabled] D8000-DFFF [Disabled]

~thMove F5 Previous Value FlO Save Configuration F6 Next Value Esc Exit

Figure 3-4. Solid State Disk Setup Menu

3.3.3.1 SSD Interface (Disabled/Enabled)

If enabled, the SSD driver is initialized when the CPU is booted; if disabled, the SSD driver is not initialized.

3.3.3.2 Boot from SSD (Disabled/Enabled)

If enabled, the SSD is assigned the drive C designator and the system attempts to boot from drive C. If disabled, the SSD is assigned the drive D designator and the system does not attempt to boot from drive D. This option is only valid if the SSD Interface has been enabled.

3.3.3.3 SSD Location (VMEbus Standard/XVME-956/l01)

There are two options:

VMEbus Standard XVME-956/l01

The SSD resides in VME standard memory (A24). The SSD resides on the Xycom PC/104 Expansion Bus.

3.3.3.4 SSD Size (.l2..8.KBytes)

This defines the size of the SSD in 128 Kbyte increments, up to 32 Mbytes.

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3.3.3.5 SSD Address (QQQOOOOOh)

This indicates the starting address of the SSD in hexadecimal, on 1 Mbyte boundaries. The SSD Address is set to zero if the SSD Location is XVME-956/101.

3.3.3.6 SSD Device Type (RAM/ROM/FLASH/EEPROM)

This specifies the device type used by the SSD. The EEPROM option is not implemented at this time.

3.3.3.7 XVME-956/101 Device Size (1/2/4 MBits)

This option is only necessary if SSD is in the XVME-956/101. It specifies the size of the devices used for the SSD. This is necessary only if the SSD Location Field has been set to XVME-956/101. It specifies whether the devices installed in the XVME-956/101 are 1 Mbit, 2 Mbit, or 4 Mbit devices.

3.3.3.8 On-board Extended BIOS

An extended BIOS may be on-board or off-board. The XVME-678/688 contains an onboard extended BIOS ROM. An offboard extended BIOS may be located on a module installed in the PC/I04 site. During power-up, the XVME-678/688 BIOS scans memory to locate any extended BIOS. The onboard extended BIOS setup options indicate where extended BIOS code is located. All extended BIOS areas are assumed to be offboard by default. Onboard extended BIOS must be enabled to function properly.

The DOOOO-DFFFF extended BIOS memory ranges are automatically disabled when Solid State Disk memory is set to XVME-956/101. The EOOO-EFFF memory ranges are automatically disabled when Solid State Disk memory is set to VMEbus Standard.

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3.3.4 Extended BIOS Features Menu

The Extended BIOS Features Menu is depicted below.

Extended BIOS Features - Copyright 1989-91, Quadtel Corp.

Auto-park Disk: [No] Keyboard Click: [No ] Quick Boot: [No] Keyboard Delay: [3/4 Sec ] Screen Saver: [Disabled] Keyboard Rate: [221 Sec]

Numlock Boot State: [Auto ]

+-th Move F5 Previous Value F9 Auto Configuration Esc Exit F6 Next Value FlO Save Configuration

Figure 3-5. Extended BIOS Features Menu

Each of the choices on this menu are described below.

3.3.4.1 Auto Park Disk (N.Q/Yes)

This selection determines whether the system BIOS automatically parks the fixed disk drive. If this option is enabled, the system BIOS parks the fixed disk drive(s) heads after several seconds of inactivity. Most modern hard disk drives have self-parking heads, so enabling this option may not be necessary.

CAUTION This feature can be incompatible with fixed disk drives that are not BIOS compatible and could cause problems with programs that do not utilize the BIOS for fixed disk 110.

NOTE Parking the heads causes some drives to spin down so that they do not respond to accesses quickly enough and display the message: "Not ready reading drive C. Abort, Retry, Fail?"

3-13'


3.3.4.2 Quick Boot (NQ/Y es)

When quick boot is selected, the system BIOS bypasses the floppy disk drive tests, memory tests, and floppy disk drive boot on power-up or soft reset. The system initializes and boots from the fixed disk in a few seconds.

CAUTION During hard disk partitioning and formatting, the quick boot selection must be set to No. Otherwise, an operating system missing error is displayed, and the system does not boot.

NOTE If yes is the option selected, memory is not tested and the floppy disk drive(s) defined in the Setup Menu must be correct. Also, the system will not boot from drive A.

3.3.4.3 Screen Saver (Disabled/10 min/30 minl1 hour)

This option allows blanking the screen after a specified period of keyboard inactivity. This ensures that the data displayed does not permanently burn into the monitor. Blanking can be set to occur after 10 minutes, 30 minutes, or one hour, or this option can be disabled. Press any key to redisplay the screen after the screen saver has been activated.

CAUTION Do not enable the screen saver when running programs that do not use the BIOS for keyboard handling, such as Microsoft Windows. If the screen saver is enabled with these programs, the screen blanks after the specified time, regardless of activity, and can only be restored by exiting the program.

3.3.4.4 Keyboard Click (NQ/Y es)

If enabled, this function provides audible key press feedback by causing the BIOS to click through the system speaker every time a key is pressed. This option is only valid for systems with a speaker connected to the speaker jack (110).

3-14

3.3.4.5 Keyboard Delay (112/.3/4 quarters of a second)


This sets the amount of time that elapses after a key is pressed before the key starts to repeat. The smaller the time selected, the sooner the key starts to repeat.

3.3.4.6 Keyboard Rate (2/6/10/13/18/22/27/30 per second)

This option defines the rate at which the keyboard repeats while a key is pressed. The higher the number, the faster the key repeats.

3.3.4.7 Numlock Boot State (All1a/OniOft)

This option determines how the BIOS defines the numlock key at power-up or soft reset. Normally, the BIOS sets the numlock (numeric keys selected) if it detects a 101- or 102-key keyboard at power-up. If an 84-key keyboard is detected, numlock is turned off (cursor keys selected). Select Auto to keep this state; On to select the numeric keys, regardless of keyboard; or Off to select the cursor keys, regardless of keyboard.

3-15


3.3.5 System Infonnation Menu

The System Information Menu, depicted in Figure 3-6 below, provides the following information:

System Information - Copyright 1989-91 by Xycom, Incorporated

Processor: Cx486SLC/e LPT 1 Address: 0378H Coprocessor: Internal LPT2 Address: Unused

LPT3 Address: ·Unused

BIOS ID: 3171000006 BIOS Revision: 03.06.01 COM1 Address: 03F8H

COM2 Address: 02F8H Programmable Memory: 4096K COM3 Address: Unused

Other Memory: OK COM4 Address: Unused

Internal Mouse: No

Press < any key> to exit.

Figure 3-6. System Information Menu

The System Information Menu states the type of processor and math co-processor used and the port addresses. The BIOS ID and revision identify the BIOS and may vary. Programmable memory is controlled by the BIOS. Other memory includes AT-bus memory that is annexed as system memory. (This memory could be from a PC/104 expansion card.)

3.3.6 Diagnostics Menu

The Advanced Diagnostics Software System is a collection of utility programs that provide advanced tests for PC/AT-compatible systems. This section contains information on using the Advanced Diagnostics Software System on the XVME-678/688. All pertinent menu instructions are included.

The Diagnostics Menu offers the following choices: Park Fixed Disks, Diagnostics, and Format Fixed Disk. Each of the choices from the Main Menu is explained in the following sections.

3.3.6.1 Park Fixed Disks

This menu. selection parks the fixed disk drive(s) by placing the fixed heads over the diagnostic cylinder so vibration does not damage the usable media. This operation should be performed before transporting the system.

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3.3.6.2 Diagnostics

When Diagnostics is selected from the Main Menu, a warning message is displayed. It states that running the utility can cause problems with other running software. You are also told to do the following:

• Reboot your system after running diagnostics. • Format your floppy disks using DOS after exiting the utility. • Insert scratch diskettes into all drives.

After reading the warning and inserting the disks, press (N) to abort the operation or (Y) to continue.

If (Y) is selected, the Advanced Diagnostics Menu appears. It is shown in Figure 3-7 below.

Advanced Diagnostics V1.04A, Copyright 1989, 1990 Quadtel Corporation

Continuous: [No] Stop on error: [Yes] Echo log to LPT1: [No]

[P] System Board [N] Monochrome Adapter [ 84] Keyboard [N] Color Graphics Adapter [640K] System Memory [N] Enhanced Graphics Adapter [3072K] Extended Memory [P] Video Graphics Array

[N] Monochrome Parallel [1.2 MB] Diskette Drive 0 [P] Primary Parallel [360 KB] Diskette Drive 1 [P] Secondary Parallel [P] Fixed Disk 0 [P] Primary Serial [N] Fixed Disk 1 [P] Secondary Serial

t-l. Move F5 Previous Value F9 Test Present Devices F1 Help F6 Next Value FlO Test Selected Devices Esc Exit

Figure 3-7. Advanced Diagnostics Menu

Items that appear in bold in the menus indicate fields that users can change. Default settings initially appear on the screen.

Each of the selections on the menu indicate the hardware item to test and the configuration of that item. Some items are present (P) or not present (N), while others specify a hardware type. For example, Keyboard can be an 84-key keyboard, a 101-key keyboard, or not present.

The selections shown in the menu are detected by the diagnostics system. Use the arrow keys to select items to change to override the automatic selection process or to exclude certain tests from being performed.

3-17


General instructions for using this menu are described below:

• Arrow keys (t.J,) move the cursor up and down. • TAB moves to the right. • < Enter> validates the selection. • < Esc> exits the menu. You are prompted to save any changes. • < F5 > selects the previous or smaller value; < F6> selects the next or higher value. • < F9 > tests all currently available items. Set these selections to not present (N) if there are

specific tests that you do not want performed. • < FlO> tests a single item when the cursor is moved to the specified test. The selection

to test cannot be set to N or None.

Each of the tests on the Diagnostics Menu is described below.

When a test is initiated, a window like that shown in Figure 3-8 is displayed. The information shown depends on the type of test selected.

Advanced Diagnostics Copyright 1989, 1990 Quadtel Corporation

Continuous: No Stop on error: Yes Echo log to LPTl: No Press < ESC> to abort current test.

Testing: Primary Async Test Results:

External Loopback ... None Modem control lines ... Passed Baud rate clock (110 baud) ... Testing

Figure 3-8. Advanced Diagnostics Test Menu

The left side of the screen shows information relating to the test(s) being performed; the right side shows results of completed tests.

3-18

CAUTION Tests that are labeled destructive could destroy information. Use caution when testing floppy and hard disks.


3.3.6.3 Test Control Options

The fields at the top of the screen are options that control how the tests are performed. These options must be set before a test or tests are initiated.

Continuous Test Set to yes or no. When set to yes, the test is performed continuously until < Esc> is pressed to stop it. After pressing < Esc>, press the space bar to continue or press < Esc> to abort the test(s). Continuous test works with a single test (selected by < FlO » or several tests (selected by < F9 ».

Stop on Error

Echo to LPTI

Set to yes or no. When set to yes, the diagnostic system stops after detecting an error. After the system reports the error, press the space bar to continue or < Esc> to end testing.

Set to yes or no. If set to yes, the test result data is written to a printer attached to LPTl. This feature is useful if Continuous Test is set to Yes, Stop on Error is set to No, and run the test(s) unattended.

NOTE Some of the submenu tests require response to prompts. These are identified as interactive. If performing continuous unattended tests, do not select any interactive tests.

3.3.6.4 System. Board

This selection tests the processor, DMA registers, CMOS RAM, real time clock, timers, and interrupt controller. After the tests are completed, press < Esc> to return to the Diagnostics Menu or the space bar to run the tests again.

3.3.6.5 Keyboard

After Keyboard test is selected, a menu appears that allows the keyboard and controller tests to be enabled or disabled.

< F7 > selects all tests, while < F8 > sets all tests to No.

After pressing < FlO > to accept the selections, a keyboard map appears that is appropriate to the type of keyboard specified under Diagnostics Keyboard. Press < Ctrl > < Y > if all keys are working correctly or < Ctrl > < N > if there are keys that do not work.

3-19


3.3.6.6 System Memory

This diagnostic tests the amount of read/write system memory.

3.3.6.7 Extended Memory

This diagnostic tests the amount of extended system memory. Separate tests for read/write and address lines are performed.

3.3.6.8 Diskette Drives 0 and 1

Choosing to test the diskette drives brings up a submenu that requests the drive to test. Certain test features can be set to Yes or No. The test will seek tracks, verify tracks, change the disk, and perform a read/write and format. The disk change is interactive, and read/write and format are destructive.


Select test for diskette drive A:

Seek tracks [Yes] Verify tracks [Yes] Disk change (interactive) [No]

Read / Write (destructive) [Yes] Format (destructive) [Yes]

t-J.. Move F5 Toggle F7 All FI Help F8 None Esc Abort FlO Accept

Figure 3-9. Diskette Drive Menu

3-20


3.3.6.9 Fixed Disk Drives 0 and 1

This selection brings up a menu that enables or disables controller, head select, and seek tests. The drive designation for the drive to be tested must be entered as 0 or 1.


Select tests for fixed disk: 0

Controller test [Yes] Head select test [Yes] Seek test [Yes]

t-J.. Move F5 Toggle F7 All Esc Abort F8 None FlO Accept

Figure 3-10. Fixed Disk Menu

CAUTION Tests that are labeled destructive could destroy information. Use caution when testing floppy and hard disks.

3.3.6.10 Monitor Type

Set your monitor type to P and the other monitor types to N. There are four choices:

• Monochrome Adapter (MDA) • Color Graphics Adapter (CGA) • Enhanced Graphics Adapter (EGA) • Video Graphics Array (VGA)

Select the VGA option if the video controller on the XVME-678/688 has not been disabled.

3-21


3.3.6.11 Parallel Port Tests

Set the primary, secondary, and monochrome parallel ports to (P) if present or (N) if not present in your system. When a parallel port test is selected, a menu similar to the one below appears:

Select Tests for Parallel

Internal Loopback [Yes]

Printed Pattern [No] (requires connected printer)

External Loopback [No] (requires loopback connector)

t-l.. Move F5 Toggle F7 All Esc Abort F8 None FlO Accept

Figure 3-11. Parallel Port Test Menu

The port(s) selected are tested for externalloopback, internalloopback, and printer pattern.

If performing a parallel loopback test, there must be a loopback connector on the parallel port. The pinouts of this connector are shown in Figure 3-12 below.

3-22

Serial L.oopback Connections

i

SLCT

~~AUTOFEED ERR .21

DOii e15 3 -16 e

INIT - 17 e 4 SLCTIN

• e5 e18 .6 e19 .7

e20 .8

e21 .9 ACK e22 10

e 23.11 BUSY

e24 .12 IlpE e25 .13 IlsTRB

Parallel Loopback Connections

Figure 3-12. Serial and Parallel Loopback Connections


3.3.6.12 Serial Port Tests

Set the primary and secondary serial ports to (P) if present or (N) if not present in your system. A menu appears after selecting the port(s) to test. Baud rate clock, internal transfer and receive data lines, and modem control data lines can be tested. A loopback connector is required to execute the externalloopback test. Refer to Figure 3-12 for the Serial and Parallel Loopback Connections diagram.

3.3.7 Fonnat Fixed Disk Menu

Select Format Fixed Disk from the Main Menu to format fixed disk drive(s). A menu prompts for which fixed disk (0 or 1) to format. Use the arrow keys to select the disk and press < Enter>. A warning is displayed stating that this operation will destroy all data on the selected hard drive. You are prompted to continue. If (Y) is selected, the Format Fixed Disk Menu (shown in Figure 3-13) appears:

Format Fixed Disk vl.02

Drive: 0

Cyl Hd

Interlv: [03]

t.,l.. Move

Esc Escape

Heads: 8 Cylinders: 1024

Cyl Hd Cyl Hd Cyl Hd Cyl Hd

Insert: Cyl [0 ] HD [0] Bad: 0

InslDel Bad Track F5 Scan bad tracks F2 Clear Table F6 Analyze Surface F3 Print Table F7 Format Unformatted F4 Set Interleave F8 Format Preformatted

Figure 3-13. Format Fixed Disk Menu

CAUTION Most IDE drives should not be low-level formatted. Check your IDE drive manual for formatting procedures.

3-23


3.3.7.1 Using the Bad Track Table

Bad tracks are areas of the fixed disk that cannot properly store data. Bad tracks are displayed in the center of the menu. This list is automatically updated when the < F5 >, < F6 >, or < F8 > commands are used.

To add a bad track manually, press < Insert> and use the arrow keys or < Enter> to select the cylinder and head fields. Enter the appropriate information and press <FlO> or <Enter>. You are alerted if you enter an invalid head or cylinder. Use the arrow keys to position the cursor, press < Delete>, and then enter the new information.

Press < F2 > to clear the entire bad track table. Press < F3 > to print the table. If the drive has already been formatted, press < F5 > to search for existing bad tracks.

3.3.7.2 Setting the Interleave

The interleave is the value used by the format operation to interleave the fixed disk tracks. Press < F4 > to set the interleave. Consult your disk drive manual to set the proper interleave.

NOTE The interleave specified is the value which will be used to format, which is not necessarily the current value for your fixed disk.

If the interleave is not set, a default of three is used.

3.3.7.3 Analyzing the Fixed Disk Surface

If you do not need to reformat the entire fixed disk, but want to perform a thorough media test to detect any bad or marginal areas, select < F6 > to analyze the surface.

CAUTION Analyzing the surface causes all data on the disk to be lost.

Any bad tracks found in the analysis are automatically added to the bad track table. As they are located, the bad tracks are reformatted as bad to prevent these areas from being used subsequently.

3-24

3.3.7.4 Fonnatting a New Fixed Disk Drive


Formatting the disk sets bad tracks with a special attribute so other programs (like DOS FORMAT) do not attempt to use these areas.

After installing a new fixed disk drive, enter the bad track information provided by the manufacturer into the bad track table. Next, press < F7 > to begin formatting. The following operations are performed:

• Formatting each track of the fixed disk using the current interleave • Reformatting each bad track as bad so that it cannot be used

3.3.7.5 Fonnatting an Already Fonnatted Disk

If the fixed disk was previously formatted, select < F8 > to begin formatting. The following operations are performed:

• The drive is scanned for bad tracks, which are added to the bad track table. • Each track is reformatted using the current interleave. • Each bad track is reformatted as bad so it cannot be used. • A surface analysis is performed on the media and any additional bad tracks found are reformatted

as bad and added to the bad track table.

3.3.7.6 Finishing the Fonnatting

The Fixed Disk Format commands perform low-level format operations on the fixed disk drive(s). After the format is complete, run the DOS FDISK command followed by DOS FORMAT to prepare the media for use under DOS (or the corresponding utilities for another operating system). Refer to the operating system manual for more information.

3.3.7.7 Error Codes

When the diagnostics system detects an error, a two-byte hexadecimal code is displayed. The first byte of this code is the class of error; the second byte is the subclass. The error code class generally corresponds to a specific hardware system or group of systems. For example, the first class (01) is used for the system board, so error 0108 indicates a system board error regarding the 8253 counters.

3-25


Table 3-1. Error Codes

Code Class Failure Type

0101 DMA registers 0102 DMA memory move 0103 Interrupt mask 0104 Hot interrupt line 0105 Stuck NMI 0106 Process registers 0107 System board System timer 0108 8253 counters 0109 System timer interrupts (1) 010A System timer interrupts (2) o lOB Processor flags 0110 CMOS memory 0111 Real time clock 0120 BIOS checksum

0701 Keyboard Controller 0702 Keyboard map

1001 Co-processor Registers 1002 Calculations

1701 Text attributes 1702 Background colors 1703 Character set 1704 Text page registration 1705 Text pages 1706 Graphics display 1707 Video EGAIVGA palette 1708 Memory 1709 VGA sequencer 170A VGA controller registers 170B VGA attribute controller 170C VGA DAC 1730 Cannot initialize video

2001 Baud rate clock 2002 Serial Internal loopback data 2003 Internalloopback control 2004 External loopback data

3-26

Code

2701 2702 2703 2704 2705 2706 2707 2708

3001 3002 3003

3701 3702 3703 3704 3705 3706 3707 3708 3709 370A 370B 370C 370D 370E 3710 3711 3720 3740 3750 3780 37BB 37CC 37EO 37FF

Table 3-1. Error Codes (continued)

Class Failure Description

Registers read/write Control loopback Printed pattern

Parallel Printer not ready Unknown error No paper/paper jam Printer timeout Printer busy

Address lines Memory Data patterns

Walking bits

Invalid parameter Address mark not found Write protect error Sector not found Reset failed Change line active Drive parameter error DMA overrun Attempt to DMA across 64 K Bad sector flag found

Disk Bad cylinder detected Media type not found Invalid format sectors count Control data mark detected CRC or ECC error detected ECC corrected error General controller failure Seek operation Change line test Drive not ready Undefined error occurred Write fault on selected drive Status error Sense operation failed


3-27

Chapter 4 - PROGRAMMING

4.1 INTRODUCTION

The XVME-678/688 is fully PCI AT compatible, and runs a wide range of software designed for 'the IBM PCI AT. Because it is designed to meet both PCI AT and VMEbus standards, its programming capabilities exceed that of either a typical PCI A T or VMEbus processor.

This chapter provides information needed to program the XVME-678/688 module. The information is presented as follows:

• Module memory maps (as seen by the CPU) • DRAM, EPROM memory • Real Mode Window accesses • 1/0 port addresses, registers, and descriptions • Interrupts • Byte-swapping • System resource functions • CMOS RAM

4.2 XVME-678/688 MEMORY MAPS

Figures 4-1 through 4-5 on the following pages show the XVME-678/688 1, 2, 4, 10, and 16 Mbyte memory maps as they appear to the on-board processor.

4-1

Chapter 4 - Programming

FEOOOO-FFFFFF

160000-FDFFFF

100000-15FFFF

OFOOOO-OFFFFF

OEOOOO-OEFFFF

ODOOOO-ODFFFF

OCBOOO-OCFFFF

OCOOOO-OC7FFF

OAOOOO-OBFFFF

0000OO-09FFFF

System BIOS 128K

1/0 Memory 14848K

DRAM* 384K

System BIOS 64K

Real Mode Wndow I Extended BIOS I 1/0 64K

Extended BIOS / I/O 64K

User Area 32K

VGABIOS 32K

VGA DRAM Memory 128K

DRAM 640K

*The 384 K of Extended DRAM is only available when no BIOS is shadowed.

Figure 4-1. 1 Mbyte Memory Map (as seen by the CPU)

4-2

FEOOOO-FFFFFF

20000-FDFFFF

100000-1 FFFFF

OFOOOO-OFFFFF

OEOOOO-OEFFFF

ODOOOO-ODFFFF

OCBOOO-OCFFFF

OCOOOO-OC7FFF

OAOOOO-OBFFFF

000000-09FFFF

System BIOS 128K

I/O Memory 14208K

DRAM 1024K

System BIOS 64K


Real Mode VVindow / Extended BIOS / I/O 64K

Extended BIOS / I/O 64K

User Area 32K

VGABIOS 32K


DRAM 640K


4-3


FEOOOO-FFFFFF System BIOS 128K

400000-FDFFFF 1/0 Memory 12160K

100000-3FFFFF DRAM 3072K

OFOOOO-OFFFFF System BIOS 64K

OEOOOO-OEFFFF Real Mode Wndow I Extended BIOS 11/0 64K

ODOOOO-ODFFFF Extended BIOS I 110 64K

OCBOOO-OCFFFF User Area 32K

OCOOOO-OC7FFF VGA BIOS 32K

OAOOOO-OBFFFF VGA DRAM Memory 128K

00000O-09FFFF DRAM 640K


4-4

FEOOOO-FFFFFF

AOOOOO-FDFFFF

100000-9FFFFF

OFOOOO-OFFFFF

OEOOOO-OEFFFF

ODOOOO-ODFFFF

OCBOOO-OCFFFF

OCOOOO-OC7FFF

OAOOOO-OBFFFF

00000O-09FFFF

System BIOS 128K

110 Memory 6016K

DRAM 9216K

System BIOS 64K


Real Mode VVindow I Extended BIOS 11/0 64K

Extended BIOS 1110 64K

User Area 32K

VGAB/OS 32K


DRAM 640K


4-5


FEOOOO-FFFFFF System BIOS 128K

100000-FEFFFF DRAM 3072K

OFOOOO-OFFFFF System BIOS 64K

OEOOOO-OEFFFF Real Mode Wndow I Extended BIOS I lID 64K

ODOOOO-ODFFFF Extended BIOS I lID 64K

OC8000-0CFFFF User Area 32K

OCOOOO-OC7FFF VGABIOS 32K

OAOOOO-OBFFFF VGA DRAM Memory 128K

000000-09FFFF DRAM 640K


4-6

4.2.1 I)IlAJ\{


The XVME-678/688 is available with 0, 1, or 4 Mbytes of DRAM, and can be expanded to 2, 10, or 16 Mbytes of DRAM.

1 Mbyte M2nvry The 1 Mbyte DRAM is divided into 640 and 384 Kbyte blocks for CPU accesses when the Shadow RAM option is not enabled. The 640 Kbyte block resides from 000000-09FFFF; the 384 Kbyte block from 100000-15FFFF. If the shadow RAM option is enabled, the DRAM is reduced to the lower 640 Kbytes of DRAM.

2 Mbytes M2nvry The 2 Mbyte version has 1.64 Mbytes of DRAM divided into 640 Kbyte and 1 Mbyte blocks. The additional 384 Kbytes of DRAM are dedicated for Shadow RAM and are not relocatable. Because this configuration uses only two SIMMs, there is no interleaving. This configuration tends to be less optimal for performance than the other memory configurations.

4 Mbytes Menvry The 4 Mbyte version has 3.64 Mbytes of DRAM divided into 640 Kbyte and 3 Mbyte blocks. The additional 384 Kbytes of DRAM are dedicated for Shadow RAM and are not relocatable.

10 Mbytes M2nvry The 10 Mbyte version has 9.64 Mbytes of DRAM divided into 640 Kbyte and 9 Mbyte blocks. The additional 384 Kbytes of DRAM are dedicated for Shadow RAM and are not relocatable. Because this configuration uses two SIMMs of different sizes, there is no interleaving. This configuration tends to be less optimal for performance than the others.

16 Mbytes Menvry The 16 Mbyte version has 15.64 Mbytes of DRAM divided into 640 Kbyte and 15 Mbyte blocks. The additional 384 Kbytes of DRAM are dedicated for Shadow RAM and are not relocatable.

4-7


4.2.2 EPROM

The XVME-678/688 has one 256Kx8 EPROM. This EPROM can represent the entire IBM BIOS range. The EPROM memory map is shown in Figure 4-6 below:

Device Address

30000-3FFFFF

20000-2FFFF

1000-1FFFF

08000-0FFFF

0000O-07FFF

System BIOS 64K

Diagnostics 64K

System BIOS 64K

User Area 32K

Video BIOS 32K

System Address

FOOOO-FFFFF

EOOOO-OEFFFF

DOOOO-DFFFF

C8000-CFFFF

COOOO-C7FFF

Figure 4-6. EPROM Memory Map

See Section 2.6 for instructions on removing this EPROM to install extended BIOS.

4-8


4.3 ACCESSING VMEbus MEMORY SPACE USING THE REAL MODE WINDOW

The Real Mode Window is 64 Kbytes long and resides within addresses OEOOOO-OEFFFF. It provides a means of addressing the VMEbus Short 110 and Standard memory spaces. The window can be software configured to address one of four entities: VMEbus Short 110 space, VMEbus Standard address space, VMEbus lACK space, and EPROM.

The window is controlled by bits 5 and 6 of Control Register 1 (see Section 4.6.1). The next four sections describe how the window operates for each configuration.

4.3.1 EPROM

This mode is selected after reset and is compatible with the IBM PC/AT architecture. When the window is configured for EPROM, the off-board EPROM (if one exists) appears in the window. The on-board EPROM is only accessed under the following two conditions:

• Bits 05 and 06 in Control Register 1 are set to 0 to allow an EPROM access. • The on-board EPROM is enabled through the Extended BIOS Setup Menu (see Section 3.3.1 for

more information).

NOTE To access the VMEbus, bit 0 of Control Register 3 must be set to o.

4.3.2 VMEbus lACK Space

When the window is configured for the VMEbus lACK space, a byte read from specific addresses within the window causes the XVME-678/688 to perform a VMEbus lACK cycle. The data returned from the byte read is the status 10 vector returned from the responding VMEbus interrupter.

4-9


The VMEbus interrupt level acknowledged is determined by the window address read, as shown below:

Window Address VMEbus Interrupt Level

OEOO03 1 OEOO05 2 OEOO07 3 OEOO09 4 OEOOOB 5 OEOOOD 6 OEOOOF 7

4.3.3 VMEbus Short 110 Space

When the window is configured for VMEbus Short 110, the entire 64 Kbyte Short 110 address space can be accessed through the 64 Kbyte window. Any references to the window map into the VMEbus Short I/O space with the CPU's lower 16 address bits being used as the VMEbus 16-bit address.

Example:

4-10

This example uses the MS-DOS Debug program to display and alter memory in the VMEbus Short 110 memory space. The example displays memory at Short 110 address 1000H and modifies memory location 1081H.

DEBUG -030 26

-D EOOO: 1000 -EEOOO: 1081 03 -030 06

;Enter Debugger ;Write to the Control Register to enable the Short I/O ;Address Space in the Real Mode Window

;Display Short I/O memory beginning at location 1000H ;Enter the value 03 at Short 110 address 108lH ;Write to Control Register port to set Real Mode Window ;back to EPROM

4.3.4 VMEbus Standard Address Space


When the window is configured for VMEbus Standard address space, the 64 Kbyte window can be used to access any 64 Kbyte block of the Standard VMEbus address space. In this mode, the 16 Mbyte Standard Address Space is logically divided into 256 64-Kbyte blocks. During these VMEbus accesses, the CPU's lower 16 address bits are used as the lower VMEbus address bits. The upper 8 VMEbus address bits used for the cycle are obtained from the 8-bit VMEbus HI Address Register (VME_HI_ADD). This register is an output port to the CPU and resides at 110 address 34h.

Before accessing the window in this mode, the upper 8 VMEbus address bits must be written to VME_HI_ADD. This defines which 64-Kbyte block of the Standard VMEbus address space will be accessed. Subsequent accesses to the window will use the 8 bits in VME_HI_ADD and the lower 16 bits of the CPU's address to form the 24 bit VMEbus address.

For example, to read word 123456h in the VMEbus Standard address space, configure the window for VMEbus Standard address space, output 12h to VME_HI_ADD (110 address 34h), and do a word read at address OE3456H. The word will be read from VMEbus address 123456h.

4-11


4.4 VMEBUS MASTER INTERFACE

The VMEbus master interface allows the XVME-678/688 to become a master or interrupt handler on the VMEbus. The master interface is disabled or enabled in Control Register 3 (3CH). The master interface is invoked whenever the CPU accesses the VMEbus Standard address space, the Short I/O address location, or the lACK address location. All accesses over the VMEbus are through the Real Mode Window (described in Section 4.3).

VMEbus cycles may be terminated with BERR or DTACK (see Figure 4-7). Circuitry is provided to allow BERR detection as either an 110 channel check error or as IRQ 10. Bit 0 in Control Register 4 (3DH) determines where local bus error interrupts are mapped i{enabled. Refer to Section 4.7.1 if the BERR signal is mapped onto IRQlO.

Circuitry inside this box is non·standard hardware added to allow BERR detection. All circuitry outside the box is standard IBM AT hardware. It is shown for reference only.

r---------------------------------------10CHCK .. -~----a ~-----~

BERR*---a

CONREG5_0 ------I ""'---IS

Bit 0 of STATUS 1

a~~----_r~-----------~

R

--------. -----------------------------1

Bit 3 of ----0 >---........ --------------------------Cl R I/O Port B

STATUS 1 = 1I032H

Bit 6 of 1/0 Port B

Q~~----------~~

110 Channel ErrorNMI

Bit 7 of I/O Port 70H ----0 >--------------------------------------------1

Figure 4-7. BERR Mapped Onto 10CHCK*

4-12


If the bus error interrupt is enabled (bit 0 in Control Register 5 is set to 1) and mapped to the IOCHCK* signal, asserting BERR has the same effect as a parity error on the I/O channel. The BERR signal is linked into the IBM AT architecture in the same manner as the IOCHCK* signal. Bit 3 of I/O port B (I/O address 61H) enables the IOCHCK* and BERR* signals.

When enabled, the assertion of BERR during an XVME-678/688 master cycle causes a latch to set. The status of this latch can be detected by bit 0 of Status Register 1. If this bit is 1, the BERR latch is set and generating an I/O channel error NMI. If this bit is 0, the latch is cleared. If the bit is 1, bit 6 of I/O port B is set to indicate an I/O channel error. To reset the latch, set bit 3 of the AT's port B to 1. To disable the BERR signal from causing I/O channel errors, set bit 0 of Control Register 5 to O.

All master cycles are byte-swapped during read and write operations. (Refer to Section 4.8 for more information on byte-swapping.)

The XVME-678/688 offers a Release on Request Option (ROR) which can be selected in Control Register 6 (3FH). When ROR is selected, the XVME-678/688 keeps the bus after it makes an access until another master requests to use the bus. This option reduces the number of arbitration cycles on the VMEbus when there is a limited number of masters. This increases the VMEbusthroughput.

NOTE If the bus is obtained by using bit 3 of Control Register 1 (30h), the ROR option will not release the VMEbus until bit 3 is negated.

To change the bus request level, the XVME-678/688 must lock onto the bus. Bit 3 of Control Register 1 (30h) and bit 4 of status register 2 (33h) are used in this procedure. When bit 3 of Control Register 1 is set to 1, the VMEbus master interface requests the bus. Bit 4 of status register 2 can then be polled to determine when the master interface has been granted ownership. When bit 4 is set to 1, the master interface does not have ownership. When bit 4 is set to 0, the master interface has ownership. Once the master interface gets ownership of the bus, it won't release it until bit 3 of Control Register 1 is reset by the 80386SX.

To change the Bus Request Level of the XVME-678/688, follow the steps below:

1. Set bit 3 of Control Register 1 (30H) to 1.

2. Poll bit 4 of status register 2 (33H) and wait until it becomes O.

3. Change the Bus Request Level by writing to Control Register 6 (3FH).

4. Set bit 3 of Control Register 1 to O.

4-13


NOTE The XVME-678/688 will not give up the VMEbus for the duration of step 3 even if the ROR option is selected.

This method may also be used to guarantee multiple consecutive VMEbus cycles by changing step 3 to VMEbus master cycles.

4.5 SHADOW RAM OPTION

Shadowing is the process of loading the BIOS from EPROM into DRAM after power-up. Both the System and VGA BIOS can be shadowed into DRAM to increase system performance.

On the 1 Mbyte version of the XVME-678/688, the 384 Kbytes of DRAM can be used to shadow the BIOS or can be relocated to the address above the EPROMs as DRAM. The 2, 4, 10, and 16 Mbyte versions of the XVME-678/688 always allocate 384 Kbytes of DRAM for shadowing the BIOS.

Because shadowing the BIOS increases system performance, the XVME-678/688 is factory-shipped with the System BIOS and the Video BIOS shadowed.

Refer to Section 3.3.1.13 for more information on shadowing.

4-14


4.6 110 PORT ADDRESSES

The XVME-678/688 110 map contains all IBM PC/AT architecture 110 ports, plus ten 110 ports at 110 address spaces 30H-34H 36H, and 3CH-3FH. Standard PC/AT 110 addresses are shown in Table 4-1 below. The additional 8-bit 110 ports are listed in Table 4-2 on the next page.

Table 4-1. 110 Address Map

Hex Range Port

000-01F DMA Controller 1, 8237 A-5 Equivalent 020-021 Interrupt Controller 1, 8259 Equivalent 022-023 Chips & Technology Register Set-up 024-02F Interrupt Controller 1, 8259 Equivalent 030-03F VMEbus Interface Control and Status Registers 040-05F Timer, 8254-2 Equivalent 060-06F 8742 Equivalent (Keyboard) 070-07F Real Time Clock bit 7 NMI Mask 080-09F DMA Page Resistor OAO-OBF Interrupt Controller 2, 8259 Equivalent OCO-ODF DMA Controller 2, 8237 A-5 Equivalent OEO-OEF Available OFO Clear Math Co-processor Interrupt 13 OF1 N/A OF2-0FF Math Co-processor 100-lEF Available 1FO-1F7 IDE Controller (AT drive) 1F8-277 Available 278-27F Parallel Port 2 (see note) 280-2F7 Available 2F8-2FF Serial Port 2 (see note) 300-36F Available 370-377 Alternate Floppy Disk Controller (see note) 378-37F Parallel Port 1 (see note) 380-3BF Available 3CO-3CF VGA/EGA 3DO-3EF Available 3FO-3F7 Primary Floppy Disk Controller 3F8-3FF Serial Port 1 (see note)

NOTE Because serial and parallel port addresses can be changed and disabled, they may not be used for all applications. The XVME-678/688 is shipped with serial ports 1 and 2 and parallel port 1 enabled at the address specified.

4-15


Table 4-2. 110 Addresses Unique to the XVME-678/688

Address Port Access

30H Control Register 1 IN/OUT 31H Auxiliary Interrupt IN only 32H Status Port 1 IN only 33H Status Port 2 IN only 34H VME HI Address IN/OUT 36H Control Register 2 IN/OUT 3CH Control Register 3 IN/OUT 3DH Control Register 4 IN/OUT 3EH Control Register 5 IN/OUT 3FH Control Register 6 IN/OUT

NOTE The default setting for all control register bits at power-up is O.

The following sections discuss these ten 110 ports.

4-16


4.6.1 Control Register 1 (CO NREG 1, Port Address 30H)

This read/write port controls many module functions. All bits of this port are set to zero when the module is reset. The bits of this register are described below.

DO is set to 0 and is reserved and read-only

D 1 controls the FAIL LED o = FAIL LED is on, XVME-678/688 asserting SYSFAIL if SW1, position 3 is closed (refer

to Section 2.3) 1 = FAIL LED is on, XVME-678/688 not asserting SYSFAIL

D2 controls the PASS LED o = PASS LED is off 1 = PASS LED is on

D3 gives the instruction to the VMEbus requester o = release the VMEbus 1 = acquire and retain ownership of the VMEbus

D4 sets the Auxiliary NMI sources status (VME SYSFAIL *, VME Local BERR *, and ABORT switch) o = disable 1 = enable

D5,D6 determine the Real Mode Window access type

EPROM Access VMEbus Short I/O Access VMEbus Standard Access VMEbus lACK Cycle

D6 o o 1 1

D5 o 1 o 1

D7 sets the Auxiliary Maskable Interrupt status (VME interrupts 1 through 7) o disable 1 = enable

NOTE AMls must be disabled before toggling bit D7 of this register. Refer to Section 4.7.1 for instructions on how to disable interrupts.

4-17


4.6.2 Auxiliary Interrupt (AUX_INT, Port Address 31H)

This read-only port shows which auxiliary interrupts are pending.

DO is always low

D1-D7 define the status of the seven VMEbus interrupts. Bit numbers correspond to the interrupt levels (i.e., bit 5 gives the status of VMEbus interrupt 5). o = not pending 1 = pending

4.6.3 Status Register 1 (STATUS1, Port Address 32H)

Bits DO through D3 of this read-only port give the interrupt latch status. The bits of this register are described below. When DO through D3 are set to 1, the latch is set. When DO through D3 are set to 0, the latch is not set.

DO gives the BERR 110 channel error latch status

D 1 is reserved as read only and is set to 0

D2 gives the SYSF AIL auxiliary NMI latch status

D3 gives the ABORT switch NMI latch status

D4-D7 are reserved, read-only, and set to 0

4-18


4.6.4 Status Register 2 (STATUS2, Port Address 33H)

The bits of this read-only port are described below.

00-03 are reserved, read-only, and set to 0

04 indicates whether the VMEbus requester has ownership of the VMEbus o = yes 1 = no

05 defines the status of the VMEbus signal SYSF AIL o = asserted 1 = not asserted

06,07 are reserved, read-only, and set to 1

4.6.5 VMEbus m Address (VME_HI_AOO, Port Address 34H)

This read/write port is used to provide the upper 8 address bits (A16-A23) when the VMEbus Standard address space is accessed through the Real Mode Window (refer to section 4.3.4).

4.6.6 Control Register 2 (CONREG2, Port Address 36H)

This register is used to control the AM2 bit for VME accesses and the ROM DOS boot option.

DO is reserved, read-only, and set to 0

01 gives the AM2 setting on VMEbus access o = set to 0 (non-privileged) 1 = set to 1 (supervisory)


4-19


4.6.7 Control Register 3 (CONREG3, Port Address 3CH)

This register is used to control various features. All bits in this port are set to zero when the module is reset. Each bit is described below.

DO gives the VMEbus master interface status o = enable 1 = disable

Dl gives the status of the Program FLASH BIOS (future use) o = disable ' 1 = enable


4.6.8 Control Register 4 (CONREG4, Port Address 3DH)

This register enables the seven VMEbus interrupts which cause IRQIO to interrupt the CPU as individual entities. Bit 0 of this register implements a new function which is the mapping of the auxiliary NMIs (ABORT and SYSFAIL) and VME BERR onto IRQlO.

DO determines where the auxiliary interrupt occurs o = Aux NMIs on NMI interrupt 1 = Aux NMIs on IRQI0

DI-D7 enables/disables its corresponding interrupt level o = disable 1 = enable

Dl controls VME(IRQl)

D2 controls VME(IRQ2)






4-20

4.6.9 Control Register 5 (CONREG5, Port Address 30H)


This control register is used to enable Auxiliary Non maskable interrupts. If the auxiliary NMIs are mapped onto IRQ1O, then enable bits 0-2 become the clearing mechanism for the interrupt.

DO determines whether local bus error causes NMI o = does not cause NMI 1 = causes NMI

01 determines whether VMESYSFAIL causes NMI o = does not cause NMI 1 = causes NMI

02 determines whether ABORT switch causes NMI o = does not cause NMI 1 = causes NMI


4.6.10 Control Register 6 (CONREG6, Port Address 3FH)

Control Register 6 is used to set the bus request and acknowledge level and to offer a Release on Request (ROR) option. When the system resource switch is in the on position, bus request level 3 is chosen regardless of the bit pattern in DO and 01.

00,01 choose the bus request level DO Dl o 0 Level 3 1 0 Level 2 o 1 Level 1 1 1 Level 0

02 selects type of release o = Normal release 1 = Release on request

03 is a read-only bit that reflects the position of the system resource switch o = not system resources 1 = system resources


4-21


4.7 INTERRUYfS

The XVME-678/688 handles interrupts on the VMEbus. In addition to the interrupts generated by the PCI AT peripheral chips, the XVME-678/688 handles the following interrupts:

• VMEbus interrupts • Auxiliary maskable interrupts (VMEbus interrupts; BERR, SYSF AIL, ABORT switch mapped

to IRQ1O) • Auxiliary non-maskable interrupts (ABORT switch and SYSFAIL mapped to NMI (IOCHCK*»

All seven VMEbus interrupt levels can interrupt the XVME-678/688 (refer to Figure 4-8 on the next page). Each VMEbus interrupt level has a separate enable bit located in Control Register 4 (3DH). When this enable bit is set to 1, the interrupt is enabled. When the enable bit is set to 0, the interrupt is disabled. (Refer to section 4.6.8.)

Each VMEbus interrupt line has a bit position in the AUX_INT input port (see section 4.6.2). VMEbus interrupt level 1 corresponds to AUX_INT bit position 1. When a particular bit in AUX_INT is set, the corresponding VMEbus interrupt is pending. The XVME-678/688 should run a VMEbus lACK cycle on the corresponding interrupt level (refer to section 4.3.2) to satisfy the VMEbus protocol and to acquire the status ID vector. Software should ensure the VMEbus interrupter has negated its interrupt before leaving the ISR.

4.7.1 Auxiliary Maskable Interrupts (AMIs)

Ten maskable interrupts have been added to the basic IBM PCI AT architecture. They consist of the seven VMEbus interrupts, BERR, SYSFAIL, and the ABORT switch (refer to Figure 4-8 on the next page). The seven VMEbus interrupts are always mapped to IRQI0. SYSFAIL, BERR, and the ABORT switch can be mapped to IRQ 10 or the ANMI structure. None of these three can cause interrupts on both IRQ 10 and the ANMI.

All seven VMEbus interrupt AMls are disabled by bit 7 of Control Register 1 (30H). Bit 0 of Control Register 4 determines whether BERR, SYSFAIL, and the ABORT switch are mapped onto IRQI0 or the ANMI structure.

If these interrupts are mapped onto IRQ1O, the clearing and enabling mechanism is the enable/disable bit in Control Register 5 (see Figure 4-9 on page 4-24). For example, if an interrupt (IRQ1O) was caused by BERR, the interrupt event is determined by reading Status Register 1. It is cleared by setting bit 0 of Control Register 5 to O. The control bit may then be set back to 1 to re-enable.

4-22

VMEbus Interrupts

IRQ7·

CONREG4_7

IRQ6·

CONREG4_6

IRQS·

CONREG4_S

IRQ4·

CONREG4_4

IRQ3·

CONREG4_3

IRQ2·

CONREG4_2

IRQ1·

CONREG4_1

1 -l

'1

1 ---i

Aux _Int Input Port

Inverter Buffer

I/O 31 h

'1 D-1

~

1

1

Bit 7 of I/O port CONREG1

CONREG4_1 = Control Register 4 bit 1 Control Register 4 = I/O 3Dh

Figure 4-8. Auxiliary Maskable Interrupt Structure


D7 D6 DS D4 D3 D2 D1 DO

AT-bus Interrupt

IRQ10

4-23


SYSFAIL* S

CONREG5_1

R

Abort Toggle

S

R

)-----IS

L.-------a R

CONREG5_2 .. Control Register 5 bit 2 Control Register 5 = I/O 3Eh

0

0

SYSFAIL NMI

LATCH

ABORT NMI

LATCH

BERR NMI

LATCH

STATUS 1_2

1/0 32h

STATUS1_3

AT-Bus Interrupt

IR010

Note: This is internally OReeI with the VMEbus interrupts to create IR010

4-9. BERR, SYSFAIL, and ABORT Switch Mapped on IRQI0

4-24

4.7.2 Auxiliary Non-Maskable Interrupts


Two non-maskable interrupts (ANMls) have been added to the basic IBM PCI A T architecture: the ABORT switch and SYSFAIL (see Figure 4-10).

The IBM PCI A T architecture provides a mechanism to disable and enable NMls: an output to port 70H with D7 =0 enables NMls; an output to port 70H with D7 = 1 disables NMls. This mechanism is also used to enable and disable the ANMls. Both ANMls are implemented as latches. When the interrupt occurs and is enabled, the latch will set. The latch remains set until the interrupt is disabled or a system reset occurs.

SYSFAIL and the ABORT switch are mapped onto the NMI by setting bit 0 on Control Register 4 to O. SYSFAIL and the ABORT switch are enabled by setting bit 4 of Control Register 1 to 1 and by enabling the individual interrupt enable in Control Register 5. If bit 4 is on and at least one of the individual enables in Control Register 5 is on, the occurrence of the interrupt event will set a latch, which remains set until bit 4 is reset.

When the latch is set, the NMI will occur if the module NMI (bit 7 of port 70H) is enabled. The state of these latches can be determined by checking Status Register 1 (32H). The SYSFAIL latch is bit 2 and the ABORT switch latch is bit 3. When any of these bits is high, the corresponding latch is set.

Bit 0 of CONREG4 = 0

}-----IS

R

J--I---IS

R

Bit 7 of Output Port 70h

IBM AT NMI

CONREGS_2 - Control Register 5 bit 2 Control Register 5 • I/O 3 Eh

Q~_~ ___ S_T_Aru_S_l~_2~

SYSFAIL NMI

LATCH

ABCAT NMI

LATCH

I/O 32h

Figure 4-10. Auxiliary Non-maskable Interrupt Structure

NMI

4-25


4.8 BYTE-SWAPPING

Byte-swapping is the method the XVME-678/688 uses to transfer data to and from the VMEbus, despite their different byte-ordering schemes. The CPU processor on the XVME-678/688 follows the Intel byteordering scheme, while the VMEbus follows the Motorola byte-ordering scheme. The difference is illustrated below.

4.8.1 Byte-Ordering Schemes

The Intel family of processors stores data with the least significant byte located at the lowest address and the most significant byte at the highest address. The Motorola family stores data exactly opposite, with the least significant byte located at the highest address and the most significant byte at the lowest address. This fundamental difference is illustrated in Figure 4-11, which shows a 32-bit quantity stored at address "M" by both architectures:

4-26

Address INTEL MOTOROLA

Low Byte M High Byte

• M+1 • • • • M+2 • • •

High Byte M+3 Low Byte

Figure 4-11. Byte-Ordering Schemes

NOTE The two architectures differ only in the way they store data into memory, not in the way they place data on the shared data bus.

4.8.2 Address Consistency


Address consistency refers to the situation where the data byte at both the XVME-678/688 and VMEbus addresses is the same for each byte address. In other words, the XVME-678/688 and VMEbus memory images appear the same. Address consistency is desirable for byte-oriented data such as strings or video image data. Consider the example below of transferring the string "Text" to VMEbus memory using a 32-bit transfer (Note that the 80386SX/486SLC/e processor splits the 32-bit transfer into two 16-bit transfers) :

First 16-Bit Transfer

80386SX Byte-swapping VME

Data Bus Hardware Data Bus

Address D15

I ::< I D15 Address

I I M 'T' D8 D8 'T' M

M+1 'e' D7 D7 'e' M+1 I I

M+2 'x' DO DO M+2

M+3 't' M+3

XVME·678/688 VMEbus Memory

Second 16-Bit Transfer

Address Address

M 'T' 80386SX Byte-swapping VME M

Data Bus Hardware Data Bus

M+1 'e' D15

I ::< I D15 M+1

I I M+2 'x' D8 D8 'x' M+2

M+3 't' D7 D7 't' M+3 I I

XVME·678/688 DO DO VMEbus Memory

Figure 4-12. Maintaining Address Consistency

Notice that the data byte at each address is identical. To achieve this, the data bytes needed to be swapped as they were passed from the 678/688 internal bus to the VMEbus. The XVME-678/688 incorporates byte-swapping automatically in hardware. No software concern is necessary if address consistency is desired.

4-27


4.8.3 Numeric Consistency

Numeric consistency refers to the situation where the byte-ordering schemes described above must be followed to maintain the value of a 16-bit or 32-bit quantity. Numeric consistency is desired for transferring integer data, floating point data, pointers, etc. Consider the long word value 12345678H stored at address "M" by both the XVME-678/688 and the VMEbus:

Address

78 M 12

56 M+1 34

34 M+2 56

12 M+3 78

XVM E -678/688 VMEbus

Figure 4-13. Maintaining Numeric Consistency

Notice that the internal data storage scheme for the Intel machine is different from that of the VMEbus (i.e., the byte "78" is stored at location M in the Intel machine, while "78" is stored at location M + 3 on the VMEbus due to the inherent specification of each bus). However, the data bus connections are the same between architectures and therefore the data must be passed straight through.

4-28


To maintain numeric consistency, the bytes of a 16-bit or 32-bit quantity must be swapped in software prior to transferring them to the VMEbus, or afterward if the data has been read from the VMEbus. The following code example illustrates this necessity:

value equ CONREG 1

mov

12345678h equ 30h

aX,OEOOOh mov eS,ax

in al,CONREG_1 and al,9Fh or al,40h out CONREG_1,al

mov xchg ror xchg

mov

eax,value ah,al eax,16 ah,al'

es:[O],eax

;Point to Real Mode Window

; Select VMEbus Standard address space

;Read value into register ;Swap low-order bytes ;Swap the words ;Swap high-order bytes (EAX=78563412h)

;32-bit transfer to VMEbus

4-29


4.9 SYSTEM RESOURCE FUNCTIONS

System resource functions are provided by a switch. The switch controls enabling of the lACK daisy chain driver, BERR timeout, the arbiter, and the SYSCLK driver. The bus error timeout assertion occurs 16 usec after the data strobes. The switch position can be read back in Control Register 6 (3FH).

The module is reset by VME SYSRESET* or the Vcc going out of tolerance. The module will assert VME SYSRESET* in one of two conditions:

• Vcc is out of tolerance and switch SW1, position 1 is closed.

Or

• The toggle switch is toggled down and switch SW1, position 2 is closed.

See Figure 4-14 for a block diagram of the reset structure.

8-POSITION SWITCH

DC+5V Monitor RESET*

rcx:n.E IL.--_--i SWITCH TRESET*

4-30

VMESYSRESET*

- ~ Local CPU RESET* L.--__ ----I~

Figure 4-14. Reset Structure

4.10 CMOS RAM


The XVME-678/688 has 128 bytes of battery-backed RAM located on the 82C206 chip. The RAM is accessed by first placing the index value on the data bus. It is recommended that the address 070H be used to strobe the index. To do this, write to port 70H with the index value. The RAM may then be written to or read from port 071H.

Index Function

OOH-3FH AT configuration

40H-7FH Xycom configuration

Observe caution when writing the index value to port 070H, because bit 7 is the NMI enable bit. If a 0 is placed in bit 7 the NMI will be enabled; if a 1 is placed in bit 7 the NMI is disabled.

Writing to CMOS RAM involves two steps:

1. Out to port 70H with the CMOS address to which data will be written 2. Out to port 71H with the data to be written

Reading CMOS RAM involves two steps:

1. Out to port 70H with the CMOS address from which data will be read 2. In from port 71H, and the data read is returned in the AL register

Table 4-3 on the next page shows the CMOS RAM address map.

4-31


Table 4-3. CMOS RAM Address Map

Address Description

OO-OD Real time clock information DE Diagnostic status byte OF Shutdown status byte 10 Diskette drive type byte - drives A and B 11 Reserved 12 Fixed disk type byte 13 Reserved 14 Equipment byte 15 Low base memory byte 16 High base memory byte 17 Low expansion memory byte 18 High expansion memory byte 19 Disk C extended byte lA Disk D extended byte

lB-2D Reserved 2E-2F 2-byte CMOS checksum

30 Low expansion memory byte 31 High expansion memory byte 32 Date century byte 33 Information flags (set during power on) 34 Reserved

35-3F Reserved 40-53 Extended CMOS

54 Reserved 55-77 Reserved 78-7D Reserved 7E-7F Extended CMOS checksum

4-32

Chapter 5 - XVME BIOS FUNCTIONS

5.1 XVME BIOS FUNCTIONS

The XVME-678/688 BIOS contains a series of functions that are accessible to user programs, to assist in configuring and using the VMEbus Interface Control and Status Registers. These functions spare the user from having to directly access and manipulate the XVME registers, and provide a compatibility buffer in case future XVME PCI AT register maps and bit definitions change. It is recommended that these functions, rather than direct access, be used.

The XVME BIOS functions are accessed via INT 15h function AFh (i.e., AH = AFh). In addition to the INT 15h interface, the Xycom BIOS Signature area includes a call entry point to the XVME BIOS functions. The individual function to be performed is identified by an 8-bit sub function number in AL. Subfunction numbers indicate the group (most significant hex digit of sub function number) and the index (least significant hex digit of subfunction number). When using the call entry, it is not necessary to load AH with AFh.

The following code fragment (in assembly) shows how to perform subfunction OOH (Identify XVME Model) using Interrupt 15h. This method is the easiest, but may not work when running in protected mode.

Failed:

MOV INT JC

AX,OAFOOH 15H Failed

5-1

Chapter 5 - XVME BIOS Functions

The following code fragment (in assembly) shows how to use the information returned by subfunction OOH (Identify XVME Model) to access the call entry for subfunction 01H (Get Real Mode Window Physical Segment). Using the call entry is faster than using Interrupt 15H but, again, may not work when running in protected mode.

Failed:

5-2

; The following three entries must remain in the same contiguous order ; and reside in the data segment. Call_Entry LABEL DWORD Call Offset DW? Call_Segment DW OFOOOH

; This code assumes that DS has been loaded properly and ; that static entries in the data segment have been set up properly. MOV AX,OAFOOH INT 15H JC Failed MOV Call_ Offset,CX MOV AL,01H CALL Call_Entry JC Failed


The following code fragment (in assembly) shows how to perform sub function OOH (Identify XVME Model) via the call entry point. This method should be used when running in protected mode. In this code fragment 'Seg_FOOO' is the segment descriptor for the physical segment FOOOH (in real-mode Seg_FOOO is FOOOH). Processes using the call entry must have execute privilege in Seg_ FOOO and privilege to access the 110 ports since the XVME BIOS functions perform such accesses.

More:

REP

Found:

; The following three entries must remain in the same contiguous order ; and reside in the data segment. Call_Entry LABEL DWORD Call Offset DW? -Call_Segment DW Seg_FOOO Signature DB 'XYCOMSIG'

; This code assumes that DS has been loaded properly and ; that static entries in the data segment have been set up properly. MOV ES,Seg_FOOO ; Search for signature in FOOO block XOR DI,DI

MOV SI,Offset Signature MOV CX,4 CMPSW JE ADD JC ADD JMP

ADD MOV

Found DI,lOH Not Found DI,OFFFOH SHORT More

DI,2CH-8 Call_ Offset,DI

; Call subfunction OOH MOV AL,OOH CALL Call_Entry JC Failed

; Compare 4 Words

; See if signature located ; Next paragraph boundary ; Don't go out of physical segment FOOO

; Calculate call entry point offset ; Save

Not Found:

Failed:

5-3


5.2 MISCELLANEOUS FUNCTIONS

This category of BIOS functions accesses information about the module, including the module 10, front panel LEOs, and Flash BIOS configurations.

5.2.1 Identify XVME Model

Within the system BIOS, a data table contains the module model number, the offset of the call entry point for the XVME BIOS functions, and the base address of the VM~bus interface configuration and status registers. When called, this function returns the value of these items in the data table. This information can then be used by application software to determine the configuration of the module.

Int ISh Function AFH

Call With:

Returns: If error:

If successful:

5-4

Subfunction OOH

AH = AFH AL = OOH

Carry Flag Set AH = Error Code 01 = "XY" Carry Flag Clear AH = 0 01 = "XY" BX = Model number CX = Offset of call entry point (segment of call entry point is FOOOh) OX = Base 110 address of XVME registers

5.2.2 Get Real Mode Window Physical Segment


This function returns the Physical Segment of PCI A T memory occupied by the Real Mode Window.


Call With:

Returns:

Subfunction OtH

AH = AFH AL = 0IH

If error: Carry Flag Set

If successful:

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = Physical segment of Real Mode Window

5-5


5.2.3 Get LED Configuration

This function indicates which state the front panel LEDs are in. Possible LED states are

Passed Testing Other Failed

Int I5h Function AFH

Call With:

Returns:

Green LED on, red LED off Green LED on, red LED on Green LED off, red LED off Green LED off, red LED on

Subfunction 03H

AH = AFH AL = 03H


If successful:

5-6

AH = Error Code D = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = Current LED configuration

0- Passed I - Testing 2 - Other 3 - Failed

5.2.4 Set LED Configuration

XVME·6781688 Manual July 1994

This function can be used to alter the state of the front panel LEDs. Possible LED states are

Passed Testing Other Failed

Green LED on, red LED off Green LED on, red LED on Green LED off, red LED off Green LED off, red LED on

The previous configuration is returned upon completion.


Call With:

Returns:

Subfunction 04H

AH = AFH AL = 04H BX = Desired LED configuration

o . Passed I • Testing 2· Other 3 . Failed


If successful:

Note:

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 01 = "XY" BX = Previous LED configuration

O· Passed I . Testing 2· Other 3 . Failed

The XVME·678/688 asserts the VMEbus SYSFAIL signal when the fail LED is on (Fail and Testing LED configurations) and Switch SWI position 3 is closed.

5·7


5.2.5 Get Flash BIOS Write Configuration

This function returns the state of the module's on-board Flash BIOS, if installed.


Call With:

Returns:

Subfunction 06H

AH = AFH AL = 06H


If successful:

Note:

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = Current Flash BIOS write configuration

0- Disabled 1 - Enabled

This routine should be used only if the module's BIOS socket contains a Flash memory device.

5-8

5.2.6 Set Flash BIOS Write Configuration


This function is used to enable or disable the Flash BIOS write logic. The previous configuration is returned upon completion.

Int 15h Function AFH

Call With:

Returns:

Subfunction 07

AH = AFH AL = 07H BX = Desired Flash BIOS write configuration



If successful:

Note:

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = Previous Flash BIOS write configuration


This function should be used only if the module's BIOS socket contains a Flash memory device.

5-9


5.3 REAL MODE WINDOW (RMW) FUNCTIONS

These functions provide access to the Real Mode Window configuration, which can be used to map any 64 Kbyte segment of the VMEbus address space into the Real Mode Window page of PCI A T memory. Section 4.3 contains an explanation of the Real Mode Window operation.

5.3.1 Get Real Mode Window Configuration

This function returns the VMEbus address space of the 64 Kbyte segment currently pointed to by the Real Mode Window.

lnt 1Sh Function AFH

Call With:

Returns:

Subfunction 10

AH = AFH AL = lOH


If successful:

5-10

AH = Error Code DI = "XY" Carry Flag Clear AH = a DI = "XY" BX = Current RMW address space

a-ROM 1 - VMEbus short 2 - VMEbus standard 3 - VMEbus lACK

CX = Current 64 Kbyte portion of VMEbus Standard Address Space mapped to RMW (if used)


5.3.2 Set Real Mode Window Configuration

This routine is used to configure which 64 Kbyte segment the Real Mode Window point~ to. The previous configuration is returned upon completion.

lnt I5h Function AFH

Call With:

Returns:

Sub function 11

AH = AFH AL = IIH BX = Desired RMW address space

0- ROM I - VMEbus short 2 - VMEbus standard 3 - VMEbus lACK

CX = Desired 64 Kbyte portion of VMEbus Standard Address Space mapped to RMW (if used)


If successful:

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = Previous RMW address space

0- ROM I - VMEbus short 2 - VMEbus standard 3 - VMEbus lACK

CX = Previous 64 Kbyte portion of VMEbus Standard Address Space mapped to RMW (if used)

5-11


5.4 AUXILIARY NON-MASKABLE INTERRUPT (ANMI) FUNCTIONS

The ANMI group consists of VMEbus signals BERR, SYSFAIL, ACFAIL, and the front panel Abort switch. Any of these signals can be configured to cause a Non-Maskable Interrupt (NMI) or an interrupt on IRQlO. The functions in this group can be used to configure and reset the ANMls. Sections 4.4.2 and 4.5 contain more information about AN MIs .

5.4.1 Get ANMI Group Configuration

This function returns whether the ANMls are configured to generate interrupts on NMI or IRQlO.


Call With:

Returns:

Subfunction 20

AH = AFH AL = 20H


If successful:

5-12

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = Current ANMI group configuration

Bit 0 0 - ANMI to use NMI 1 ANMI to use IRQI0

Bit 7 0 ANMI group disabled 1 ANMI group enabled

5.4.2 Set ANMI Group Configuration


The interrupt the ANMls generate-IRQ1O or NMI-can be set by calling this function. The previous configuration is returned upon completion.


Call With:

Returns:

Subfunction 21H

AH = AFH AL = 21H BX = Desired ANMI group configuration

Bit 0 0 - ANMI to use NMI 1 ANMI to use IRQ10



If successful:

Note:

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = Previous ANMI group configuration

Bit 0 0 - ANMI to use NMI 1 ANMI to use IRQ10


When enabled ANMls come in on NMI or IRQI0 (see sections 5.4.1 and 5.4.2), it is the responsibility of users to ensure that IRQ 10-if used-is enabled via the 8259 and that an appropriate interrupt handler or NMI handler is provided. MS-DOS allows users to directly manipulate the 8259 and the interrupt vector table. Other operating systems usually provide a service for attaching to and enabling specific PC/AT IRQs, but tend to be less flexible when dealing with NMls. Check the operating system documentation for proper NMI handling.

5-13


5.4.3 Get ANMI Mask

The current state of the ANMI source mask bits can be determined by calling this function.


Call With:

Returns:

Subfunction 22H

AH = AFH AL = 22H


If successful:

5-14

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = Current ANMI mask

Bit 0 0 - VMEbus BERR ANMI disabled 1 VMEbus BERR ANMI enabled

Bit 1 0 VMEbus SYSFAIL ANMI disabled 1 VMEbus SYSFAIL ANMI enabled

Bit 2 0 ABORT switch ANMI disabled 1 ABORT switch ANMI enabled

5.4.4 Set ANMI Mask


This function allows each of the ANMI sources to be enabled or disabled. The previous state of the ANMI source mask is returned.


Call With:

Returns:

Subfunction 23H

AH = AFH AL = 23H BX = Desired ANMI mask

Bit 0 0 - VMEbus BERR ANMI disabled I - VMEbus BERR ANMI enabled

Bit I 0 - VMEbus SYSFAIL ANMI disabled I - VMEbus SYSFAIL ANMI enabled

Bit 2 0 - ABORT switch ANMI disabled I - ABORT switch ANMI enabled


If successful:

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = Previous ANMI mask

Bit 0 0 - VMEbus BERR ANMI disabled I VMEbus BERR ANMI enabled

Bit 1 0 VMEbus SYSFAIL ANMI disabled I VMEbus SYSFAIL ANMI enabled

Bit 2 0 ABORT switch ANMI disabled I ABORT switch ANMI enabled

5-15


5.4.5 Get ANMI Status

When an ANMI is detected, a call to this function can be used to determine which source the interrupt is from. This function is also used to determine the current state of the VMEbus SYSFAIL and ACFAIL signals.


Call With:

Returns:

Subfunction 24H

AH = AFH AL = 24H


If successful:

5-16

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = ANMI status

Bit 0 0 - VMEbus BERR ANMI not pending 1 - VMEbus BERR ANMI pending

Bit 1 0 - VMEbus SYSF AIL ANMI not pending -1 - VMEbus SYSFAIL ANMI pending

Bit 2 0 - ABORT switch ANMI not pending 1 - ABORT switch ANMI pending

Bit 3 0 - VMEbus ACFAIL ANMI not pending 1 VMEbus ACFAIL ANMI pending

Bit 5 0 - VMEbus SYSFAIL signal currently asserted 1 - VMEbus SYSFAIL signal currently negated

5.4.6 Clear ANMI


Once the ANMI has been detected and properly processed, this routine can be called to clear the source of the ANMI.


Call With:

Subfunction 25H

AH = AFH AL = 25H BX = ANMIs interrupts to be reset

Bit 0 0 1

Bit 1 0 1

Bit 2 0 1

Returns: If error: Carry Flag Set

If successful:

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY"

- Do not clear YMEbus BERR ANMI - Clear VMEbus BERR ANMI - Do not clear VMEbus SYSFAIL ANMI - Clear VMEbus SYSF AIL ANMI - Do not clear ABORT switch ANMI - Clear ABORT switch ANMI

5-17


5.5 VMEbus MASTER FUNCTIONS

This category of functions allows programs to access the software configuration of the module's VMEbus Master interface. Functions are provided to read and modify the Master interface configuration and request VMEbus ownership. For more information on the master interface, refer to Section 4.8.

5.5.1 Get VMEbus Master Configuration

The information returned from this function provides programs with the current state of the VMEbus master interface, address modifier codes used for master cycles, the VMEbus request level used, and the VMEbus requester configuration.


Call With:

Returns:

Subfunction 30H

AH = AFH AL = 30H


If successful:

AH = Error Code DJ = "XY" Carry Flag Clear AH = 0 DJ = "XY" BX = Current VMEbus master configuration

5-18

Bit 0 0 1

Bit 2 0 1

Bit 3-4 00 01 10 11

Bit 5 0 1

- VMEbus master interface disabled - VMEbus master interface enabled - VMEbus master accesses non-privileged - VMEbus master accesses supervisory

VMEbus request level 3 VMEbus request level 2 VMEbus request level 1 VMEbus request level 0

- Release VMEbus when done - Release VMEbus on request


5.5.2 Set VMEbus Master Configuration

This function provides the ability to modify the configuration of the VMEbus master interface. Parameters that may be modified are the same as those mentioned in Section 5.5.1. The previous configuration of the master interface is returned upon completion.


Call With:

Subfunction 31H

AFH = 31H

AH AL BX = Desired VMEbus master configuration

Bit 0 0 1

Bit 2 0 1

Bit 3-4 00 01 10 11

Bit 5 0 1

Returns appear on the following page.

- VMEbus master interface disabled VMEbus master interface enabled

- VMEbus master accesses non-privileged - VMEbus master accesses supervisory



5-19



If successful:

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = Previous VMEbus master ·configuration

Note:

Bit 0 0 1

Bit 2 0 1

Bit 3-4 00 01 10 11

Bit 5 0 1

- VMEbus master interface disabled VMEbus master interface enabled

- VMEbus master accesses non-privileged - VMEbus master accesses supervisory



VMEbus Request Level cannot be changed when system resources are enabled. Also VMEbus request level and VMEbus release settings should only be changed when the VMEbus is owned by the XVME-678/688 (see sections 5.5.3 through 5.5.6 for VMEbus ownership functions).

5-20

5.5.3 Get VMEbus Ownership Configuration


This function returns the current state of the VMEbus ownership option. This function provides a way to determine if ownership of the VMEbus has been requested.

Int I5h Function AFR

Call With:

Returns:

Subfunction 32H

AR = AFH AL = 32H


If successful:

AH = Error Code DI = "XY" Carry Flag Clear All = 0 DI = "XY" BX = Current VMEbus ownership configuration

o - Not requested 1 - Requested

5-21


5.5.4 Set VMEbus Ownership Configuration

Although exclusive ownership of the VMEbus is not required for all VMEbus transfers, there may be instances where time critical operations need to be performed on the VMEbus without interruptions. This function can be used to gain exclusive ownership of the VMEbus. A call to this function requests ownership of the VMEbus from the arbiter. Use the Get VMEbus Ownership Status function (Section 5.5.5) to determine when the arbiter has granted use of the VMEbus. The previous configuration is returned upon completion.


Call With:

Returns:

Subfunction 33H

AH = AFH AL = 33H BX = Desired VMEbus ownership configuration

0- Not requested 1 - Requested


If successful:

5-22

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = Previous VMEbus ownership configuration

0- Not requested 1 - Requested

5.5.5 Get VMEbus Ownership Status


This function can be used after executing the Set VMEbus Ownership Configuration (Section 5.5.4) routine to determine when the arbiter has granted exclusive use of the VMEbus to the module.


Call With:

Returns:

Subfunction 34H

AH = AFH AL = 34H


If successful:

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = Current VMEbus ownership status

0- Granted 1 - Not granted

5-23


5.5.6 Wait for VMEbus Ownership to be Granted

This function is similar to the Get VMEbus Ownership Status (Section 5.5.5), but it does not return control until exclusive use of the VMEbus has been granted.


Call With:

Returns:

Subfunction 35H

AH = AFH AL = 35H


If successful:

Note:

AH = Error Code 01 = "XY" Carry Flag Clear AH = 0 01 = "XY"

Does not return until VMEbus ownership has been granted.

5-24

5.6 VMEbus INTERRUPT HANDLER FUNCTIONS


This group of functions is used to configure and process VMEbus interrupts-also referred to as Auxiliary Maskable Interrupts (AMls)-received on IRQI0. Each of the seven VMEbus levels can be enabled or disabled. If a VMEbus interrupt is pending, an interrupt acknowledge cycle (lACK) can be performed using the Real Mode Window. Section 4.4 contains more information on AMls.

5.6.1 Get VMEbus Interrupt Group Configuration

This function indicates if the VMEbus Interrupt Group AMls are enabled or disabled.


Call With:

Returns:

Subfunction SOH

AH = AFH AL = SOH


If successful:

AH = Error Code 01 = "XY" Carry Flag Clear AH = 0 Dr = "XY" BX = Current VMEbus interrupt group configuration

o - VMEbus interrupt group disabled 1 - VMEbus interrupt group enabled

5-25


5.6.2 Set VMEbus Interrupt Group Configuration

This function can be used to enable or disable the VMEbus Interrupt Group AMIs. The previous configuration is returned upon completion.


Call With:

Returns:

Subfunction SIB

AH = AFH AL = SIR BX = Desired VMEbus interrupt group configuration



If successful:

Note:

AH = Error Code DI = "XY" Carry Flag Clear AR = 0 DI = "XY" BX = Previous VMEbus interrupt group configuration


When enabled, VMEbus interrupts come in on IRQIO. It is the responsibility of the user to ensure that IRQIO is enabled via the 8259 and that an appropriate interrupt handler is provided. MS-DOS allows the user to directly manipulate the 8259 and the interrupt vector table. Other operating systems usually provide a service for attaching to and enabling specific PC/AT IRQs.

5-26

5.6.3 Get VMEbus Interrupt Mask


This function returns which VMEbus interrupt level AMIs are enabled and disabled.


Call With:

Returns:

Subfunction 52H

AH = AFH AL = 52H


If successful:

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DJ = "XY" BX = Current VMEbus interrupt mask

Bit 1 0 - VMEbus interrupt level 1 disabled 1 - VMEbus interrupt level 1 enabled







5-27


5.6.4 Set VMEbus Interrupt Mask

This function allows each of the VMEbus interrupt level AMIs to be enabled or disabled. The previous VMEbus interrupt mask is returned upon completion.

Int I5h Function AFH Subfunction S3H

Call With: AH = AFH AL = 53H BX = Desired VMEbus interrupt mask




Bit 4 0 - VMEbus interrupt level 4 disabled I - VMEbus interrupt level 4 enabled

Bit 5 0 - VMEbus interrupt level 5 disabled I - VMEbus interrupt level 5 enabled




5-28


If successful:

AH = Error Code 01 = "XY"

Carry Flag Clear AH = 0 01 = "XY" BX = Previous VMEbus interrupt mask









5-29


5.6.5 Enable/Disable Specific VMEbus Interrupts

This function allows specific VMEbus interrupt level AMIs to be enabled or disabled, depending on the state of bit O. The previous state of the VMEbus interrupt mask is returned upon completion.

Int I5h Function AFH Subfunction 54H

Call With: AH = AFH AL = 54H BX = Desired VMEbus interrupt mask operation

Bit 0 0 - Disable indicated VMEbus interrupts 1 - Enable indicated VMEbus interrupts

Bit 1 0 - Leave VMEbus interrupt level 1 as is 1 - Operate on VMEbus interrupt level 1








5-30


If successful:

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = Previous VMEbus interrupt mask









5-31


5.6.6 Get VMEbus Interrupt Status

This function indicates which VMEbus interrupts are pending. A pending interrupt needs to be acknowledged. The calling program can select all VMEbus interrupt levels or just those currently enabled.


Call With:

Returns:

Subfunction 55H

AH = AFH AL = 55H BX = Which VMEbus interrupts levels

o - VMEbus interrupt levels that are enabled 1 - All VMEbus interrupt levels

If error: Carry Flag Set AH = Error Code 01 = "XY"

If successful: Carry Flag Clear AH = 0 01 = "XY" BX = Current VMEbus interrupt status

Bit 1 0 - VMEbus interrupt level 1 not pending 1 - VMEbus interrupt level 1 pending







5-32

5.6.7 Detennine Highest Priority Pending VMEbus Interrupt


This function returns the level (1 to 7) of the highest priority VMEbus interrupt that is pending. Level 7 is the highest priority while Level 1 is the lowest. The calling program can select whether all VMEbus interrupt levels are checked or just those currently enabled.


Call With:

Returns:

Subfunction 56H

AH = AFH AL = 56H BX = Which VMEbus interrupt levels

o - VMEbus interrupt levels that are enabled 1 - All VMEbus interrupt levels


If successful:

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = Highest priority pending VMEbus interrupt

0- None 1 - VMEbus interrupt level 1 2 - VMEbus interrupt level 2 3 - VMEbus interrupt level 3 4 - VMEbus interrupt level 4 5 - VMEbus interrupt level 5 6 - VMEbus interrupt level 6 7 - VMEbus interrupt level 7

5-33


5.6.8 Acknowledge VMEbus Interrupt Via Real Mode Window

If an interrupt is pending on one of the VMEbus interrupt levels, an interrupt aclmowledge cycle must be executed to retrieve the Status ID vector from the interrupter. This function uses the Real Mode Window to perform an lACK cycle on the interrupt level passed by the calling program.


Call With:

Returns:

Subfunction 57H

AH = AFH AL = 57H BX = VMEbus interrupt level to aclmowledge

1 - VMEbus interrupt level 1 2 - VMEbus interrupt level 2 3 - VMEbus interrupt level 3 4 - VMEbus interrupt level 4 5 - VMEbus interrupt level 5 6 - VMEbus interrupt level 6 7 - VMEbus interrupt level 7

ES = Segment descriptor or Real Mode Window segment if called from protected mode or zero if otherwise


If successful:

Note:

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = Interrupt vector obtained during VMEbus lACK

To perform VMEbus lACK, the VMEbus master interface must be enabled (see sections 5.5.1. and 5.5.2 on enabling the VMEbus Master Interface).

5-34

5.7 VMEbus SYSTEM RESOURCE FUNCTIONS


This function can be used to read the status of the module's System Resources.

5.7.1 Get System Resource Flag

The System Resource Flag indicates if the System Resources, VMEbus BERR, VMEbus Arbiter, and VMEbus system clock are provided by the module. The System Resources switch, SWl, is used to enable or disable the System Resources.


Call With:

Returns:

Subfunction SOH

AH = AFH AL = 80H


If successful:

AH = Error Code DI = "XY" Carry Flag Clear AH = 0 DI = "XY" BX = System resource flag

o - System resources disabled 1 - System resources enabled

5-35

Appendix A - VMEbus CONNECTOR/PIN DESCRIPTIONS

The XVME-678/688 PC/AT Processor Module is a double-high VMEbus compatible module. On the rear edge of the board is a 96-pin bus connector labeled PI. The signals carried by connector PI are the standard address, data, and control signals required for a PI backplane interface, as defined by the VMEbus specification. Table A-I identifies and defmes the signals carried by the PI connector.

Table A-I. VMEbus Signal Identification

Signal Connector, Row: Signal Name and Description Mnemonic Pin Number

ACFAIL* IB:3 AC FAILURE: Open-collector driven signal which indicates that the AC input to the power supply is no longer being provided, or that the required input voltage levels are not being met.

IACKIN* lA:21 INTERRUPT ACKNOWLEDGE IN: Totem-pole driven signal. IACKIN* and IACKOUT* signals form a daisy-chained acknowledge. The IACKIN* signal indicates to the VME board that an acknowledge cycle is in progress.

IACKOUT* IA:22 INTERRUPT ACKNOWLEDGE OUT: Totem-pole driven signal. IACKIN* and IACKOUT* signals form a daisy-chained acknowledge. The IACKOUT* signal indicates to the next board that an acknowledge cycle is in progress.

AMO-AM5 lA:23 ADDRESS MODIFIER (bits 0-5): Three-state IB:16,17 driven lines that provide additional information about the 18,19 address bus such as size, cycle type, and/or DTB master lC:l identification.

AS* lA:18 ADDRESS STROBE: Three-state driven signal that indicates a valid address is on the address bus.

AOI-A23 lA:24-30 ADDRESS BUS (bits 1-23): Three-state driven lC: 15-30 address lines that specify a memory address.

A24-A31 2B:4-11 ADDRESS BUS (bits 24-31): Three-state driven bus expansion address lines.

A-J

Appendix A - VMEbus Connector/Pin Description

Table A-I. VMEbus Signal Identification (continued)

Signal Connector, Row: Signal Name and Description Mnemonic Pin Nwnber

BBSY* lB:l BUS BUSY: Open-collector driven signal generated by the current DTB master to indicate that it is using the bus.

BCLR* IB:2 BUS CLEAR: Totem-pole driven signal generated by the bus arbitrator to request release by the DTB master if a higher level is requesting the bus.

BERR* lC:ll BUS ERROR: Open-collector driven signal generated by a slave. It indicates that an unrecoverable error has occurred and the bus cycle must be aborted.

BGOIN*- IB:4,6,8,1O BUS GRANT (0-3) IN: Totem-pole driven signals BG3IN* generated by the Arbiter or Requesters. Bus Grant In and

Out signals form a daisy-chained bus grant. The Bus Grant In signal indicates to this board that it may become the next bus master.

BGOOUT*- IB:5,7,9,11 BUS GRANT (0-3) OUT: Totem-pole driven signals BG30UT* generated by Requesters. These signals indicate that a

DTB master in the daisy-chain requires access to the bus.

BRO*-BR3* 1B: 12-15 BUS REQUEST (0-3): Open-collector driven signals generated by Requesters. These signals indicate that a DTB master in the daisy-chain requires access to the bus.

DSO* lA:13 DATA STROBE 0: Three-state driven signal that indicates during byte and word transfers that a data transfer will occur on data bus lines (DOO-D07).

DS1* lA:12 DATA STROBE 1: Three-state driven signal that indicates during byte and word transfers that a data transfer will occur on data bus lines (DO-D 15).

A-2

Signal Mnemonic

DTACK*

DOO-D31

GND

IACK*

IRQl *-IRQ7*

LWORD*

(RESERVED)

SERCLK

SERDAT



Connector, Row: Signal Name and Description Pin Number

lA:16 DATA TRANSFER ACKNOWLEDGE: Open-collector driven signal generated by a DTB slave. The falling edge of this signal indicates that valid data is available on the data bus during a read cycle, or that data has been accepted from the data bus during a write cycle.

lA:I-8 DATA BUS (bits 0-31): Three-state driven, bi-directional lC: 1-8 data lines that provide a data path between the DTB 2B:IA-21 master and slave. 2B:23-30

lA:9,1l,15,17,19 GROUND IB:20,23 lC:9 2B:2,12,22,31

lA:20 INTERRUPT ACKNOWLEDGE: Open-collector or three-state driven signal from any master processing an interrupt request. It is routed via the backplane to slot 1, where it is looped-back to become slot 1 IACKIN* to start the interrupt acknowledge daisy-chain.

IB:24-30 INTERRUPT REQUEST (1-7): Open-collector driven signals, generated by an interrupter, which carry prioritized interrupt requests. Level seven is the highest priority.

lC:13 LONGWORD: Three-state driven signal indicates that the current transfer is a 32-bit transfer.

2B:3 RESERVED: Signal line reserved for future VMEbus enhancements. This line must not be used.

IB:21 A reserved signal that will be used as the clock for a serial communication bus protocol that is still being finalized.

IB:22 A reserved signal that will be used as the transmission line for serial communication bus messages.

A-3



Signal Connector, Row: Signal Name and Description Mnemonic Pin Number

SYSCLK 1A:1O SYSTEM CLOCK: A constant 16 MHz clock signal that is independent of processor speed or timing. It is used for general system timing use.

SYSFAIL* 1C:1O SYSTEM FAIL: Open-collector driven signal that indicates that a failure has occurred in the system. It may be generated by any module on the VMEbus.

SYSRESET* 1C:12 SYSTEM RESET: Open-collector driven signal which, when low, will cause the system to be reset.

WRITE* 1A:14 WRITE: Three-state driven signal that specifies the data transfer cycle in progress to be either read or written. A high level indicates a read operation, a low level indicates a write operation.

+5V STDBY 1B:31 +5 VDC STANDBY: This line supplies +5 VDC to devices requiring battery backup.

+5 1A:32 +5 VDC POWER: Used by system logic circuits. 1B:32 1C:32 2B:1,13,32

+12V 1C:31 + 12 VDC POWER: Used by system logic circuits.

-12V 1A:31 -12 VDC POWER: Used by system logic circuits.

A-4

BACKPLANE CONNECTOR PI


The following table lists the PI pin assignments by pin number order. (The connector consists of three rows of pins labeled rows A, B, and C.)

Table A-2. Connector PI Pinouts


1 DO BBUSY D08 2 DOl BCLR* D09 3 D02 ACFAIL* D10 4 D03 BGOIN* D11 5 D04 BGOOUT* D12 6 D05 BGlIN* D13 7 D06 BGlOUT* D14 8 D07 BG2IN* D15 9 GND BG20UT* GND 10 SYSCLK BG3IN* SYSFAIL* 11 GND BG30UT* BERR* 12 DS1* BRO* SYSRESET* 13 DSO* BR1* LWORD* 14 WRITE * BR2* AM5 15 GND BR3* A23 16 DTACK* AMO A22 17 GND AMI A2l 18 AS* AM2 A20 19 GND AM3 A19 20 IACK* GND Al8 21 IACKIN* SERCLK Al7 22 IACKOUT* SERDAT* Al6 23 AM4 GND A15 24 A07 IRQ7* Al4 25 A06 IRQ6* A13 26 A05 IRQ5* A12 27 A04 IRQ4* All 28 A03 IRQ3* AlO 29 A02 IRQ2* A09 30 A01 IRQ1* A08 31 -12V +5V STDBY +12V 32 +5V +5V +5V

A-5


Table A-3. Connector P2 Pinouts


1 N/C +5V N/C 2 N/C GND N/C 3 N/C N/C N/C 4 N/C N/C N/C 5 N/C N/C N/C 6 N/C N/C N/C 7 N/C N/C N/C 8 N/C N/C N/C 9 N/C N/C N/C 10 N/C N/C N/C 11 N/C N/C N/C 12 N/C GND N/C 13 N/C +5V N/C 14 N/C N/C N/C 15 N/C N/C N/C 16 N/C N/C N/C 17 N/C N/C N/C 18 N/C N/C N/C 19 N/C N/C N/C 20 N/C N/C N/C 21 N/C N/C N/C 22 N/C GND N/C 23 N/C N/C N/C 24 N/C N/C N/C 25 N/C N/C N/C 26 N/C N/C N/C 27 N/C N/C N/C 28 N/C N/C N/C 29 N/C N/C N/C 30 N/C N/C N/C 31 N/C GND N/C 32 N/C +5V N/C

A-6

Appendix B - QUICK REFERENCE GUIDE

Table B-1. XVME-678/688 CPU Board Jumper Options

Jumper Position Function Section Reference

J1 A'/ Sets EPROM or Flash RAM to non-writable + 5V 2.2.2 B Sets Flash RAM to + 12V

J2 A'/ Enables battery 2.2.4 B Disables battery

J3 A'/ IRQ9 is driven by VGA controller 2.2.1 B IRQ9 is not driven by the VGA controller

J4 A'/ Test jumper that supplies V cc to OSC 2.2.4 B Test jumper that disconnects V cc from OSC

J5 A'/ Enables VGA 2.2.1 B Disables VGA

J8 A'/ IRQ12 driven for auxiliary port 2.2.3 B IRQ12 not driven for auxiliary port

B-1

Appendix B - Quick Reference Guide

Table B-2. XVME-678/688 Switch Settings

Position Setting Function

1 Open VME SYSRESET* is not driven on the VMEbus at power-up ClosedI' VME SYSRESET* is driven on the VMEbus at power-up

2 Open VME SYSRESET* is not caused by the toggle switch ClosedI' VME SYSRESET* is caused by the toggle switch

3 Openl' VME SYSFAIL is not driven on the VMEbus Closed VME SYSF AIL is driven on the VMEbus

4 Open VME system resource function is disabled ClosedI' VME system resource function is enabled

5 Openl' Not user configurable. Must remain Open.

6 Openl' Disables the battery Closed Enables the battery

7 Openl' Enables the keyboard Closed Disables the keyboard

8 Openl' Enables color video Closed Enables monochrome video

.I indicates the default settings

B-2

Pin

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17


Table B-3. P4 Floppy Drive Connector

Signal Pin Signal

GND 18 FDIRC* FRWC* 19 GND GND 20 FSTEP* N/C 21 GND KEY 22 . FWD * N/C 23 .GND GND 24 FWE* lDX· 25 GND GND 26 FTKO* Mal 27 GND GND 28 FWP* FDS2 29 GND GND 30 FRDD* FDS1 31 GND GND 32 FHS· M02 33 GND GND 34 DCHG*

B-3


Table B-4. P5 IOE Hard Orive Connector


1 RESET * 21 N/C 2 GND 22 GNO 3 ID87 23 IOW* 4 S08 24 GNO 5 S06 25 IOR* 6 S09 26 GNO 7 S05 27 N/C 8 SDlO 28 ALE 9 S04 29 N/C 10 SO 11 30 GNO 11 S03 31 ATIRQ14 12 S012 32 ATIOCS16* 13 S02 33 SAl 14 S013 34 N/C 15 SOl 35 SAO 16 S014 36 SA2 17 SOO 37 HCSO 18 S015 38 HCS1 19 GNO 39 N/C 20 N/C 40 GNO

Table B-5. P6 Keyboard Connector

Pin Signal

1 OATA 2 NC 3 GNO 4 +5V 5 CLK 6 N/C

B-4

Table B-6. P7 Auxiliary Connector

Pin Signal

I DATA 2 NC 3 GND 4 +5V 5 CLK 6 N/C

Table B-7. P8 COM2 Serial Port Connector

Pin Signal Pin

I DCD2 6 2 RXD2 7 3 TXD2 8 4 DTR2 9 5 GND

Table B-8. P9 COMI Serial Port Connector

Pin Signal Pin

I DCDI 6 2 RXDI 7 3 TXDI 8 4 DTRI 9 5 GND


Signal

DSR2 RTS2 CTS2 RI2

Signal

DSRI RTSI CTSI RII

B-5


Table B-9. PlO VGA Connector


1 RED 9 KEY 2 GREEN 10 GND 3 BLUE 11 N/C 4 N/C 12 N/C 5 GND 13 HSYNC 6 GND 14 VSYNC 7 GND 15 N/C 8 GND

Table B-I0. JKl Parallel Port Connector


1 STROBE 14 AUTOFEED 2 PDOUTO 15 PERROR 3 PDOUTI 16 INIT 4 PDOUT2 17 SELIN 5 PDOUT3 18 GND 6 PDOUT4 19 GND 7 PDOUT5 20 GND 8 PDOUT6 21 GND 9 PDOUT7 22 GND 10 PACK 23 GND 11 PBUSY 24 GND 12 PE 25 GND 13 SELECT

Table B-ll. 17 Speaker Connector

Pin Signal

1 SIGNAL 2 +5V 3 N/C

B-6

Pin

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Table B-12. PXTl Connector

Row A Signal Row B Signal

IOCHCHK* GND SD7 RESETDRV SD6 +5V SD5 IRQ9 SD4 N/C SD3 DRQ2 SD2 -12V SD1 N/C SDO +12V IOCHRDY KEY AEN SMEMW* SA19 SMEMR* SA18 IOW* SA17 IOR* SA16 DACK3* SA15 DRQ3 SA14 DACKl* SA 13 DRQ1 SA12 REF* SA11 SYSCLK SAlO IRQ7 SA9 IRQ6 SA8 IRQ5 SA7 IRQ4 SA6 IRQ3 SA5 DACK2* SA4 TIC SA3 ALE SA2 +5V SAl OSC SAO GND GND GND


B-7


Table B-13 . PAT 1 Pinouts

Pin Row C Signal Row D Signal

0 GND GND 1 SBHE* MEMCSI6* 2 LA23 IOCSI6* 3 LA22 IRQI0 4 LA21 IRQll 5 LA20 IRQ12 6 LA19 IRQ15 7 LA18 IRQ14 8 LA17 DACKO* 9 MEMR* DRQO 10 MEMW* DACK5* 11 SD8 DRQ5 12 SD9 DACK6* 13 SDI0 DRQ6 14 SD11 DACK7* 15 SD12 DRQ7 16 SD13 +5V 17 SD14 N/C 18 SD15 GND 19 KEY GND

B-8

Appendix C - EXTENDED VGA MODES

The XVME-678/688 board supports standard VGA modes 0-13, as well as the following extended modes:

Table C-1. Extended Mode VGA Support

Resolution Colors

640 x 480 256 800 x 600 16 132 x 25 16 132 x 43 16 132 x 50 4 1024 x 768 (interlaced) 16 80 x 43 16 80 x 50 16

Because these resolutions are beyond the original IBM specification, do the following:

• Make sure your monitor has the desired resolution capabilities. A generic IBM clone is not able to sync on the different frequencies required for extended modes. Refer to Table C-2 for the horizontal and vertical frequencies for each mode. To run different extended modes, a multisync monitor is recommended. If you are using a mUltisync monitor, make sure the maximum horizontal and vertical frequencies are not exceeded. Otherwise, the monitor will not sync.

• Make sure a video driver is available for running your application software. These video drivers are available from Chips & Technology. The drivers are loaded as part of the setup for the application program. Currently available drivers include the following:

• AutoCAD (reI. 10, 11) • Ventura Publisher (reI. 2.0)

• Cadkey (reI. 3.5) • VersaCAD Designer (reI. 5.4) • Framework II/III • VersaCAD386

• GEM (reI. 3.xX) • VESA

• Lotus and Symphony (reI. 2.XX) • Windows 286 (reI. 2.X) • Microsoft Word (reI. 5.0 and 5.1) • Windows 386 (reI. 2.X)

• PCAD (reI. 4.01) • Windows 3.0

• Presentation Manager • WordPerfect (reI. 5.0 and 5.1)

• SCO ODT x Window • Wordstar (reI. 4.XX and 5.XX)

C-J

Appendix C - Extended VGA Modes

Table C-2. Extended Video Modes

Mode Maximwn Alpha Display Horizontal Vertical (HEX) Colors Fonnat Size Frequency Frequency

50 16 80 x 30 640 x 480 31.5 K 60 51 16 80 x 43 640 x 473 31.5 K 60 52 16 80 x 60 640 x 480 31.5 K 60 53 16 132 x 25 1056 x 350 31.3 K 70 54 16 132 x 30 1056 x 480 31.3 K 60 55 16 132 x 43 1056 x 473 31.3 K 60 56 16 132 x 60 1056 x 480 31.3 K 60 57 16 132 x 25 1188 x 350 31.2 K 70 58 16 132 x 30 1188 x 480 31.2 K 60 59 16 132 x 43 1188 x 473 31.2 K 60 5A 16 132 x 60 1188 x 480 31.2 K 60

5B (I) 16 100 x 75 800 x 600 35.2 K 56 5B 16 100 x 75 800 x 600 48.0K 72 5C 256 80 x 25 640 x 400 31.5 K 70 5D 256 80 x 30 640 x 480 31.5 K 60

5E (I) 256 100 x 37 800 x 600 29.5 K 90 5F (I) 16 128 x 48 1024 x 768 35.5 K 86

5F 16 128 x 48 1024 x 768 48.7 K 60 60 4 128 x 48 1024 x 768 33.4 K 40

C-2

The XVME-678/688 supports the following extended video modes:

Mode Resolution Colors Horizontal Frequency

60H 132 columns x 25 rows 16 30.23 KHz 61H 132 columns x 50 rows 16 30.23 KHz 62H 132 columns x 43 rows 16 30.23 KHz 64H 80 columns x 43 rows 16 31.39 KHz 65H 80 columns x 50 rows 16 31.39 KHz 6AH 800 x 600 16 37.78 KHz 70H 800 x 600 16 37.78 KHz 72H 1024 x 768* 16 35.41 KHz 78H 640 x 400 256 31.39 KHz 79H 640 x 480 256 31.39 KHz

* interlaced mode


Vertical Dot CLK Frequency

67.33 Hz 40 MHz 67.33 Hz 40 MHz 67.33 Hz 40 MHz 69.91 Hz 25.11 MHz 69.91 Hz 25.11 MHz 60.16 Hz 40 MHz 60.16 Hz 40 MHz 85.74 Hz 44.76 MHz 69.90 Hz 50.3 MHz 59.79 Hz 50.3 MHz

C-3

Appendix D - BLOCK DIAGRAM, ASSEMBLY DRAWING, AND SCHEMATICS

VGA CONTROLLER

BUFFERS

SCATSX

80386SX I 486SLC/e

PROCESSOR

ATbus

DRAM SIMM SOCKETS (4)

80387SX MATH CO-PROCESSOR

FLOPPY IDE

VMEbus MASTER

INTERFACE

Figure D-l. XVME-678/688 Board Block Diagram

D-J

Appendix D - Block Diagram, Assembly Drawing, and Schematics

.. r- : J_-,., .. ;;;1 ..

1

1

1

1

1

1 ... 1 Kl ~ 1

:)

1

1

1

I 1

C> C> ~I .. IP ,., - ,.,

l I C42 -L-J-F

Figure D-2. XVME-678/688 Board Assembly Drawing

D-2

REMOVE THIS SHEET!

Insert Schematic

Sheet Here

REMOVE THIS SHEET!

Numerical 1 Mbyte memory map 4-2 2 Mbyte memory map 4-3 4 Mbyte memory map 4-4 10 Mbyte memory map 4-5 16 Mbyte memory map 4-6 256Kx8 EPROM 2-20, 4-8 80386SX central processing unit 1-4 80387SX math co-processor 2-17

A Address consistency 4-27 AT-bus speed 3-7 Auto Park Disk 3-13 Auxiliary connector (P7) 2-12 Auxiliary interrupt 4.:18 Auxiliary maskable interrupt structure 4-23 Auxiliary maskable interrupts 4-22 Auxiliary NMI configuration 3-9 Auxiliary non-maskable interrupt (ANMI) functions

5-12 Auxiliary non-maskable interrupt structure 4-25 Auxiliary non-maskable interrupts 4-25

B Bad track table 3-24 Bank and SIMM Size 2-22 Battery and test jumpers (12, J4) 2-5 BERR 4-12 BERR, SYSFAIL, and ABORT Switch Mapped on

IRQlO 4-24 BIOS

Adding extended 2-20 Shadow 3-6 Xycom extensions 3-1

BIOS Main Menu 3-2 BIOS Setup Menus 3-1

Diagnostics Menu 3-16 Extended BIOS Features Menu 3-13 Function keys 3-1 General instructions 3-2 Setup Menu 3-3 Solid State Disk Setup Menu 3-11 System Information Menu 3-16 VMEbus Master Setup Menu 3-8

B (continued) Bus request level 4-13 Byte-ordering schemes 4-26

Intel 4-26 Motorola 4-26

Byte-swapping 3-8, 4-13, 4-26 Address consistency 4-27 Byte-ordering schemes 4-26 Numeric consistency 4-28

C CMOS 3-1

RAM 3-3, 4-31 RAM address map 4-32

COM A 3-7 COM B 3-7 COMI serial port connector (P9) 2-13 COM2 serial port connector (P8) 2-12 Connectors 2-6

Auxiliary (P7) 2-12 COM1 serial port (P9) 2-13 COM2 serial port (P8) 2-12 Floppy drive (P4) 2-10 IDE hard drive (P5) 2-11 Keyboard (P6) 2-12 Parallel port (JK1) 2-14 PATl 2-16 PXTl 2-15 Speaker (17) 2-14 VGA (P10) 2-13 VMEbus PI 2-8 VMEbus P2 2-9

Control Register 1 4-17 Control Register 2 4-19 Control Register 3 4-20 Control Register 4 4-20 Control Register 5 4-21 Control Register 6 4-21

INDEX

/-1

Index

o Date 3-4 Diagnostics Menu 3-16

Diagnostics 3-17 Diskette Drives 0 and 1 3-20 Error Codes 3-25 Extended Memory 3-20 Finishing the Formatting 3-25 Fixed Disk Drive, formatting new 3-25 Fixed Disk Drives 0 and 1 3-21 Fixed Disk Surface, analyzing 3-24 Format Fixed Disk Menu 3-23 Formatted disk, formatting again 3-25 Interleave, setting 3-24 Keyboard 3-19 Monitor Type 3-21 Parallel Port Tests 3-22 Park Fixed Disks 3-16 Serial Port Tests 3-23 System Board 3-19 System Memory 3-20 Test Control Options 3-19 Using the Bad Track Table 3-24

Diskette Drives 0 and 1 3-5, 3-20 DOS FDISK command 3-25 DOS FORMAT 3-25 DRAM 1-4, 4-7

1 Mbyte 4-7 10 Mbytes 4-7 16 Mbytes 4-7 2 Mbytes 4-7 4 Mbytes 4-7

DTACK 4-12

E EMS memory 3-5 EPROM 4-8, 4-9 EPROM memory map 4-8 EPROM/flash jumper (11) 2-4 Error codes 3-25 Extended BIOS Features Menu 3-13

Auto Park Disk 3-13 Keyboard Click 3-14 Keyboard Delay 3-15 Keyboard Rate 3-15 Numlock Boot State 3-15 Quick Boot 3-14 Screen Saver 3-14

Extended memory 3-4

1-2

F FAIL LED 3-1 Fixed disk drive, formatting new 3-25 Fixed disk drives 0 and 1 3-5, 3-21 Fixed disk surface, analyzing 3-24 Floppy drive connector (P4) 2-10 Floppy drive controller 1-4 Format fixed disk 3-23 Formatted disk, formatting again 3-25

H Hard drive controller 1-4

I/O address map 4-15 I/O addresses. unique to the XVME-678/688 4-16 110 port addresses 4-15

Auxiliary Interrupt 4-18 Control Register 1 4-17 Control Register 2 4-19 Control Register 3 4-20 Control Register 4 4-20 Control Register 5 4-21 Control Register 6 4-21 Status Register 1 4-18 Status Register 2 4-19 VMEbus HI Address 4-19

110 ports Centronics-compatible parallel 1-5 RS-232C serial 1-5

IDE hard drive connector (P5) 2-11 Installation 2-1

Adding extended BIOS 2-20 DRAM 2-22 Into a backplane 2-17 Jumpers 2-2 Math co-processor 2-25

Interleave, setting 3-24 Internal Floppy and IDE 3-5 Internal LPT 3-7 Interrupts 4-22

Auxiliary maskable interrupts 4-22 Auxiliary non-maskable interrupts 4-25

IRQIO 4-12 IRQ12 Jumper (J8) 2-4

J Jumpers 2-2

K

Battery and Test (J2, J4) 2-5 EPROM/Flash (11) 2-4 IRQ12 (J8) 2-4 Locations 2-3 VGA (13, J5) 2-4

Keyboard Click 3-14 Keyboard Connector (P6) 2-12 Keyboard Controller 1-5 Keyboard Delay 3-15 Keyboard Rate 3-15

M Manual structure 1-2 Master access mode 3-9 Master byte-swapping 3-8 Math co-processor installation 2-25 Memory

EMS 3-5 Extended 3-4, 3-20 Shadow 3-4 System 3-4, 3-20

Memory maps 4-1 10 Mbyte 4-5 16 Mbyte 4-6 2 Mbyte 4-3 4 Mbyte 4-4 EPROM 4-8

Miscellaneous XVME BIOS Functions 5-4 Get Flash BIOS Write Configuration 5-8 Get LED Configuration 5-6 Get Real Mode Window Physical Segment 5-5 Identify XVME Model 5-4 Set Flash BIOS Write Configuration 5-9 Set LED Configuration 5-7

Monitor type 3-21

N Numeric consistency 4-28 Numlock boot state 3-15

o Off-board extended BIOS 3-12 On-board extended BIOS 3-12


P PI pinouts 2-8 P2 pinouts 2-9 Parallel port

Connector (JKl) 2-14 Tests 3-22

Park Fixed Disks 3-16 PASS LED 3-1 PA Tl connector 2-16 PC/I04 expansion site 3-12 Power-up speed 3-6 Programming 4-1 Programming the EPROM 2-20 PXTl connector 2-15

Q Quick boot 3-14 Quick reference guide B-1

R Real mode window

EPROM 4-9 Using to access VMEbus memory space 4-9 VMEbus lACK Space 4-9 VMEbus Short I/O Space 4-10 VMEbus Standard Address Space 4-11

Real Mode Window (RMW) Functions 5-10 Get Real Mode Window Configuration 5-10 Set Real Mode Window Configuration 5-11

Release on Request option 4-13 Reset structure 4-30

S Screen saver 3 -14 Serial port tests 3-23 Setting the EPROM menu 2-21 Setup Menu 3-3

AT-bus Speed 3-7 BIOS Shadow 3-6 Date 3-4 Diskette Drives 0 and 1 3-5 EMS Memory 3-5 Extended Memory 3-4 Fixed Disk Drives 0 and 1 3-5 Internal COM A and COM B 3-7 Internal Floppy and IDE 3-5 Internal LPT 3-7 Power-Up Speed 3-6 Setup RAM Configuration 3-4

1-3

Index

S (continued) Setup Menu (continued)

Shadow Memory 3-4 System Memory 3-4 System Memory Cache 3-7 Time 3-4 Video System 3-6 Wait States 3-6

Setup RAM Configuration 3-4 Shadow memory 3-4 Shadow RAM 4-14 SIMM

Installation Procedure 2-23 Size 2-22

Solid State Disk Setup Menu 3-11 Boot from SSD 3-11 On-board Extended BIOS 3-12 SSD Address 3-12 SSD Device Type 3-12 SSD Interface 3-11 SSD Size 3-11 XVME-956/101 Device Size 3-12

Speaker connector (17) 2-14 Specifications 1-6 SSD

Address 3-12 Boot from 3-11 Device Type 3-12 Interface 3-11 Location 3-11 Size 3-11

Status Register 1 4-18 Status Register 2 4-19 Switch

Locations 2-3 Settings 2-5

System board 3-19 System Information Menu 3-16 System memory 3-4 System memory cache 3-7 System Resource Functions 4-30 System Resources 3-9

T Test control options 3-19 Time 3-4

1-4

V VGA

Connector (P 1 0) 2-13 Extended modes C-l Graphics controller 1-5 Jumpers (13, J5) 2-4

VGA, extended modes C-l Video drivers C-l Video system 3-6 VME SYSRESET* 4-30 VME HI ADD 4-11 VMEbus BERR Timeout 3-9 VMEbus HI Address 4-19 VMEbus lACK Space 4-9 VMEbus Interrupt Handler Functions 5-25

Acknowledge VMEbus Interrupt Via Real Mode Window 5-34

Determine Highest Priority Pending VMEbus Interrupt 5-33

Enable/Disable Specific VMEbus Interrupts 5-30

Get VMEbus Interrupt Group Configuration 5-25

Get VMEbus Interrupt Mask 5-27 Get VMEbus Interrupt Status 5-32 Set VMEbus Interrupt Group Configuration

5-26 Set VMEbus Interrupt Mask 5-28

VMEbus Master Functions 5-18 Get VMEbus Master Configuration 5-18 Set VMEbus Master Configuration 5-19 Get VMEbus Ownership Configuration 5-21 Set VMEbus Ownership Configuration 5-22 Get VMEbus Ownership Status 5-23 Wait for VMEbus Ownership to be granted

5-24 VMEbus Master Interface 1-5, 4-12 VMEbus Master Setup Menu 3-8

Auxiliary NMI Configuration 3-9 Master Access Mode 3-9 Master Byte-Swapping 3-8 Master Interface 3-8 System Resources 3-9 VMEbus BERR Timeout 3-9 VMEbus Interrupt Handler Configuration 3-10 VMEbus Request Level 3-9

VMEbus Memory Space, accessing using the Real Mode Window 4-9

VMEbus PI connector 2-8

V (continued) VMEbus P2 connector 2-9 VMEbus request level 3-9 VMEbus Short 110 Space 4-10 VMEbus signal

(RESERVED) A-3 +12V A-4 +5 A-4 +5V STDBY A-4 -12V A-4 A24-A31 A-I ACFAIL* A-I AMO-AM5 A-I AS* A-I BBSY* A-2 BCLR* A-2 BERR* A-2 BGOIN*- BG3IN* A-2 BGOOUT*- BG30UT* A-2 BRO*-BR3* A-2 000-D31 A-3 DSO* A-2 DS1* A-2 DTACK* A-3 GND A-3 IACK* A-3 IACKIN* A-I IACKOUT* A-I IRQ 1 *-IRQ7* A-3 LWORD* A-3 SERCLK A-3 SEROAT A-3 SYSCLK A-4 SYSFAIL* A-4 SYSRESET* A-4 WRITE* A-4

VMEbus Standard Address Space 4-11 VMEbus System Resource Functions 5-35

W Wait states 3-6


X XVME BIOS Functions 5-1 XVME-678/688

Operational description 1-3 Features 1-1 Specifications 1-6

XVME-955 hard disk/floppy disk module 2-17 XVME-956/101 3-11

/-5


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EXTENDED 8IOS

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A

~ XDCO',5l

~ IRQl

~ ATIRQ12

~ COLOR

~ K8INHI8IT

I«}--

1

1

1,18

4

4

'P7 1

-02 3 4


5 MOUSE PORT

l~o I«}-- -06 7

f~ 8 II ~

~

'P6 1

I«}--1-02 3 4 5

t.~ I«}--ro 6

KEYBOARD PORT

7 8 9 ~

~ RESET2_ 1

~ GATEA20 1

I 7 _ .....

o i ~ X ~ com £JU>E,KIDIIlIII<""" 6 "'_ ~ =... pn.. SCHEMATIC C @ ............. XVME-688

~,-.... '-"" TIIUI;~"'TN.""" ~ ........ ~ UTTt:lXYGaIIMD ...... MDT -

~;r:.~ 3~ 72688C-OOl

XVME-6781688 &hematic Sheet 3 of 18

~5

15

3 3 15 15 15 15 15 15

1

+ v

2

R27 10K SI'Il

TPl )

,~----t---------UVVV~--------------------------4-----------------------------~~[) 16MH2

r=----~~~---------------------------------------------------------------------------------------------------------------~~ CLKXIN

VBU ~C>--------~--------------------------------------------------~~----------------------, TP2 (

1 CB77 1 9f~

r~ 3..!.JaGU lV2

r~ ~91 1 9f~ ""!,loou 470K

SI'Il

5 '; U16

!?R92 14069

SI'Il

< IBM 1 SI'Il

GND-7

~9 SI'Il

1

REV 1m til.

A

~ 32KHi!


f1'NFACTl..RIl£ RaEASE SIt

12,14,15

ALE ~c>----------~~R4A1A,~2--------------------------------------------------------------------------__________________ -+ ________________________________________________________ ~ ATALE 8,l1,lB

33 SI'Il

REFRESH.C>-----------~2~R6A9A'~1--------------------------------------------------------------------------------------------~------------------------------------------------------_4=> ...f") ATREF. 9,lB

~ ~

33 SI'Il U35

.-__ ~2~ >~3 __________________ L1IR~~~~4~F-2------------------------------------------------------------__________________________________________________________________ ~=> 1 l.-6Sf'1) 33 SI"()

~125 UCC-14

ATOSC 18

..--- Bl4MHi! 9

U35 GND-7 OSC14MH2~C>----+-~--~5~ >~6 __________________ L1'R~9~5~.F_2------------------------------------------------------------__________________________________________________________________ ~=>

~SI'Il 33S1'1l 74F125

.~ ~93 CR7 :>'00 ,1N914B lSI'll

<\7 Q3 3 t~ 5PKOUT ..--- 2 I"

,1N914B

~~1 +5V R1372

lOOStt) 1/ .....

J7 1 2 A 3 8

9R138 10K SI'Il

2

,r-. BATOUT 15

VMESYSFAIL. 14,17 ~

-R VMESVSRESET. 12,14,15,17 LOG....RESET 15

I 7 --..-

~ ~ =.""'=!" X ~ c om !>I.lM:._4II1>'I

8 I ~ r.T".n<~----------------------~ 8 .x~... SCHEMATIC C ~ ............ " XUME -688

--r..- ;~..-.,... I = IF-==-=':=" '":"". ~O&II. II).

~ ~ I~ ~"5.;:~n>-I.T,~72688C-OOl

XVME-678/688 Schematic Sheet 4 of 18

~6

BANKO LOI.I

Bt1A( 0 '10)

SDI CRA1

1 CASL. ~ ~O.

~ ~~33 ~ og.o DCI2

DQ4~ DQ5 ....

IlQ6 BI'IR(, DCI7 il

~~ DQII AMACO}

:s3 D9 h Q9

~1~ 1 _( 1 ) BI1A( 10

~ :s35K! IC f-IC ~\1 AHAC::>} rl \Ill) U5S

.co , U5S D- ~:.= :s3

HA(O 2 118 ~1 _(3)

~ 4 116 I :s35K! ~ 6 114 ~'!.1 AMAC4} MAC I 335K!

!'IA(0'9)

'L .. ~~ _(5)

HA( 11 19

I l - ~1 BHAC6}

335K! 7 ~. AHAC?l

33 5111

£~1 AMACAl

:s3

~~ ~1.1 Bt1A(9)

335K! ~1 AHAC1 Ol BANKO HIGH HA(B) 2 Y11 ~

Ji. LH ~1 8 112 BKJI':.

1

11 "'" 19 335K! 13 17 l ~'!.a Y24f.L- 335111 - SDI CRA1

~:: !.~~ DCI2 DCI3 DQ4

~7 DQ5 IlQ6 DCI7

Bl'lRC 7' DQII OIlS:

D9

~ Q9

o .9t:j Bt1A( LO

I =~r rli !AlII ~ .'" o Y9't)

~\1 og.o

BANKI LOI.I

~

.~~ 0(0) OlD)

~

OU) 8MA(6:

~ 01 0(2)

D9 h 0C'1l

BMRUO: nC4l

0(5) ri !AlII~ ~-i .a,

~ OC6}

nC?l

BANKl HIGH

SDI CRA1 nCA}

~~ 1t1A': 0) 4 O(B) 0I9~ It1A O(

DCI3 0(10: 01 10) 0111 DQ4

DQ5 DC 1 L} IlQ6 DCI7

OUS: nC1"l

DQII It'll D9 0(13)

n ~- Q9

OC14}

IC ~IC nC1<;l

no !AlII U5S ."', U5S

7

lR4~2

~ ~ 1114.;>1(

12 111~;>I( 11 111~;>I(

'" 16':7';>1(

9 111~;>I( 7 111~;>I( .. 111':7';>1(

"""

III 4.;>1(

..J.5. 111~;>I( II . 111~'IC S 111~;>I(

"ll1~;>I(

3 111~;>I( 2 111~;>I( 1 111~;>I(

"""

-

~

~PARL

0(0'1 5)

PARH

~ ATSY SCLK :=:: ATS9£.

ATAEN ATRESET DRV


1

1

1

lB lB 7,9,14,1B lB

. - .. -

7 ---~I=-"i:i. x~com --..,. B 1:= = .... .-------------1 B ......... SCHEMATIC c ~ ... _... XUME-688

"I_-":-"'_~ ~-'IIL a 1InY .. ___ ......... -

==:..~..: s-.;, 72688C-OOl


D-7

1

1 1 1

1

1 1

MATH COPROCESSOR

0(0'15)c:>-------------------------------------,

& INTERFACE CIRCUIT


A..CC SIDCET +/V

A(0'23 ,~ -531UD..K2

~f~ L~~========I40 STEN 59 acrt

C>------~------------------------------------------~~~ C>------~------------------------------------------_;H~~ C>------~-------------------------------------------~~~ READYe :5

M/loe [>-____ ~::::::::::::::::::::::::::::::::::::~~~==+l~~. ) ~M'52 A(2: ~ IMlO. C> ___________________________________________________ 4~1 W~

WIRe R ADSe ~ 47.R)SO

~===i~~4 EHl 21EHl 25GNl

t-----.....;;;"Q1ii GNl t-----.....,32;,jEHl t-------=34"l::

NlCik--1«:

~~::;

!tR101 10K 511)

2

!tR68 1K

511)

2

i?R58 10K 511)

WC~IC NIC~I«: t-------------------------------------------------------------;~:>3B7_BUSYe 1

NlC~1«: ::::~~::;

~Q~~~----------~~--------+_----~--------------------------, "~ 9JSY.I:l'~=------_I_---__1I__-.... I ~JACT02 _1" GNlF.~~----, L-+----~~SM GNl ~42;;_----.... !t R98 GNlp'~~o------~ ~ GNlr.67,------~ 2 GNl r.63,;------+ :: f"66"'-____ -+

8~ Q ACT02

I SMO

I ~ 40 d 6 ~CT02

I SMO

UCC=14 GNl-7

2 40 " ff!::T02..1 ~

12~ ",I~ /~-----' ~

VCC-14 6ND-7

" Ull )o'L------D 387 _PEREQ

I ~ m =''''':r X ~ com SUK:'-""" 8 ~ ~ ~~~.----------------------, ~ .. """... .1'1 SCHEMATIC

~ ............. XVME-688 r-r- -:!" 11-.... _·-i =::==~,=,.~ __ JlJ.

I~ I~ t 1~;='-~f1jQ 72688C-OOl

7 ----

XVME-6781688 Schematic Sheet 6 of 18

D-8

6 8 8 8 8 8

16 1 1 1,18 1,18 1,18 1,18 2 2 S 1,18

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

2


R112 +su.-----~AAA~~--_,

10K sm

ATIoCS1~~J~~============t===============================~1l HCS1. ;=.. IoB7=

~~"CJ--------------------------------------------__,

IoENH.<"Jr------------------------------------------,

MULTIFUNCTION CHIP SERIAL PORTS PARALLEL PORT FLOPPY oRU IDE DRU

U4S

+ U

+ U B2C711 FLATAU<

. 1 ~ 2 ~ =l~ \tt1_c72~5'-----4 r-- V V V --- ~ HXSI. ~~~----~

-::~~t.? ::~! 9~~~ .2< :0. ~ ~~~~=~ "~T;~~)(~[~ :I~ )=============1 J:s.., 2 2 2' IDEEIHI· D2 5 3

2 ~ 53 ". ;[)(4

L..-______ ~1.~'~ t~~=i~~~==========t • ~~~--------+-------------r------~-~-A-A-~------~---I---------~--~~T~ ~~ . - ~~OA~ -'P ~ D7!-'·5<i""---'A:O-Lo""'-'w'-'-------t

I ~

~7 I l~'~ ~ =0 D~p-93~-__ ------------------' ~ ~ C~p:~92------------------------------------------------------_I_,_I_c-----------------------------------------<J I ~

~

ATSo( 0 '15)

OTR2 RTS2 TX02 CTS2

" ~~OD R~P:9~1=================================================_4_------------------------------------<J oRATEO ~~90

ATD~~~~~ ~====================================================~~~.~. ~I-r~;~========================================================~------------------------------------------CJ -<-J OSR2

ATIRQ3 <: ~ :IRQ3 RlCD2 89 ATIRQ4 (J----------------------------------------------------~38~~4 ~p-~87--------------------------------------------------------------------------------------------------~ ATIRQ7 CJ----------------------------------------------------~~~~m ~p:~86---------------------------------------------------------------------------------------------------<J ATIRQ6 CJ--------____________________________________________ ~4~°F.rnm DCD1. p=;tB5==================================================================================================~ ATIOR_ E~============~~===================================2~~~ RIl~B4 ATIow_ ~~~ Dml.p~~==================================================================================================~ ATAEN ~ ~11,.1z. 52 AEN CTSHj)62 ATORQ2 <J------------~~~-----J----=-----------------------:~~~T RTS1.P~~:~---------------------------------------------------------------------------------------------------L)

XRST ~C) ______________ ~SMD'·uO~ ______ ~1 r-----____________________ ~S8~ ~;I_c~79---------------------------------------------------------------------------------------------------L) FRWC_ <~Jr-------------------------4--------------------------~~LC ~11-~78---------------------------------------------------------------------------------------------------<J

RX02 CJ OC02 ~ ~~1 .a RI1

OTR1 CTS1 RTS1 OSR1 TX01 RX01

lOX- ~3==========================l========================~~~~. S~.p~~------------------------------------------------, MOl_ .. 2 HlRO. .....TlFO' p.=76 ______________________________________________ , FOS2_ OWl. ~p.~~---------------------------------------------, FOS1_ <J--------------------------+-------------------------~4~OWO. naT.p7~------------------------------------------_. Mo2_ C}--------------------------+-------------------------~S~Mm1. SL~p·73~----------------------------------------__,

+SU.-~~----~----~----,

~R116 ~R1S9 lFR161 <~R160 <' 4.71< <' 4.71< 4.71< <' 4.71< ~sm ~lsm lsm 2 sm

2

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

FOIRC_ <J'-------------------------+-----------------------__ ~7'-jDlR POO 71 POAC 0 )

FSTEP_ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~:~ POl ~ 16 FWD_ 9 I.IlATAe PD2 . 69 2 ~~======================~====~~====E====l=====§~~~~~~EO 16 F~~~: ':~. PD3:: PO· ~ '-----------------------------------------_1_,----...... ------0 r=; IPNIERRDRT 16

FWP_ I-RTf'RH ~ 6S PO (S '-------------------------------------------..... -----------0 ~ SELIN 16 FROO- ~TAe ~t~64==~PODAet"nZf==~==~~~~--_::::_1I_~~jU~~t0Jl~~--------------------------------------------~--£D~1-----4r--~=> 16 FHS_ 17 HJSELOSK~ P07 DA' D '7 ) ~ OCHG_ ~D----------------------_t----------------------__'L.j ~ _~ E'll£llJLl. 2.. JL 33 Po( 0 ~ POC 0 >7 )

"Tc:'" n) --<Ii AO ~p.:,,:,-61---------------------------, RN6

_ R1071 +SU.----~~AA~--------------~

4.71< 5MD

ATSACO'19) <=J-----------------------------~

..RTSAC 29 Al ~PE' 60 POAC 1 ) La. 7 33 pn( 1 rSAC 2 30 Ai! RN6 SAC3 31 A3 SLCTl_csg~-------------------__, POl'lC2l 6 33 PO(2) c:I'lC 4 32 A4 X2 21 'v RN6 1'l'c:"(S 33 AS Xl/CU<l-'2""--0 ______ ~ Pn"(:>;) 12. 5 33 PO(3)

.A 59.(7 -f- : ~rl fi~9'----' ~ PORC 4) ~ 4 ~ Po( 4

A'5~~~ :; All CNl~ Y~, 2 " POACS 11. 3 ~ PD(S)

A9 CNl~ ~~~ RN6 L-____ CNl=~ tH! MDa pnl'l( n) 15. 2 33 POC 6)

1 ~ ~f20 !'OOD) ~ .1 ~ PnI?

y~ -R102_

'------~VVV,~~--.+SU 4.71< sm

PACK '------------------------------------------------------------~<J PBUSY

~------------------------------------------------------------------~"8 ~~LECT

16 16 16 16

DC .....

16

61 ~~ X ~ com EfU>£.-.."., 6 "'_ 8 ~,

8 ......... , SCHEMATIC c § ........... h XVME -688

I ~ ..... ~,....,..~ -..: ENI.KI. UTYOIXYCIOII ... ..-u.IGT -

~"5.~"" 7~ 72688C-OOl


D-9

IDE DRIUE CONTROLLER

UCC-14 GNO-7

1 XRST n 11 Ull 0

FS~t 7 IOB7 ~

2 ATSOCO'15J ~

'Us5 7 IOENH. '"'

1"- LS245 1 G 5I"Il

----L DIRucc-1I!O

ATSO(BJ 2 .... " 1,8 Al 81 rSI . 9 3 A2 82 117 '10 • A3 83 ' 16

<;r 1 5 ... 8. 15 6 AS as • 7 A6

::;; 12 rSI .4 8 R7 rSI 15 9 AS BB

'---

'U54 IOENL. '"' 1"-

LS245 7 G 5I"Il

LL OlR uccoozo

ATSO(6J 2 A1 --,.

J.a 81 'SOC 5 3 A2 82 7 ;SO( 4 • A3 83 16

O( 5 ... 8 • 5 6 AS as " 7 A6 86 13 8 R7 87~

r--L AS BB~ '---

1,18 ATIRQ14 /"""L ~140

1~ 3351"1l UCC-14

+5U+---, 2 C49 +r U35 !?R139 I"'W ,R1~~ GNO-7 10 151"1l

I < 330

1,7,18 ATIOCS1~(t. 8~ ~,51"1l 10K

~F125 5I"Il

2 ATSACO'19l ~

'U56 1 LS244

Hi G1 ........ W G2 UCC-ZI

7 ~g~~: ~ 2 Al~l1~ 7 6 A12 Y12 4

'SAC 2 8 A13 Y13 12 4 ATALE '"' 4 A14 Y14 16 2 ATIOW.;=;

:;~:::~ 2 ATIOR.~ fHSA' llA23Y23

"SAC 0 13~

'7

III

I

15. 2 33 RNII , .. 3 33 RNII

16. 1 33 RNII

13.. • 33 RNII

12. 5 33 RNII

Ii 33 'v RNII

9 8 33 RNII

,a. 7 33 RNII

"'" "" .... A


REIJIS]lJ,j !l.lD< ......... ..- ...... '" .... I"V'NFACTlRII'£ RELEASE S""

IOE CONNECTOR

1~ 2 3 4 S 6 7 B 9 10 11 12 13 14 1S 16 17 18 111

~: 23 24 as 26

~.,

~., 31 32 33

~., 36 ;p 38

tc---¥of<> ~

- I- I- lIMO I'" I

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n~ SCHEMATIC ..x1't.JlDl:t.l

C ~ ... ..-.... XUME -688 f- f-1; :-..-... .---- ...... ~ ........ UI1YtlX\'QQlllMlDlHIIU.1IDT _

I~ I~ 1::""5.;='~"" ~ 72688C-OOl

XVME-6781688 Schenuitic Sheet 8 of 18

D-I0

9

9

2

9 9 9

9

9

9

UP(O,7l

OAC PALETTE

BT471

ATSA(O'19l<= ~>--------,

+ U

R115 1K

SIf)

L2

f'LCC/SlD<ET

~R143 1K

SIf)

2

2 C32 b CS3 1, CSO 1, C40 1 C29

lFL'_~_~ _______________ ~lE~1_~~_1~ ____ ~lF*-~9c_OO_'_~ __ ~~+~2_;to_~_~F __ ~~~ +~U ~ <~ R121

10K SIf)

2

i}..142 ~~~1 1X

2 SMO

MONITOR SENSE U1339

+ U

~R135 4./1< SIf)

2

2 IF~~ ~'3L-____________ ~11~~~b~3 ________________________________________________________ ~ HSYNC ~D--------i----"--I~~SMO~~ I IN) J

t UCC-14 GNO-7

4 'UsO USYNCD----------~51~ ~~~-------~11~~TIRanIF'3--------------------------------~

I

UIOEO OUTPUT


9

I 71-..... ° =-'"':t"" X ~ com IR.JI£,-""" 6 --8 ~ r,pn'n<~----------------------_1 8 .......... SCHEMATIC C @ -"'''AD •• ft XUME-688 1-1---1 ~--.. -·i ..... ___ ,..'"'~.~CI&.Ml.

ll~j 1~~.z .... j,~~72688C-OOl XVME-678/688 Schematic Sheet 10 of 18

D-12

13

14

1

1

1 14 2

4 2 2 14 14

12

UI'£ MASTER

ADDRESS MODIFIER DRIVER

... _ .... A


- . - .-I1INJFACTURDE RELEASE I"'"

UI0 9 8

r-------------------------------------~,D~>~~--------------------------------ty !::' ut£A/14 17

74F125 UI0

C_AM2C> ~--------------------____________________________________________________ ~--------------------------------______ t-____ ~12, >;11~ ____________________________________ _L>

13L.9~ 74F125

UI0

..r'\VMEAM2 17

+iU

~R24 10K UME MASTER ADDRESS DECODE ~

2 25NS

A(O'23) ~ TEST XR5T. If-DA ~

MAS_EN_ ;:( LOMEGCS_ ~ A( 1

--.8{16 ATILE ~

ATMEMR_ ATMEMIoI. ;;

IoISELO I.ISELI

+5V

11A5-DONE .......

r--------~r_--~2~ >;3 ______________________________________ ~ I 1 L.95r()

'V 74F125

VMEAMI 17

UI0

5 ~6~------------------------------------~ r-----------------------------+---~4~L.9~ 1JI1E7ACK. 17

74F125

....... ~ 12 ·5~ 12

V6 --'"'" ATIDC:HIDY 5 ~6~--------------------------------------------------------------_;_> ;----------'4"--1L.9~ 9

74F125 VCC-14 GND-7

-

--'"'" ATMEMCS1S-

I 7 ---o ~ :::=.-:r X ~ com ---...,. ~ i· .... B =... fPn.& SCHEM~TIC C ~ ........... XVME-688 Ib>o!!··_·· .. ..... -m.~nK ..... _~_III. 1IlIY • ..___-.... _ _

I=--:;::::,~~ 17. 72688C-OOl

XVlvfE-6781688 Schematic Sheet 11 of 18

~J3

12

12

14 1

... ~ ... U

~R13 UCC-14 10K SI'D GND-7

I1ASe ~ 1 '" US7 '- 1 r--us-~ ______ ~ ____ ~=J~~~//~----------~~ ______________ ~I~~

~R12S 10K SI'D

2

ut1EENe L..J -______ ~ :::

ACO'23) C>------------------------------------------~~~A~C~----~~B~m~nlHl~2~UR~(,~'t=)======1 ~=A;;(H:===4~6~m2 n21-;'4 • A( 4: : A13 V13t-;~"'6i--~::R~«: ~~------1 t--A~CC S~---+--;;13;-1m4 n4r.7;=-~U~RC: S~------1 t--R~CC 6:!+----+-7.1So-!A21 Y21HS;'-~U~RC: 6:!+-------1

t-_A~C7~:---+~17~~ ~t3~~~~========t .-_A~(~ __ -+~II~A24 Y24~9

-

""""iJi4 I 1. FCT37

DUT34H ~C> _____________________________ --.?~~~.SI'D

)(oCO'lS) 8 ~m(n "D1 Ql~ _UA(16) t-------,XI:~D(:e_!~--~ "12 iii! LaURC T t--~~~g~:I:+---..<:7 1-:-14113 :~S ::: La:

t--~~~D~C:4~--~O~ ~~!i16~~~A~(?~O~~~~ 1====~~~D~((~5t:==~4~ :: CI7 19 :23:

+5U~ UCC IH) 10 -

2 RTSO( ° '15) C:>----------------------......

RDJ tal"'.

A

~------------------------------------------------~~ ~


11

UA(l'23) 17

1=~~~t==~it:7~~~~~~1 r----------------------------------------~J UO(O'lS) AT<;nc n 1 11 so AO~9'--------:LJ~nc:'~RIl~--.. 12S1 Al~B------~U~DD~(:~9~~

t-~~rSD~D~(2~--~1713 B2 A2""7 ______ ~U~DD~(:~ ll",!+O--_t

17

12 2

12

t--~A-~~:!!D~CC[!--3 4~--~!;i;I; B3 U1 A31:i:;---~~~::~ ~l:~l _ _t

t--~A-:!!:;O~C[~ 5'--~1~6 B4 SI'D A4~4~====~;~t=l t--~A-<;()~([~ fi'--~o;;;!BS AS!?

t=jiISi~tt:==j18~: :1"2=--___ -"" oo",-",(LS""""-_ _t lEe DIR

19 IF

r ~eL>------------------+_-----------~

I==: I

7 ---~ I =:r X ~ com IIUIIE_..,.. 8 ~ ~n&~-----------~ 8 .x..- ... II" SCHEMATIC C ~ ............ 11 XVME -688 --'-- Il-.... ·-Ii 1NI.K ___ .,..~_~caa.MJ.

~ ~Ii I~~~":'~~ 72688C-OOl


D-15

1

1

17

5 2 2 12 4

12 4 1 15 17 12 15 4

15

11DDA0~

RCO '23)

0'

Aj

ROe( 1.7) ...... ~ 0' ~

RTREN~~ ~~~.~ ~r

=,,,,"RIL_I .. c .. c .. ,

~ T-

lCRST SYSRES

VI"

UHEDS ABlJRT lEi1'Hi!

.'" ,

UELRS- 8

ACT1DID ... 41 q

:::: I!i2 5

~

"'" U7 9

2 1 -.-~ . ......

=' =: .-.... ."..- .....

" = .. , :::-- .. .. ,...-...,

~. ........ = 34

i~ 54

.4

32 49 Ii6

Pl.I:CISDDCET

+!iU

f.! UCC-14 6ND-7

5~ ~

.. ~~ .. i(Sos

~! j2-

'¢ ~

~

~

~

" ~ jiM!

V

~~. ID ji-M! 12 r---i r--- 9 -

~7 11 ~~IR

...,

~ ~ 1~!~2 +r 11K SIt)

1,18


OUT34H 13

AN1I RnRQ10

)(1)(0'15) FAD... PR55 ~ 1JSEl...0 IJSEl...l c...A'12 ms....El* Fl.RSHEI* ILD ILl RI.D TD1EDUT

RTBUF--El*

1>16

1 1,18

1 15 15 12 11 11 11 11 3 12 12 12 15

2


A' BATTERY ENABLED B' CLR CMOS

UME SYSTEM RESOURCES +suI4-----------------,

MIl -MI.

A


• ... (X ...

1 SUBAT~====~--------------~ 4 BATOUT[

4

4 R20 lit

,91)

UCC-14 GND-7

11

POWER FAIL DETECT _, He He

He

He

U59

UBU r--------------------------------------------+-----------------------+--------------~~ USYSRESET.

Q1 3

2

U59 r-----~,~L---------------~----------------------~--------------~ CEO.

H14 SMa PC IMPLEMENTATION

6

091)

BATTERY BACKED 1

1 fL---t===1l~~AC20

r--_---"-1I""-"~ SMD 7

PURSD

1 CBB1 UMESVSRESET.C>---------~------~ )o"~----~------------------------------~~W---------~

R30 10K 91) J~ 14

StI) 2

U59

1,4,17 4

3

4 LOC_RESETe>------------------------------------------------------------------------------------~~~~------~

16

4

4

14

14

12 17 15 12

14

ABORT

3

RESET

TEST _RESETe e>------------l

3

H 14 SMa

R26, 2 4 1 +SU_---"'\M-...... -'-_' I U16 6 2~211.

-...... ~ --Ll ~ /b"------~,"vOKV----.+SU U6

16I1H~C> ~----------------------------------------------------------------------~~--------------}_----=91)~--------____ ~9~)~8~--------------------------------------_[) SYSRES. ~ 101.991)

74F125

-9

T I U16 8 ~ __ ~10~11 ~ ~--------------------------------------_c>

UCC-14

FAIL

TIMEOUT [) ________________________________________________________ ~~------------------------+_----------------~1~2r~UIT1U6~\ SND-7 I F~ ~l------------------------------~D

+SU 2Rl~ • ~l,.~ " U59. 11(91) 220

1~ ~4 91) StI)

~ '"~ ~.".,~ J9I) to;

ucc-••

~ UMEBBSY. __ u

--... A1 Vi UMEDTACK. ;=:;. A2

13 UMEBERR. A3 UMEAS. ;=:;. 11 A4 y 19

'----

U35 PASS [~>-______ ~~--~--------~12 ~'~' ____________ ~

2~~'! 1. 1 ~R1 r-Tif~ ~, +SU ~ ;'100..!r - ~C-~-14 0S2 IE 291) SND-7 - '< ~

~152 330 5KJ

1

UCC-14 SND-7

PASS LED

L-________________ ~U~51 StI)

U6 2 3

~------------~1~>9I)=------------.~ ! 74F125

OS~~ ~ 9-R151

330 91) 2

FAIL

LED

-

-

ABORT

LRESET

TSYSRESETe

SVSRES

UI1ESYSCLK

USYSFAIL.

UMEBERR.

BBSY

14

4

4

12,14

17

4

15,17

12

12 12 12,14

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D-17

CONNECTORS + v

~ P- FUFPY 1

SIll

I III 2 DISK

17 +12V 1 uoo 20 3

7 OCOI ~ 1 RYl RR 2 4

1 4 ~ 7 RX01 ,RY2 3 5 7 OSR1 , RY3 6 6 SERII=L f'ffiT 1 1 7 TX01 13= U'/

8 I 7 2 7 OTR1 8 3 7 CTS1 1 RY4 7

II 9 HlC 40--If: 5 7 RTS1 'llA3 9

10 KEY/ NJ pro 50--If: 7 RII 'RY5 11 6

17 -12V 'USSGK: 11 '----- 7

1~8S-8 9

'C886 10

1~ 1~ 11 12 13

~7 14 15 16 17 18 19 20 21 22

+~ 23 24 25

~ ~ 26 27

SIll

III1

1 2B 1 20

2 29 17 +12V UOO , ..... 3 7 DCD2 1 RYI

2 4

30

7 RXD2 1 RY2 .4

5 31

7 OSR2 1 3 6

32

7 TX02 , RY3 6 I

SERII=L f'ffiT 2 33 13= 8 7 34 7 OTR2 8

7 CTS2 1 RY4 7

II 9 '-----

5 7 RTS2 'llA3 9

10 7 RI2 ~ 'RY5

11 11

17 -12V 'USSGK: '---- f"R<A..l..EI.. f'ffiT

1~888- ~1 1

'eee7 2 PI: _II

1~ .1l.F 3 PC lSlll ~7 4 PC 2

5 PO( 6 PC 4 7 pr. s 8 9 PC 7 10 11 12 TEST INTERFRCE 13 14

D( 0 '15)::-' 15

1 P3 16 1 17 11 ~ o 0) 4 ~ 1 3 ~ 2 6 ~ 5 ~ 4 8 ~ 7 ~ [6 10 ~

7 9 -PROCLK~

2 1 12 1 CPURS 14 1 RDS_ 19 1 HOLD 1 RERDY_ 18

1 HLOR 20 13 1 8HE_ 17 15 TEST _RESET-~ R,: 0 15 16

1 R(o'23)~

+r

lfR146 !; R134 ,!;R133 9~Jo32 150 150 150 SIll SIll SIll SIll

11141 2'/" 2 ' /., 21/411

~llA'\ J'""'I PO(o'7) 7

t~~~ ~ PRCK 7

P8VSY 7 PE 7

SELECT 7 RlJTCFEED 7 PERR!R 7 INIT 7

~ SELIN 7

"'" A

!;~29 SIll

21/411

-i-f-

. ~ I~


REVI5JDI £LlD( _ .... .......... .. - lit _

i"R'lHCTtRW3 RELEASE SItS

"8 fRI,C_ 7

J'""'I ORRTEo 7

8 mx- 7 ~1~~ +5V ~ MOl_ 7 2./1<

SIll

F~ 7

~ FDSl_ 7 ~lS7~ 5V

~~ 7 2./1< SIll

~ 7

J'""'IFS~ 7

"8fl.v. 7

~ FhE- 7

-'""' FTKO- 7

~~ 7

~~ 7

J'""'I~ 7

~[)(}Q 7

C' STR08E 7

I- I- I- I- I 7 _ ....

0 i =.-:r X ~ com 1IUNE,tGDIIIR<..,.. 6 8 --~) n. 8 ......... , fP' SCHEMATIC C

~ .......... XUME-688

~ ;---... =.-::==~~ ~ a.I ...

II =""5.~~ ~' 72688C-O 01


~18

13 VO( 0 '15) VO( 0) QAl UDO etA2 ctA3 etM etAS etA6 eA7 ctAII eA9 -15 VME5Y5CLK '-' .AIO "AU

12 UME051. ctA12 12 UME050. = ctA13 12 VMElJRITE. ctAl4

- (tAIS 15 VMEDTACK. '- ctAl6

ctAl7 12 VMEAS. eAlB

.R19 11 VMEIACK. = ctA20 14 VMEIACKIN* = ctA21 14 VMEIACKOUT. ctA22 11 VMEAM4

~ VA( ctA23 13 VA( 1'23) ctA24

VAl ctA25 ctA26 VAl 4 ctA27 VAI3 ctA2B VAl 2 ctA29 VA(l) ctA30

16,lB -12V ctA31

VMEBB5Y. +~ ctA32 12 ct81

::;:::= ct82 ct83

12 VMEBGOIN* ct84 12 VMEBGOOUT. ctB5 12 VMEBGIIN* = ct86 12 VMEBGI0UT. = ct87 12 VMEBG2IN* etBB 12 VMEBG20UT. == et~

12 VMEBG3IN. == GBID 12 VMEBG30UH et811 12 VMEBRO. == et812 12 VMEBR1. ct013 12 VMEBR2. == etS14 == 12 VMEBR3. <tSIS

I«>-- IIS16 11 VMEAMl ct817 11 VMEAM2 eS18

I«>-- .019 _820

::;:::= _821 .. 822

14 UMEIRC* ( 1 07 ) .. 823 .. 824

UMt 1I<{,I. .. 825 .. 826 UMt.lI<{,I_l4 .. 827 UMEIRQ·.oS

~~~ .. -.. 1129 .. -t«l-- .. 831 +SV V (6) .. 832

"Cl V (9) .. C2

1 .. C3 .. C4 1 .. CS

1 .. C6 1 1

.. C7

.. ca

.. 1:9 4 VME5YSFAIL. "elD 15 VMEBERR. ..C11 4 UME5Y5RESEH = "C12

::;:::= ctC13

VA(23) etCt4

VA(22 eCIS .e16 1 .. C17

UHI~U .. C1B UHl19 .C19 UR 16 .. C20 VAl .. C21

1 .. C22 .. C23

1M 14 .. C24 UR loS .. C25 UAl12

7 VAl .. C26 .C27 .. C2B

UHIB. .. C29 .. C30

16 +12V .. C31 .. C32

l~J-33 lC835-74 lf2B lC3 lCl lp41 1 C2 _llF • 2 UF • 22UF • 22UF • 22UF • 22UF

+SV

lSKl "fSKl 11~V ~ REPEAT-33 ~REPEAT-40 ~ SKl

Pl JUMPER CHART P2

000 001 002 003 004 DOS 006 007 6Nl S'I'SCLJ(

6Nl OSl_ OSO_ IRITE_ 6Nl DTA:](. 6Nl -6Nl IACK_ ~ IACKI1JT_

<H4 A07 A06 AOS A04 A03 A02 AOI -12\1 +5U BBSY_

~ ACFAlL_ BGOD* BGOI1JT_ BG1D* BGlWT-BG2D* BG2DJT_

BG3D* B&3I1JT_ BRO_ ----'"' -IK! ~

6Nl SEAI1K SERMT_ 6Nl ~ ~

:mas--~ ~ IRQl_ +5U S1lJBV +5U 009 009 010 011 012 013 014 015 6Nl S'l'SFAlL_ ~

5'I'SRESET-~

FItS A23 A22 A21 A20 Al9 Al9 Al7 Al6 A15 Al4 Al3 A12 AU AlO A09 AOB +12\1 +5U

JUMPER PAGE NO.

Jl 3 J2 15 J3 9 J4 4 J5 9

J7 4

JB 3

+SV.---------------~

+SV+--i===:::j

+SV_-t=====~

"'A1 etA2 .. A3 .. M .. AS .. A6 eA7 ctAII .. 119 ctAIO • All ctA12 ctA13 .. Al4 .. AlS <tAUS .. Al7 eAIB .. Al9 .. A20 .. A21 .. A22

15 UBU .. A23 .. A24 .. A25 .. A26 etA27 etA2B eA29 etA30 etA31 etA32 et81 et82 et83 .. 84 etB5 et86 et87 etBB et~

.810

.Sl1 ,,812 ,,013 et914 <t815 ct916 ct917 eS18 .019 .. -.. 821 .. 822 .. 823 .. 824 et825 .. 826 .. 827 et_ etll29 et_ et_ ct832 etC1 ctC2 ctC3 ctC4 ctCS etC6 .. C7 eca e1:9 etC10 eC11 etC12 eC13 eC14 eC1S etC16 eC17 eC1B eC19 eC20 ctC21 etC22 .. C23 eC24 .. C25 .. C26 eC27 .. C2B .. C29 .C30 .. = .. C32


I0I1l _ .... - ....... I11III

A

+

~19

SPARES

I«:

1_ GNO-7 SKl

I«:

1_ SKl

I«:

14D611 SKl

I«:

1_ SKl

I«:

505 VCC-14 GNO-7

RI0B lAJv-,}

La< SKl

161 13 I«: -161 3 I«: -161 4 I«: -161 15 I«: -16 1 14 I«: -

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2

2

9 5

2

5

2 2

ATSAC 0 '19)

ATSDCO'15)<:~------~

+ U

~'W !H)

2

+ U

!;!~~~1 !H)

1

A1 lDD«:K_ Ai! 51)(7)

ATIOCt£KeO r-.---+-1I-A~lT=SD=C"'-----+--"""--~ A"

A3 5I)C6) M 51)(5)

AS SO(4) All 50(3) ff) 50(2) All SOCl) III 51)(0)

A10 lIDRlV A11 AEN A12 M(19)

A13 SAetS) AH SAC1?) A1S SAC 16)

ATSAC1 A" [16

--' A16 9lClS) - Ai:> 5A(14)

A1S SAC 13) A19 SACt2) A20 SACll) A21 SAUD)

[ 1: [11

;AC 10 SA(9) SACS)

.. SA(7) SA(6)

A26 SACS) SfU4) SA(3) SA(2)

A30 SAC!) A31 SAeO) rr02 6N)

ATLAC 20 '23) 8D----+-lI-----,

r----- co 6N)

ATSBHEe :::- A" _AC '3 C1 59£e C2 l.A(23)

A' I'll?? C3 l.A(22)

~ISA(19) A" Jl(20 C4 l.A(21) C5 l.A(20) a; LA(19)

ATSAC18 C:> l..A(18) TSAC 1 C8 LAC 17)

~~=~ C9 -C10 -C11 50(8) C12 50(9)

DC LO C13 5[)(10) DC 11 C14 5[)(11)

;OC 1 C1S SO(12) C16 51)(13)

C1:> 51)(14)

C1S SO(lS) >--- C19 CKEY)

PXTl

6N)

AESElIRU +5U

lRQ!I

--5U IHl2 -12U ous-+12U

CKEY) !HJ'I.je

~

m» lIRO ~

~ lRX1_

!RI1 REF_

S'I'm.J(

= lRQ6

IRQS lR04 lRQ3

IR](2e

T/C ~ +5U osc 6N)

6N)

PATl

6N)

P1EHCS16e :rIX:S16e

IRQ10 IRQ11 IRQ12 IRQ1S IRQH

lRXOe !RIO

DACI(5e

IRIS lRX6e

IRl6 OAlOe

IRl:> +5U

msTERe 6N)

6N)

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ RlGRIG _____ RNSRNSRNSRNSRNS

10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K

< <

1 2 1 3 5 '7 9 .. 8 14 12 10 &:Ir--

+5U 17

Ie

12U 17 Ie +12U 17

sur--B1 B1 B1 B1 B1 B1 B1 B1 B1

A

ATRESETDRV

~ ATIRQ9

~ ATDRQ2

~ ATSI1El"'Je ATSME/1Re ATIoue ATIORe ATDACK3e ATDRQ3

ATOACI<le ATDRQ1

ATREFe ATSYSCLK

ATIRQ7 ATIRQ6 ATIRQ5

5

9

7

2 2 2 2 1 1 1 1 4 5 7 7 1


82·.---~--------------------------------------------------------------~--~_r----------------_L/ ATIRQo4 7 ATIRQ3 7

ATIlACK2e 1 ATTIC 1 ATFLE 4

+5U 0 ATOSC 4

+iU

16 16 16 16 16 16 16 16 16 16 16 16 16 RIG RIG RIG RIG ______ RNS RNS RNS

10K 10K 10k 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K

567824681211257

0-0 ATMEMCSl6e 1

ATIIlCSl6e 8 ATIRQ10 14 ATIRQ11 1 ATIRQ12 3 ATIRQ15 1 ATIRQ14 8 ATDACKoe 1 ATIJRQO 1

01 ATIJACII(Se 1 D1 ATDRQ5 1 01 ATIlACK6e 1 01 ATIJRQ6 1 01 ~ ATllACK7e 1 01 AT0RQ7 1 01 +5U 01 Ie 01 r--01 r--

;.

I 7 ---

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~20

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