TahirGhani Intel Talk

7/31/2019 TahirGhani Intel Talk

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Tahir Ghani

Intel Fellow and Director,

Transistor Technology and Integration,Intel Corporation

Innovative Device Structures and New

Materials for Scaling Nano-CMOS

Logic Transistors to the Limit


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Key Messages End of traditional dimensional scaling era

New and rapid innovations in transistor structure and

materials are now key to sustaining Moores Law:

Uniaxial strained silicon and HiK + Metal Gate

Power Limited Era: New Transistor Architectures areneeded to meet the performance improvements whilekeeping within power budget

Nanoscale Design Rule Regime: Dimensional scaling doesnot mean better transistor performance.

This is the most exciting time to be doing transistor researchand development


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Outline End of Traditional Scaling EraTraditional scaling limiters and implications

Intels Response

Uniaxial Strain (90nm and 65nm Nodes)

HiK + Metal Gate + Strain (45nm Node)

Challenges and Solutions Beyond 45nm Node

Uniaxial Strain: Ultimate limit of silicon mobility enhancement

Power Limitation: Implications on future transistor structures

Parasitics Dominated Era: How to address increasingnegative impact of parasitics?

New Channel Materials: III-V QW FETs at Vcc~0.5-0.7V

Key requirements for implementing

III-V channels into mainstream?


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Geometric Dimensional Scaling Era

Gate Oxide Thickness Scaling

- Key enabler for Lgate scaling

Junction Scaling- Another enabler for Lgate scaling

- Improved abruptness (REXT reduction)

Vcc Scaling- Reduce XDEP (improve SCE)

- However, did not follow const E field

1990s: Golden Era of Scaling

Dramatic Vcc, Tox & Lg scaling. Increasing Idsat

R. Dennard et.al.IEEE JSSC, 1974


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Gate Leakage

Mobility Degradation

Parasitic Resistance

SOURCE DRAIN

GATE

Gate leakage

Mobility Degradation

Top Traditional Scaling Limiters

Top Scaling Challenges faced by Intels90nm CMOS Research Team in 2000

Parasitic Resistance


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1.E-03

1.E-02

1.E-01

1.E+00

1.E+011.E+02

1.E+03

1.E+04

0.5 1.0 1.5 2.0 2.5

TOX Physical [nm]

JOX

[A/cm2

]

180nmNitrided SiO2

SiO2[Lo et. al, EDL97]

130nm

Jox limit

T. Ghani et. al. VLSI Symp. 2000

Mobility(cm

2/(V

.s)

100

150

200

250

300

0 0.5 1 1.5

E EFF [MV/cm]

NA=

3x1017

1.3x1018

1.8x1018

2.5x1018

3.3x1018

Universal

Mobility

SiO2

Scaling and Mobility Reduction Trend

Gate Oxide Leakage:

Direct tunneling limited.

Running out of Atoms

Significant mobility reduction

due to channel ionized

impurity scattering


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Parasitic Resistance Impact

Salicide interface resistancebecoming a significant

component of REXTdue to salicide area scaling

S/D doping close to solidsolubility in Si (Nsurf)

Solutions:Solutions:

Barrier height reduction

Higher dopant activation(Exceeding solid solubility )

Gate Gate

Salicide

)4

exp(*

surf

Bc

N

m

qh

SilicideSilicide

SiSi

EEFF

EEGapGap

EEVV

EECCBB


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Intels Response

Uniaxial Strain (90nm and 65nm Nodes)



Higher Strain: Ultimate limit of silicon mobility enhancement?



New Channel Materials: III-V QW channels at Vcc~0.5-0.7V


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Innovations Introduced by Intel toOvercome Traditional Scaling Barriers

Uniaxial process induced strain innovations for dramatic

mobility enhancement starting at 90nm CMOS node

- Epitaxial SiGe S/D

- SiN Capping Layers

HiK gate insulator being introduced at 45nm CMOS

node to replace SiO2 to help address gate leakage

Metal Gate being introduced at 45nm CMOS node to

replace poly-silicon gate to enable Tox(e) scaling


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Why is Low Field Mobility Important

for Nanoscale Transistors?M.M. LundstromLundstrom et. al., EDL 1997et. al., EDL 1997

Conventional theory assumes infiniteConventional theory assumes infinite

supply of carriers at the sourcesupply of carriers at the source

ss(0) and I(0) and IDSATDSAT limited by lower oflimited by lower ofthe two velocity termthe two velocity term UUltimatelyltimately

limited by thermal injection fromlimited by thermal injection from

source to channel (ballistic)source to channel (ballistic)

Best devices in production todayBest devices in production todayare ~ 60% ballisticare ~ 60% ballistic

Equal contributions by ballisticEqual contributions by ballisticand mobility termsand mobility terms

Low field mobility importantLow field mobility importanttoto nanonano--MOS transportMOS transport

)(0

11

(0)s

1

(0))]V(V[CWI STGSGDSAT

++=

=

Eeffinj

EcEc (x)(x)

EcoEco

Position (x)Position (x)Energy

Energy

llllllll

Source-Barrier

ttccrrcc


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Uniaxial Strain Silicon Transistors

Intel: IEDM 2003PMOS NMOS

SiGeSiGe

These transistor structures introduced first at Intels 90nm

CMOS node. These structures have now become

industry standard for strain implementation

T. Ghani et. al. IEDM, 2003


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PMOS Strain Implementation SiGe epitaxial S/D

Formed by Si recess etch

and selective StrainedSiGe epi growth

Strained SiGe induceslarge lateral compression

in channel Valence bands warpage

and LH-HH splitting

Dramatic mobility gain

SiGe S/D also improvesparasitic resistance by reducing

salicide interface resistanceLateral compression in channelLateral compression in channel

SiGeSiGe

UniaxiallyUniaxially StrainedStrained SiGeSiGe EpiEpi S/DS/D

T. Ghani et. al. IEDM, 2003


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Strained SiGe S/D Reduces

Salicide Interface Resistance Strained SiGe has smaller Eg Smaller hole barrier height

at silicide interface

Exponential reduction ofinterface resistance on B

Higher boron activation inSiGe relative to Si ( Nsurf)

Dramatic reduction in sal interface

resistance with strained SiGe S/D

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E+19 1.E+20 1.E+21

Doping Concentration (cm-3)

Resistivity(ohm-cm2) BB = 0.5eV= 0.5eV

BB = 0.4eV= 0.4eV

BB = 0.3eV= 0.3eV

BB = 0.2eV= 0.2eV

SiGe

B

SiGe (Nsurf)

EEFF

BB

SilicideSilicide Si orSi orSiGeSiGe EECC

EEVV SiSi

EEVV SiGeSiGeEEVV

)4

exp(*

surf

Bc

N

m

qh


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Uniaxial Strain Performance Gain (Intel)

65nm CMOS Node

00

IdlinIdlin

PMOSPMOS

2020

4040

6060

8080

DriveGain(%)

DriveG

ain(%)

00

55

1010

1515

2020

25253030

Drive

Gain(%)

Drive

Gain(%) IdsatIdsat

IdlinIdlin

NMOSNMOS

IdsatIdsat

Ref: Unstrained Silicon

Uniaxial strain has demonstrated dramatic PMOS and NMOS

performance improvement on 90nm & 65nm CMOS nodes

2.2x Mobility 1.5x Mobility


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Innovations Introduced by Intel toOvercome Traditional Scaling Barriers

Uniaxial process induced strain innovations for dramatic

mobility enhancement starting at 90nm CMOS node

- Epitaxial SiGe S/D

- SiN Capping Layers

HiK gate insulator being introduced at 45nm CMOSnode to reduce gate leakage

Metal Gate being introduced at 45nm CMOS node toreplace poly-silicon gate to eliminate poly depletion:Scale Tox(e)


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IEEE Spectrum October, 1969

28

Thermal Oxidation and Poly Silicon Gate:

KEY TO MICROELECTRONIC REVOLUTION

SiO2

Growth Technology: Enabled MOS transistor to become a reality

Poly Silicon Gate: Key to Self Alignment Device Scaling

Poly /SiO2 gate stack was the foundation on which

IT revolution has been built. Served well for 40y BUT


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1E1E--66

1E1E--44

1E1E--22

1E+01E+0

1E+21E+2

1E+41E+4

55 1010 1515 2020 2525

EOT (A)EOT (A)

JJ

oxox

(A/cm

(A/cm22)) SiOSiO22 dielectricdielectric

HiHi--KK

dielectricdielectric

BENEFIT:BENEFIT:

Significant gate leakageSignificant gate leakage

reduction at a given EOTreduction at a given EOT

SiO2SiO2

1.0x1.0x

1.0x1.0x

HighHigh--kk

1.6x1.6x

< 0.01x< 0.01x

Capacitance:Capacitance:

LeakageLeakage::

Gate Leakage Reduction withGate Leakage Reduction with HiKHiK

SiliconSiliconsubstratesubstrate

GateGate

electrodeelectrode

HighHigh--kk

SiliconSilicon

substratesubstrate

1.2nm SiO1.2nm SiO22

Poly Si GatePoly Si Gate

electrodeelectrode

Intel 65nm NodeIntel 65nm Node HiKHiK Gate DielectricGate Dielectric

M. Radosavljevic et. al., Intel Corp. DARPA CMOSNano, 01/12/04


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Metal Gate Eliminates Poly Depletion

-2.0 -1.0 0 2.01.0

Vgs (V)

Cgate

Change with Tox

True Tox change

Capacitance benefit everywhere

Both Idsat and SCE improve

Inversion

MG eliminates poly dep (inversion)

Increases gate E-field

Larger QinvHigh Idsat

Tox (inv) scales significantly

BUT! Tox(e) does not impact SCE

-2.0 -1.0 0 2.01.0

Vgs (V)

Cgate

Change with MG

Inversion

Poly depletion

improvement

No Ioff

benefit


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Transistor Drive Current (rel.)

>25%Higher Drive

65 nm 45 nm

10

100

1000

0.5 1.0 1.5

LeakageCurrent

(nA/um)

Source: Intel Internal

High-k+Metal Gate

Performance / Power BenefitsTransistor Performance vs. S/D LeakageTransistor Performance vs. S/D LeakageTransistor Performance vs. S/D LeakageTransistor Performance vs. S/D Leakage

>25% Idsat gain demonstrated for

45nm CMOS vs. 65nm CMOS at fixed Ioff


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Extensive R&D done at IntelExtensive R&D done at Intel

to successfully address theto successfully address the

significant Material,significant Material,Integration andIntegration and

Manufacturing challengesManufacturing challenges

in implementingin implementing HiKHiK + Metal+ Metal

GateGate CMOS Technology.CMOS Technology.

Right Metal Gate MS electrodeswhich are HiK compatible

Bulk & interface traps:Poor reliability (Need better thanSiO2 reliabilty due to higher E)

New scattering modes:Poor mobility

Technology Integration

Yield / Manufacturability

Top Issues with Hi-k + Metal Gate

CMOS Technology


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HiK Mobility Challenge

Metal Gate recovers ~50% of the

degradation. Further stack optimization

is required for mobility improvement

Model: High-k dipoles vibrate !!

Mobility degradation due to

to scattering with soft optical

vibrational modes of dielectric

Very high charge density of MG

screens dipole vibrations.

NMOS mobility with high-k

degrades ~ 40% from

SiO2 / poly stack

ELO

Gate

High-k dielectric

Si channel

e-

+ -

-+Eg

ELOEg

ETOT=ELO+ Eg

M. Fischetti et. al. J App Phys, 2001

R. Kotlyar et. al. (Intel)

IEDM 2004


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Metal-Hf based Oxide system susceptibleto oxygen vacancy sites Efficient

electron traps located in upper half of

HfO2

bandgap: Well documentedin literature

These traps are responsible for NMOShysteresis, BT and TDDB

Key to reliability is passivating Vo sites

HiK/Metal Gate intrinsic reliabilityrequirement more stringent than best

SiO2 because they need to withstandhigher E-Field

K. Torii, IEDM, 2004

J. Mitard, IRPS, 2006

Effective Solutions to Bias-Temp

and TDDB are Key to

HiK + Metal Gate Implementation

High-K Reliability Challenge


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HiK - Dual Metal Gate Integration

Gate FirstGate First Gate LastGate Last

- Stability Right MS N & P metalswhich survive high thermal anneal

- Dual metal gate stack patterning

+ Standard process flow

+ Metals deposited afterhigh Dt More MG options

- Non-std process flow

Si

Poly

HiHi--KK

MetalMetal

NN PP


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Intels 45nm Node HiK/MG Transistors

Low Resistance

Layer

Integrated 45 nm

CMOS process

High performance

Low leakage

Meets reliability

requirements

Manufacturable

in high volume

High-k DielectricHafnium based

Silicon Substrate

Work Function MetalDifferent for NMOS and PMOS

45nm HiK + Metal Gate CMOS technology meetsmeets performance, yield and reliability goals

The implementation of highThe implementation of high--k and metal gate materials marks the biggest changek and metal gate materials marks the biggest change

in transistor technology since the introduction of polysilicon gin transistor technology since the introduction of polysilicon gate MOS transistorsate MOS transistors

in the late 1960s.in the late 1960s. Gordon MooreGordon Moore


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Worlds First Working 45 nm CPUwith HiK + Metal Gate

Worlds first working 45 nm CPU

Intel Penryn: 45nm CPU

Jan 2007

45nm SRAM Test Vehicle

Jan 2006

> 1 Billion Transistors

45nm SRAM Test Vehicle has >1B transistors

On track to ship 45nm CPUs in 2007


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Intels ResponseUniaxial Strain (90nm and 65nm Nodes)








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How Far Can Uniaxial Strain

Extend Si Performance Gains?

Significant headroomSignificant headroom leftleftto increase PMOS mobilityto increase PMOS mobility

in future (> 5x)in future (> 5x)

Mobility gain driven by hole meff

reduction due to band warpage !

Limited Max Mobility GainLimited Max Mobility Gain

for NMOS (~ 2x).for NMOS (~ 2x).

Maximum gain limited by

fundamental physics

0

1

2

3

4

5

6

0 1000 2000 3000

Channel Stress (Mpa)

MobilityEnha

ncem

entRati

PMOS

NMOS

Source: Intel(100)/

Channel=Si

EEFF

=1MV/cm

Today


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Implications of Significantly Higher

PMOS Mobility Enhancement

Expect NMOS and PMOS

mobility values toapproach each other

PMOS device drive strengthto approach NMOS in future

N/P ~ 1 N/P Symmetry

Device sizing in circuitsDevice usage model

1.0

1.5

2.0

2.5

3.0

0 1 2 3 4 5 6 7

Technology Node (nm)

N/PIdsatratio

250 180 130 90 65

Source: Intel

?


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CPU Transistor Count Trend

2x Transistors Every 2 Years

In Line with Moores Law

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1970 1980 1990 2000 2010

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

40048008

8080

8086

286 386

TM

486TM

Pentium CPU

Pentium II CPU

Pentium III CPU

Pentium 4 CPU

Itanium 2 CPU

2x increase every2 years

Penryn QC


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Negative Consequence of

CPU Transistor Count Trend

Right Hand Turn: Power Dissipation Limited to ~100W

BUT increased transistor count neededBUT increased transistor count neededin Multiin Multi--Core CPU Era !!!Core CPU Era !!!

CPU Power (W)

10

100

1000

1990 1995 2000 2005 2010 2015

CPU Power (W)

10

100

1000

1990 1995 2000 2005 2010 2015


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Multi-Core CPU Power Limited EraP = Switching Power + Leakage Power + ..

~ (fCgateVCC2 ) * N

RelativeV

RelativeV

CCCC

Relative Transistor CountRelative Transistor Count1x1x 1.5x1.5x 2x2x

Fixed PowerFixed Power

1x1x

VVCCCC scaling required for continued increase in transistorscaling required for continued increase in transistorcount in power limited worldcount in power limited world

Key Issue withKey Issue with VccVcc Scaling: Performance loss !!!Scaling: Performance loss !!!

How to maintain high performance at scaled VHow to maintain high performance at scaled VCCCC??

Constant


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Multi-Gate Transistor ArchitectureV=0

V=0

V=1V=0 WsiDrain

Lgate

Gate

Gate

Source

Wsi=20nm

Wsi= 10nm

Si

AqN

yx

=

+

2

2

2

2

M. Stettler, 2006 SINANO Device Modeling

MultiMulti--Gate Transistors have better SCE:Gate Transistors have better SCE:

+ Gates in close proximity+ Gates in close proximity

reduce spread ofreduce spread ofVVdraindrain+ Small+ Small WWSiSi desired to minimize SCEdesired to minimize SCE

+ At very thin+ At very thin WWSiSi, channel, channel

potential impervious topotential impervious to dopantsdopants

MutigateMutigate transistors have highertransistors have higher

mobility due to:mobility due to:

+ Lower channel doping+ Lower channel doping+ Lower+ Lower EEeffeffin channelin channel


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Multi-Gate Transistors Enable Vcc Reduction

MUGFET

Planar Si

NMOSR. Chau et al., ICSICT 2004

DG (Midgap gate)

D. Antoniadis, NIST Workshop, 2001Leakage Power Improvement

at Iso Performance

Inverter

Voltage

%I

mpro

vement

Larger improvementat lower Vcc

Simulation: Intel

Multi-Gate Transistors show superior

DIBL & Mobility: Lower Vt at a given Ioff:

Better gate overdrive vs Vcc.

Higher mobility vs Planar:

More so at lower lower Vcc

Power-performance tradeoff scalesbetter (vs Planar) as Vcc is reduced


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Multi-Gate Transistors:

Implementation and Design

FinFET / Tri-Gate Transistor:

++ Self Aligned structure-- Non-Planar structure

Tri-Gate Transistor


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Tri-Gate / FinFET

Value PropositionPerformance / Power:

+ Scale better at lower Vcc: Reduce Active Power OR

Better mobility & lower Vt+ Operate at lower Leakage Reduce Standby Power

+ Lower Channel Doping Lower BTBT: Lower IJUNCTIONLower Cjp: Performance gain

Reduce Standby Power

Random Dopant Fluctuation:

+ Lower Channel Doping Lower RDF. Better SRAM Vmin?

Multi-Gate Transistor is a serious contenderfor post-45nm CMOS nodes due to its

many fundamental advantages


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Process Challenges in Fabricating

Tri-Gate / FinFET Transistors

J. Kavalieros et. al. (Intel)

VLSI Symp 2006

A. Dixit, K. Anil et al.,

Solid State

Electronics, 2006

NonNon--PlanarityPlanarity

Implementing high levelImplementing high levelof channel strain:of channel strain:

-- Planar Ref= Highly strainedPlanar Ref= Highly strained

and optimized deviceand optimized device

HigherHigherRextRext::-- SelectiveSelective epiepi S/DS/D-- Minimize spacerMinimize spacer

Process control:Process control:

-- Fin width controlFin width control-- Poly sidewall profilesPoly sidewall profiles

These concerns need to be successfullyThese concerns need to be successfully

addressed foraddressed for TriGate/FinFETTriGate/FinFET TransistorsTransistors

to become mainstream.to become mainstream.


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Density Scaling on Track (Gate Pitch)

0.1

1

1997 1999 2001 2003 2005 2007 2009

Contacted

Gate Pitch

(micron)

Source: Intel

Pitch

0.7x scaling

every 2 years

Gate pitch scaling continues to follow Moores Law

showing 2x transistor increase per area every 2 years

D i C t D d ti


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GateGate

SpacingSpacing

SS DD

Shared Source DrainShared Source Drain

IOFF = Fixed

Beyond 45nm node, gate pitch scaling dramatically drive currentdramatically due to increased resistance (shrinking S/D contact area) Dramatic performance gains expected if salicide interface resistance

can be reduced.

Past: Yield vs. density tradeoffFuture: Transistor performance vs. density trade-off (NEW PARADIGM)

Drive Current Degradation

with Gate Pitch Scaling

0.60

0.80

1.00

1.20

1.40

1.60

240nm 180nm 120nm 90nm 65nm 40nm 25nm 25nm,

Rsal-

Int~0Gate-to-Gate Spacing

Idlin (normalized)

Idsat (normalized)

45nmNode

90nmNode

Shared Source DrainSpacer=10nm


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Innovative Solutions for

Salicide Resistance Reduction

1 Increase S/D dopant electrical activation

above solid solubility:

Non-Equilibrium regime

2 S/D bandgap engineering to reduce barrier

height: Example: Strained SiGe S/D

3 Explore new salicides with reducedbarrier height: Dual Salicide

2 + 3 Key Challenge:

Interface states dominate band

alignment (Fermi level pinning).

Need to develop effective interface

passivation techniques

)4

exp(*

surf

Bc

N

m

qh

Silicide

Source / Drain

SilicideSilicide

SiSi

EEFF

EEGapGap

EEVV

EECC

BB

F i L l Pi i


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Fermi Level Pinning

Yeo, King and Hu, JAP, 15 Dec 2002 )()1()( CNLCsMn EESS +=

)( sMn =

)( CNLCn EE =

Ideal

Pinned

Fermi Level Pinning: Barrier height insensitive to metal work function

Suppress Fermi level pinning by passivating dangling bondsEnables dual-metal work function materials with M near Ec and Ev

OR Effective barrier pinned close to desired level (Ev or Ec)

)()1()( CNLCsMn EESS +=

ECNL

n

)( sMn =

)( CNLCn EE =

Ideal

Pinned

Ec

Ev


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Challenges and Solutions Beyond 45nm Node Higher Strain: Ultimate limit of silicon mobility enhancement?





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High Mobility n-Channel Materials

Source: A. Pethe (Stanford)


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Ultimate Channel: Ballistic Transport

CCGG

Quantum Capacitance

important at thin TOX

)(0

11

(0)s

1

)V(V(0)WCI TGSSGDSAT

++=

=

Eeffinj

*

TGSGDSAT

2kT

)V(VWCI

t

inj

inj

m

=

=

EcEc (x)(x)

EcoEco

Position (x)Position (x)

Energy

Energy

z

0

VVGG

TTOXOX

NNINVINV z

0

VVGG

TTOXOX

NNINVINV

~t

*

1111

minj

Ballistic

2

*2

~h

mqC DOSINV

High Performance in Ballistic Regime:

1. Low mt along channel direction High inj Maximize IDSAT

2. High mDOS High CGATE High QINV Maximize IDSAT

**

**

eff

High Mobility III-V Channel= High Performance?


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High Mobility III-V Channel= High Performance?

Weaklyquantized

Stronglyquantized

III-V materials (GaAs, InSb, InAs) beinginvestigated due to small -valley m* inj IDSAT

However, lower m* leads low DOS QINV IDSAT

-valley lifts up due to confinement (1/m*)Charge transfers into X & L valleys with high m*

inj IDSAT

Small EG (InAs, InSb): High BTBT leakage

Tailor bandgap by QW confinement

Higher:::: Higher sub-T slope (poor SCE)

Projecting III-V NMOS performance based

on simplistic models could lead to erroneous

performance assessment. Need detailed

physics modeling + fabricate devices

K. Saraswat,

INMP 2005

Requirements for Building a Competitive


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Requirements for Building a Competitive

III-V Channel Transistor Technology(VCC~ 0.5-0.7V)

Integrate III-V layers on large Silicon wafers

Develop HiK dielectric compatible with III-V channels

Determining PMOS material to go with NMOS

Insertion 15nm node or beyond. Meet LG< 20nm.III-V devices may need to be Tri-Gate / FinFET structure.

It is expected to be scalable beyond first node.

III-V channel materials will have to simultaneously meetmultiple requirements to be serious contenders as

replacement for Strained-Si channel transistors

Transistor Feature Set Mapping


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Transistor Feature Set Mapping

to CMOS Nodes: Potential Roadmap

Process inducedstrain+ (2nd gen)

Gate Oxide withpoly-Si Gate

NiSi

Hik + MG (Intel)

Process inducedstrain ++

NiSi

HiK + MG(Intel: 2nd Gen.)

Process inducedstrain +++

NiSi

Alternative waferorientation?

Dopant super-activation?

HiK + MG (3rd

gen) Process induced

strain ++++

Alternative waferorientation?

Dopant super-activation?

Multi-Gate FETswith strained Si?

Next generation

silicide /contacts?

65nm Node65nm Node 45nm Node45nm Node 32nm Node32nm Node 22/15nm Nodes22/15nm NodesTODAYTODAY

Challenging but feasible roadmap for scaling

logic CMOS technology down to 15nm

CMOS Node with Si Channel.


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S mmar / Ke Message


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Summary / Key Message Transistor structure and material innovations pioneered at

Intel such as uniaxial strained silicon and high-k/metal gate

have enabled Intel to scale planar CMOS beyond 90nm node.

Achieving high performance at low Vcc is critical in a powerlimited world and will play important role in transistor

architecture and front-end feature set selection.

Multi-Gate transistors have potential to improve performancevs. power tradeoff and enable lower Vcc on products

Improving transistor parasitics is as important as improving

intrinsic transistor performance. Needs higher focus!!

Roadmap for scaling CMOS technology during next 10 yearsis quite challenging but feasible


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THANK YOU!

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