1 CAUTION: Th1-888-INTERSIL or 1
July 7, 2010TB486.0
Technical Brief 486
ISL6334EVAL1Z User GuideBoard Specifications 1. Intel VR11.1 compliant.
2. 4-Phase, 130W, 400kHz, Load Line = 0.8mΩ.
3. Socket: LGA1366, die sensing, can be configured for motherboard sensing.
4. 6 Layer Board: Top/Bottom - 0.5oz plated, 1.5oz finished; Internal Layer – 1oz.
5. Dual footprint for Intersil 12V (ISL6612A, ISL6622) and 5V drivers (ISL6596/ISL6620) for cost or efficiency optimization. With minor re-work, the board can also operate 12V drive for high-side MOSFET and 5V drive for low-side MOSFET.
6. Dual footprint for PowerPak and DPAK MOSFET for cost or efficiency optimization.
ISL6334EVAL1Z Board Brief DescriptionControl Power SupplyThere are two ways to provide 5VDC to this evaluation board: through ATX power connectors (J21) or Banana connectors (J5 and J0). SW1 is used to control the ATX silver box power supply.
Input Power Supply and External Load Connector12VDC input power supply can be connected to the board through the 4-pin ATX connector J4. Two test points, TPVIN and TPGND, are provided for input voltage measurement. Two connectors (J1 and J2) are provided for external load.
VR Enable SwitchOne switch (SW2) is provided for EN_VTT signal control. In “OFF” position, EN_VTT signal is shorted to ground and ISL6334 is disabled. Place SW2 in the “ON” position to enable operation.
PGOOD Indicator and Test PointsCR2 is used to indicate the status of VR_RDY (PGOOD) signal. When VR_RDY is high, the LED in CR2 will be OFF (no light); otherwise the red LED in CR2 will be on once 5V is applied.
Test points are provided for VR_RDY, IMON, VR_HOT and VR_FAN signals.
FIGURE 2.
FIGURE 1.
FIGURE 3.
FIGURE 4.
FIGURE 5.
ese devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights ReservedAll other trademarks mentioned are the property of their respective owners.
Technical Brief 486
VID (Figure 7)
VID code can be generated from Demo board (JP9 = DEMO) or VTT tool (JP9 = VTT).
PSIDynamic PSI signal can be generated from LGA1366 VTT or external function generator. Static, fixed PSI operation can be set through SW5. Placing the 0 switch in the “N” position, leads to the circuit operating in PSI mode.
Phase Count ControlR1P, R2P, R3P, RW2, RW3, and RW4 are used to set the phase count, as shown in Table 1. If phase count is different than 4, R1 and R5 must be adjusted accordingly for stability and correct load line.
FIGURE 6.
TABLE 1.
R3P R2P R1P RW4 RW3 RW2
4-Phase DNP DNP DNP 0Ω 0Ω 0Ω
3-Phase 0Ω DNP DNP DNP 0Ω 0Ω
2-Phase X 0Ω DNP DNP DNP 0Ω
1-Phase X X 0Ω DNP DNP DNP
NOTE: X = Don’t care.
Available Design Assist Tools1 Layout Check list.
2 VR Design Worksheet.
3 VCORE and IMON TOB Calculator.
4 Schematic is available in OrCAD format.
5 Layout is available in Allegro format.
Contact Intersil’s local office or field support for the latest available information.
FIGURE 7.
2 July 7, 2010TB486.0
3Ju
ly 7, 2
010
TB486.0
1
1
D
C
B
A
VCORE1
VCORE2
VCORE3
VCORE4
PWM1
PWM2
VCORE
VCORE
ISEN2-
ISEN1-
VCORE
ISEN3-
PWM3
VCORE
ISEN4-
PWM4
TitleSize Rev
Date: Sheet of
CISL6334 Burnside - 130W Rev C BoardB
1 3Thursday, December 20, 2007
65 Readington Road
Intersil Corporation
Somerville, NJ 08876
TitleSize Rev
Date: Sheet of
CISL6334 Burnside - 130W Rev C BoardB
1 3Thursday, December 20, 2007
65 Readington Road
Intersil Corporation
Somerville, NJ 08876
TitleSize Rev
Date: Sheet of
CISL6334 Burnside - 130W Rev C BoardB
1 3Thursday, December 20, 2007
65 Readington Road
Intersil Corporation
Somerville, NJ 08876
R2P and R3P and their traces should not beclose to any current sensing network.
CI or SI
connection
R1P
DNP
RW3RW4 RW2
DNP 0 Ohm 0 Ohm 0 Ohm
DNP 0 Ohm 0 Ohm
m DNP DNP DNP 0 Ohm
0 Ohm DNP DNP DNP
Phases Configuration
sation network must be adjusted accordingly.
Placement needs correction
RP3
1.82k
RP3
1.82k
RCI2DNP RCI2DNP
CF2470n
CF2470n
RCI3DNP RCI3DNP
CF1470nCF1470n
CF3470nCF3470n
RSI30 RSI30
RCI4DNP RCI4DNP
RSI40 RSI40
RSI10 RSI10
CC400.15uCC40
0.15u
CW3DNP CW3DNP
RCI1DNP RCI1DNP
RP41.82kRP41.82k
CC100.15uCC100.15u
44
CW2DNP CW2DNP
CF4470nCF4470n
RP21.82kRP21.82k
CC300.15uCC30
0.15u
RP11.82kRP11.82k
RSI20 RSI20
CC200.15u
CC200.15u
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ISL6334EVAL1Z Schematics
FIGURE 8. ISL6334 BURNSIDE - 130W REV C BOARD, CONTROLLER CIRCUIT
5
5
4
4
3
3
2
2
D
C
B
A
VCC5
Vc5
VCC5
Vc5
VCC5
VCC12
Vc5
Vc5
PSI#
RGNDVSEN
VID1VID2VID3VID4VID5VID6VID7
EN_VTT
VID0
VR_RDY
ISENSE
ISENSE_DN
VSS_SENSE_DIE
Intersil Confidential
Controller circuit
~27ns RC TimeConstant
SET R5+R1=R334;Average OC=100uA
RN2 = Vishay, NTHS0805N02N6801
Expose these traces on external layers
RSS2
SI - 1P
RSS1
DNP
RFS1
TO GND
RFS2
SI - 2P
CI - 1P
CI - 2P
TO Vc5DNP
DNP
DNP
TO GND
TO GND
TO Vc5
TO Vc5
DNP
DNPTO Vc5DNP
DNPTO GND
Phase Dropping Decoding
Place this close to the socketDNP0 Ohm
R3P R2P
DNPDNP4-PHASE
3-PHASE
2-PHASE 0 OhX
1-PHASE X X
X = DON'T CARE
Number of Operating
Droop (R1+R5) and compen
IMON OC Trip = 1.12V
SI = Un-couppled InductorCI = Couppled Inductor
R3P DNPR3P DNP
CT2120pCT2120p
R1P DNPR1P DNP
TP15
IMON
TP15
IMON
R880R880
R91DNP
R91DNP
C51n
C51n
C212pF C212pF
CT4120pCT4120p
TP7VR_RDYTP7VR_RDY
C15
DNP
C15
DNP
R79.31kR79.31k
TP29PSI#
TP29PSI#
R2 12.1kR2 12.1k
R27DNSR27
DNSRN26.8kRN26.8k
C14
33nF
C14
33nF
RT2
221
RT2
221
R1 1kR1 1k
C3390pF C3390pF
U1 ISL6334U1 ISL6334
FB14
VDIFF15
VSEN17 RGND16
EN_VTT 33
VR_RDY36
VID61VID52VID43VID34VID25VID16VID07PSI#8
VR_FAN 37
VR_HOT 38
TM 39
TCOMP 18
OFS9
FS34
EN_PWR 32
ISEN3+ 29ISEN3- 30PWM3 31
ISEN1+ 28ISEN1- 27PWM1 26
ISEN2+ 22ISEN2- 21PWM2 20
ISEN4+ 23ISEN4- 24PWM4 25
SS35
VCC19
IMON10
DAC11
REF12
COMP/FB13
GN
D41
VID740
R11
1k
R11
1k
RT4221RT4221
R3460 R3460
RFS2
DNP
RFS2
DNP
R3441.30k R3441.30k
R2P DNPR2P DNP
CVC0.1u
CVC0.1u
TP6VR_HOT
TP6VR_HOT
Q242N7002Q242N7002
R6100kR6100k
CWDNP CWDNP
R102k
R102k
RMON
10.2k
RMON
10.2k
Csen
DNP
Csen
DNP
CW1DNP CW1DNP
R2449.9k
R2449.9k
TP5VR_FANTP5VR_FAN
RMOFS
901k
RMOFS
901k R2820kR2820k
R17
49.9k
R17
49.9k
RT1
221
RT1
221
CT3120pCT3120p
R5237
R5237
C660.1uC660.1u
RFS1
62k
RFS1
62k
CT1120pCT1120p
R82.2R82.2
RW4
0
RW4
0
RSS1
100k
RSS1
100k
RSS2DNP RSS2DNP
RW3
0
RW3
0
R9DNP
R9DNP
ROFS
26.1k
ROFS
26.1k
R90
0
R90
0
RW2
0
RW2
0
R345DNP R345DNP
RT3
221
RT3
221
C1 150pFC1 150pF
R3249
R3249
REDGREEN
CR2VR_RDY REDGREEN
CR2VR_RDY
4Ju
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010
TB486.0
1
1
D
C
B
A
VCORE
Rail5
Rail4
Rail4 Rail4
TitleSize Rev
Date: Sheet of
CISL6334 Burnside - 130W Rev C BoardB
2 3Wednesday, December 05, 2007
65 Readington Road
Intersil Corporation
Somerville, NJ 08876
TitleSize Rev
Date: Sheet of
CISL6334 Burnside - 130W Rev C BoardB
2 3Wednesday, December 05, 2007
65 Readington Road
Intersil Corporation
Somerville, NJ 08876
TitleSize Rev
Date: Sheet of
CISL6334 Burnside - 130W Rev C BoardB
2 3Wednesday, December 05, 2007
65 Readington Road
Intersil Corporation
Somerville, NJ 08876
hese hoods on differentns for scope probe ground
CO4422uCO4422u
CO32330uCO32330u
CO622uCO622u
CO43DNPCO43DNP
CO2322uCO2322u
1212
CO522uCO522u
TP100GNDTP100GND
CO1722uCO1722u
CO922uCO922u
CO38330uCO38330u
CO2522uCO2522u
CO37330uCO37330u
CO1322uCO1322u
CO1522uCO1522u
CO722uCO722u
TP50GNDTP50GND
CO34DNP
C330MW
CO34DNP
C330MW
CO46DNPCO46DNP
CO27DNPCO27DNP
CO2222uCO2222u
CO1422uCO1422u
CO822uCO822u
CO42DNPCO42DNP
J1V_COREJ1V_CORE1
CO31330uCO31330u
CO1622uCO1622u
CO41DNPCO41DNP CO45
DNPCO45DNP
J2GNDJ2GND
1
CO2422uCO2422u
CO1822uCO1822u
CO33330uCO33330u
CO422uCO422u
4040
CO47330uCO47330u
2121 CO2622uCO2622u
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FIGURE 9. ISL6334 BURNSIDE - 130W REV C BOARD, POWER STAGE
ISL6334EVAL1Z Schematics (Continued)
5
5
4
4
3
3
2
2
D
C
B
A
PHASE1
PHASE2
PHASE4
LG1
LG3PHASE3
LG2
LG4
UG2
UG1
UG3
UG4
VCC12
VCC12
VCC12
VCC12
VCC5
VCC12
ISEN1-
PWM1
PWM2
ISEN2-
PWM4
ISEN4-
ISEN3-
PWM3 LG3
LG2
LG1
LG4
UG2
UG3
UG4
UG1
PHASE3
PHASE4
PHASE2
PHASE1
Rail1
Rail2
Rail3
Power Stage
Intersil Confidential
Follow Intel Burside ATX Layout Guideline for Power Stage and LGA1366 Socket as
well as Input Bus Line (1080 pre-preg stackup, 6 layers)
CI: Phase1 (Thermistor) + Phase3 ; Phase2 + Phase4
Dual footprint for SI and CI - Expose Output Inductor Copper
Dual footprint - LFPAK/DPAK for High-side (T/B) and Low-Side (B/T)
Place tpositio
Need new footprint and use
bigger hole for T-core; Expose
output copper for Coupled
Inductors
Default - 12VUG, LDO=LG. Hardware Options: 12VUG5VLG; LDO=UGLG; 5V DRIVER
L1 160nHL1 160nH
RPS2 0RPS2 0
C764.7uC764.7u
RV5
DNP
RV5
DNP
CO20DNPCO20DNP
C27680uFC27680uF
QLT41QLT411
23
RPH3 0RPH3 0
RGV2DNPRGV2DNP
RGV1DNPRGV1DNP
RDU40
RDU40
CO36330uCO36330u
CO10DNPCO10DNP
CO19DNPCO19DNP
C244.7uC244.7u
C28680uFC28680uF
CC4 1uCC4 1u
QLT21QLT211
23
R2V12 10R2V12 10
CL21u
CL21u
CL11u
CL11u
RPS3 0RPS3 0
CO22uCO22u
CB10.1u CB10.1u
CL31u
CL31u
C674.7uC674.7u
RGV3DNPRGV3DNP
C784.7uC784.7u
L2160nH L2160nH
UD1 ISL6622CR/12CRUD1 ISL6622CR/12CR
UGATE 1
LGATE 6
PHASE 10LVCC/VCC7
VCC/PVCC9
PWM4
BOOT 2
GN
D/4
5
11EP
UVCC/NC8
GDV/NC3
L3 160nHL3 160nHQLT31QLT31
1
23
CB30.1u CB30.1u
RDL1DNP
RDL1DNP
QUB2QUB21
23
C32DNPC32DNP
RDU10
RDU10
RPS1 0RPS1 0
TP10GNDTP10GND
CO1122uCO1122u
RPH2 0RPH2 0
C444.7uC444.7u
R462.2R462.2
C234.7uC234.7u
RDU20
RDU20
C464.7uC464.7u
CO28DNPCO28DNP
2SEP2SEP
CO29DNPCO29DNP
CC2 1uCC2 1u
C684.7uC684.7u
C26DNPC26DNP
UD4 ISL6622CR/12CRUD4 ISL6622CR/12CR
UGATE 1
LGATE 6
PHASE 10LVCC/VCC7
VCC/PVCC9
PWM4
BOOT 2
GN
D5
11EP
UVCC/NC8
GDV/NC3
QLT12QLT121
23
QUB3QUB31
23
C75DNPC75DNP
C224.7uC224.7u
R1V12 10R1V12 10QUB1QUB1
1
23
RDL40RDL40
C30DNPC30DNP
RDL20RDL20
QLT11QLT111
23
CC1 1uCC1 1u
RPH4 0RPH4 0
CO3922uCO3922u
CO35330uCO35330u
RPS4 0RPS4 0
QUB4QUB41
23
CB40.1u CB40.1u
C704.7uC704.7u
L4 160nHL4 160nH
C644.7uC644.7u
CO322uCO322u
RGV4DNPRGV4DNP
R4V12 10R4V12 10
R732.2R732.2
CB20.1u CB20.1u
C31DNPC31DNP
RDU30
RDU30
UD3 ISL6622CR/12CRUD3 ISL6622CR/12CR
UGATE 1
LGATE 6
PHASE 10LVCC/VCC7
VCC/PVCC9
PWM4
BOOT 2
GN
D/4
5
11EP
UVCC/NC8
GDV/NC3
CL41u
CL41u
C33DNPC33DNP
UD2 ISL6622CR/12CRUD2 ISL6622CR/12CR
UGATE 1
LGATE 6
PHASE 10LVCC/VCC7
VCC/PVCC9
PWM4
BOOT 2
GN
D/4
5
11EP
UVCC/NC8
GDV/NC3
CC3 1uCC3 1u
QLT42QLT421
23
QLT32QLT321
23
RPH1 0RPH1 0
R3V12 10R3V12 10
CO22uCO22u
R472.2R472.2
C794.7uC794.7u
CO22uCO22u
CO222uCO222u
CO122uCO122u
RDL30RDL3
0
QLT22QLT221
23
R712.2R712.2
CO30330uCO30330u
5Ju
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010
TB486.0
1
1
D
C
B
A
VCC12
VID0
VID1
VID3
VID2
VID4
VID5
VID7
VID6
TitleSize Rev
Date: Sheet of
CISL6334 Burnside - 130W Rev C BoardB
3 3Tuesday, January 08, 2008
65 Readington Road
Intersil Corporation
Somerville, NJ 08876
TitleSize Rev
Date: Sheet of
CISL6334 Burnside - 130W Rev C BoardB
3 3Tuesday, January 08, 2008
65 Readington Road
Intersil Corporation
Somerville, NJ 08876
TitleSize Rev
Date: Sheet of
CISL6334 Burnside - 130W Rev C BoardB
3 3Tuesday, January 08, 2008
65 Readington Road
Intersil Corporation
Somerville, NJ 08876
se Resistor Value toe LL efficiency.
TP24VID4TP24VID4
RD510kRD510k
TP27VID7TP27VID7
SW1SW1
1
6
TPVIN
Vin
TPVIN
Vin
TP21VID1TP21VID1
TP23VID3TP23VID3
RD710kRD710k
TPGND
Vin_GND
TPGND
Vin_GND
TP26VID6TP26VID6
RD610kRD610k
TP22VID2TP22VID2
TP25VID5TP25VID5
D30kD30k
J42x2 Power ConnectorJ42x2 Power Connector
GND1
GND02 12V 4
+12V 3
55
TP20VID0TP20VID0
RD410kRD410k
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FIGURE 10. ISL6334 BURNSIDE - 130W REV C BOARD
ISL6334EVAL1Z Schematics (Continued)
5
5
4
4
3
3
2
2
D
C
B
A
UG1PHASE1
PHASE2
UG3
UG4
VCC_SENSE_DIE
LG1
PHASE1
LG2
PHASE2
LG4
PHASE4
LG3
PHASE3
VTTPWRGOOD
UG2
VSS_SENSE_DIE
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC12
VCC12
VCC12
VCC12
VCC5
EN_VTT
VTT_VID0VTT_VID1VTT_VID2VTT_VID3
VTT_VID4VTT_VID5VTT_VID6VTT_VID7
VTT_VID1
VTT_VID2
VTT_VID3
VTT_VID4
VTT_VID5
VTT_VID6
VTT_VID7
VTT_VID0
ISENSE
ISENSE_DN
VR_RDYPSI#
VSEN
RGND
EN_VTT
VCORE
LG3
LG4LG2
UG2
LG1
UG3
UG4
UG1PHASE1
PHASE1
PHASE2
PHASE3
PHASE4
PHASE3
PHASE4PHASE2
LG1 LG2
LG3 LG4
VSS_SENSE_DIE
Intersil Confidential
VID generator, LGA1366 socket and input connectors
VID Code
DEMO
Increaimprov
VTT
Place These FETs on Top Sidefor Intel Burnside CRB Design
Place These FETs on Bottom Side forIntel Burnside CRB Design (DependingUpon the Layout, we might drop this)
Add via on AR18 andAR17 for test points
Use Intersil/VTT Interposer
for DCLL Measurement
AR17
AR18
Per Intel Request,but not needed
VTT DEMO
NEED BNC FOOTPRINT
0
BNC1
ONLY 1 "ON"code allowed
RD110kRD110k
R61DNPR61DNP
RDIEN0 RDIEN0
RD010kRD010kU6
ISL43240U6ISL43240
EN11
NO12
NC14
NO29
NC314 NC27
NC417
NO312NO419
EN210EN311EN420
COM1 3
COM2 8
COM3 13
COM4 18
VCC 16
VEE 5GND 6
nc 15
QUT1QUT1
45
321
C12DNSC12DNS
R7810kR7810k
R64DNPR64DNP
R7410kR7410k
RLCN 100RLCN 100
C40DNPC40DNP
C9910uC9910u
R100DNS R100DNS
C1080.1uC1080.1u
QLB42QLB42
45
321
R99DNS R99DNS
QUT4QUT44
5321
QUT2QUT2
45
321
QLB22QLB22
45
321
C39DNPC39DNP
C37DNPC37DNP
2
3
4
R66DNPR66DNP
TP28ENABLETP28ENABLE
J21ATX 24-Pin ConnectorJ21ATX 24-Pin Connector
+3.3V1+3.3VA2
+12V1B11
+5V4+5VA6 GND5 19
NC 20+5VSB9
-12V 14
GND 3GND0 5GND1 7
+3.3VC13 GND2 15
PS_ON# 16
GND3 17
+3.3VB12
GND4 18
PWR_OK 8
+12V1A10
2525
+5VB21+5VC22+5VD23
GND6 24R101
0
R101
0
JP9JP9
R62DNPR62DNP
C41DNPC41DNP
C35DNPC35DNP
TP9
RGND
TP9
RGND
QLB11QLB11
45
321
C10610nC10610n
QLB21QLB21
45
321
C34DNPC34DNP
J0J0
R60DNPR60DNP
TP8
VSEN
TP8
VSEN
QLB41QLB41
45
321
J5J5
R59DNPR59DNP
U7ISL43240U7ISL43240
EN11
NO12
NC14
NO29
NC314 NC27
NC417
NO312NO419
EN210EN311EN420
COM1 3
COM2 8
COM3 13
COM4 18
VCC 16
VEE 5GND 6
nc 15
R79100kR79100k
RD210kRD210k
C1070.1uC1070.1u
QLB32QLB32
45
321
SW2SW21
2
3
4
6
QUT3QUT3
45
321
SW3SW DIP-8SW3SW DIP-8
SW5SW DIP-4SW5SW DIP-4
QLB12QLB12
45
321
R63DNPR63DNP
TP68
PSI
TP68
PSI
R1R1
C38DNPC38DNP
C36DNPC36DNP
QLB31QLB31
45
321
RDIEP0 RDIEP0
R65DNPR65DNP
RLCP 100RLCP 100
U100
LGA1366_SOCKET
VCC
VSS
AL10
AL9
AN9
AM10
AN10
AP9
AP8
AN8
AR9
AR8
AK8
AK7
AR7AP7
AB35
6Ju
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010
TB486.0
1
1
D
C
B
A
VSS
VSS
VSS
VSS
TitleSize Rev
Date: Sheet of
ALGA1366 SOCKET PIN OUTCustom
5 5Tuesday, January 08, 2008
Intersil Corporation
TitleSize Rev
Date: Sheet of
ALGA1366 SOCKET PIN OUTCustom
5 5Tuesday, January 08, 2008
Intersil Corporation
TitleSize Rev
Date: Sheet of
ALGA1366 SOCKET PIN OUTCustom
5 5Tuesday, January 08, 2008
Intersil Corporation
VS
S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VS
S
VS
S
VS
S
1234567891011
3334353637383940414243
234567891011
1234567891011
33343536373839404142431
3940414243
U100-7
1366LGA_6
U100-7
1366LGA_6
B2B3B4B5B6B7B8B9
B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32B33B34B35B36B37B38B39B40B41B42
A4A5A6A7A8A9A10
A14A15A16A17A18A19A20
A24A25A26A27A28A29A30A31
A35A36A37A38A39A40A41
MN
1
MN
2
MN
3
MN
4
MN
5
MN
6
MN
7
MN
8
U100-61366LGA_6
U100-61366LGA_6
E1E2E3E4E5E6E7E8E9
E10E11E12E13E14E15E16E17E18E19E20E21E22E23E24E25E26E27E28E29E30E31E32E33E34E35E36E37E38E39E40E41E42E43
D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16D17D18D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21C22C23C24C25C26C27C28C29C30C31C32C33C34C35C36C37C38C39C40C41C42C43
Tech
nica
l Brie
f 48
6
FIGURE 11. LGA1366 SOCKET PINOUT
ISL6334EVAL1Z Schematics (Continued)
5
5
4
4
3
3
2
2
D
C
B
A
VSSAB
35
AP7
AK7
VCC
VCC
AK8
AR7
AN10AN9AN8
AP9AP8
AL10
AL9
AM10
VSS
AR8AR9
VCC
VCC
VSS
VSS
VSS
VC
C
VS
S
VS
S
VCC
VCC
VS
S
VSS
VC
C
VS
S
VSS
VS
S
VSS
VC
C
VC
C
VS
S
VCC
VS
S
VSS
VS
S_S
EN
SE
VSS
VID4
VSS
VCC
VS
S
VSS
VCC
VSS
VCC
VS
S
VS
S
VC
C
VSS
VCC
VSS
VCC
VCC
VSS
VS
S
VCC
VCC
VC
C
VSS
VSS
VID5
VCC
VCC
VSS
VC
C_N
OR
TH
VSS
VCC
VSS
VS
S
VC
C
VC
C
VS
S
VCC
VSS
VCC
VS
S
VCC
VSS
VS
S
VS
S
VCC
VSS
VCC
VC
C_S
EN
SE
VID6
VS
S
VSS
VC
C
VCC
ISENSE_DN
VCC
VCC
VSS
VSS
VS
S
VC
C
VS
S
VCC
VS
S
VCC
VSS
VC
C
VS
S
VS
S
VSS
VCC
VCC
VS
S
VC
C
VCC
VS
S
VSS
VSS
VSS
VID7
VC
C
VC
C
VCC
VS
S
VSS
VSS
VCC
VS
S
VS
S
VS
S
VCC
VSS
VCC
VS
S
VSS
VS
S
VC
CV
SS
VCC
VCC
VS
S
VSS
VSS
VC
C
VSS
VS
S
VID2
VCC
VSS
VCC
VC
C
VSS
VSS
VCC
VSS
VS
S
VCC VC
C
VS
S
VCC
VSS
VS
S
VSS
VC
C
VC
C
VCC
VS
S
VS
S
VC
C
VS
S
VCC
VSS
VSS
VCC
VS
S
VCC
VSS
VSSVCC
VSS
VCC
VSS
VS
S
VS
S
VCC
VC
C
VSS
VCC
VSS
VC
C
VS
S
VSS
VSS
VS
S
VCC
VCC
VS
S
VC
C
VS
S
VCC
VR
_RE
AD
Y
VSS
VSS
VSS
VC
C
VSS
VCC
VSS
VSS
VSS
VC
C VS
S
VC
C
VCC
VC
C
VS
S
VSS
VSS
VCC
VCC
VCC
VSS
VS
S
VS
S
VCC
VCC
VSS
VSS
VCC
VC
C
VSS
VSS
VCC
VSS
VC
C
VSS
VS
S
VCC
VSS
VCC
VS
S
VC
C
VS
S
VSS
VCC
VSS
VSS
VC
C
VS
S
VCC
VSS
VSS
VSS
VC
C
VC
C
VS
S
VSS
VSS
VCC
VSS
VCC
VSS
VS
S
VS
SV
SS
VCC
VS
S
VCC
VSS
VCC
VS
S
VSS
VCC
VC
C
VCC
VS
S
VC
C
VSS
VSS
VCC
VCC
VSS
VC
C
VS
SVSS
VCC
VC
C
VS
S
VSS
VS
S
VC
C
VS
S
VCC
VS
S
VSS
VS
S
VSS
VC
C
VC
C
VS
S
VTT
PW
RG
OO
D
VCC
VS
S
VS
S
VCC
VSS
VSS
VS
S
VCC
VSS
PSI #
VCC
VS
S
VCC
VSS
VSS
VS
S
VS
S
VC
C
VCC
VS
S
VS
S
VC
C
VSS
VCC
VSS
VCC
VS
S
VC
C
VS
S
VCC
VS
S
VC
C
VSS
VSS
VC
C
VS
S
VS
S
VCC
VSS
VSS
VS
S
VC
C
VS
S
VC
C
VS
S
VCC
VSS
VCC
VS
S
VSS
VCC
VCC
VSS
VCC
VS
S
VCC
VS
S
VSS
VSS
VC
C
VCC
VS
S
VC
C
VSS
VCC
VS
S
VSS
VC
C
VS
S
VCC
VSS
VC
C
VC
C
VSS
VSS
VCC
VSS
VS
S
VS
S
VSS
VC
C
VSS
VC
C
VS
S
VSS
VSS
VCC
VCC
VC
C
VS
S
VSS
VCC
VSS
VS
S
VCC
VSS
VSS
VSS
VSS
VCC
VC
C
VC
C
VS
S
VS
S
VSS
VSS
VCC
VSS
VC
C
VCC
VS
S
VC
C
VSS
VC
C
VSS
VCC
VID
1
VSS
VSS
VCC
VSS
VSS
VCC VSS
VS
S
VCC
VS
S
VC
C
VSS
VCC
VSS
VCC
VSS
VS
S
VCC
VSS
VCC
VS
S
VC
C
VC
C
VSS
VSS
VS
S
VC
C
VCC
VSS
VCC
VSS
VSS
VC
C
VCC
VS
S
VC
C
VS
S_N
OR
TH
VC
C
VSS
VSS
VSS
VCC
VS
S
VSS
VSS
VS
S
PR
OC
HO
T#
VSS
VCC
VS
S
VCC
VSS
VSS
VCC
VC
C
VCC
VSS
VSS
VCC
VCC
VSS
VS
S
VS
S
VSS
VCC
VSS
VC
C
VCC
VSS
VS
S
VC
CVSS
VCC
VS
S
VCC
VC
C
VSS
VSS
VSS
VID
0
VC
C
VSS
VC
C
VS
S
VCC
VSS
VSS
VS
S
VCC
VS
S
VCC
VSS
VSS
VCC
VS
S
VSS
VCC
VS
S
VCC
VC
C
VCC
ISENSE
VCC
VSS
VSS
VID
3
VSS
VCC
VCC
VSS
VSS
VS
S
VS
S
AR17
AR18
VSS
U100-21366LGA_6
U100-21366LGA_6
AV1AV2AV3AV4AV5AV6AV7AV8AV9
AV10AV11AV12AV13AV14AV15AV16AV17AV18AV19AV20AV21AV22AV23AV24AV25AV26AV27AV28AV29AV30AV31AV32AV33AV34AV35AV36AV37AV38AV39AV40AV41AV42AV43
AU1AU2AU3AU4AU5AU6AU7AU8AU9
AU10AU11AU12AU13AU14AU15AU16AU17AU18AU19AU20AU21AU22AU23AU24AU25AU26AU27AU28AU29AU30AU31AU32AU33AU34AU35AU36AU37AU38AU39AU40AU41AU42AU43
AT1
AT2
AT3
AT4
AT5
AT6
AT7
AT8
AT9
AT1
0A
T11
AT1
2A
T13
AT1
4A
T15
AT1
6A
T17
AT1
8A
T19
AT2
0A
T21
AT2
2A
T23
AT2
4A
T25
AT2
6A
T27
AT2
8A
T29
AT3
0A
T31
AT3
2A
T33
AT3
4A
T35
AT3
6A
T37
AT3
8A
T39
AT4
0A
T41
AT4
2A
T43
AR
1A
R2
AR
3A
R4
AR
5A
R6
AR
7A
R8
AR
9A
R10
AR
11A
R12
AR
13A
R14
AR
15A
R16
AR
17A
R18
AR
19A
R20
AR
21A
R22
AR
23A
R24
AR
25A
R26
AR
27A
R28
AR
29A
R30
AR
31A
R32
AR
33A
R34
AR
35A
R36
AR
37A
R38
AR
39A
R40
AR
41A
R42
AR
43
AP1AP2AP3AP4AP5AP6AP7AP8AP9AP10AP11AP12AP13AP14AP15AP16AP17AP18AP19AP20AP21AP22AP23AP24AP25AP26AP27AP28AP29AP30AP31AP32AP33AP34AP35AP36AP37AP38AP39AP40AP41AP42AP43
AN1AN2AN3AN4AN5AN6AN7AN8AN9AN10AN11AN12AN13AN14AN15AN16AN17AN18AN19AN20AN21AN22AN23AN24AN25AN26AN27AN28AN29AN30AN31AN32AN33AN34AN35AN36AN37AN38AN39AN40AN41AN42AN43
AM
1A
M2
AM
3A
M4
AM
5A
M6
AM
7A
M8
AM
9A
M10
AM
11A
M12
AM
13A
M14
AM
15A
M16
AM
17A
M18
AM
19A
M20
AM
21A
M22
AM
23A
M24
AM
25A
M26
AM
27A
M28
AM
29A
M30
AM
31A
M32
AM
33A
M34
AM
35A
M36
AM
37A
M38
AM
39A
M40
AM
41A
M42
AM
43
AL1
AL2
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AL1
0A
L11
AL1
2A
L13
AL1
4A
L15
AL1
6A
L17
AL1
8A
L19
AL2
0A
L21
AL2
2A
L23
AL2
4A
L25
AL2
6A
L27
AL2
8A
L29
AL3
0A
L31
AL3
2A
L33
AL3
4A
L35
AL3
6A
L37
AL3
8A
L39
AL4
0A
L41
AL4
2A
L43
U100-31366LGA_6U100-31366LGA_6
AK1AK2AK3AK4AK5AK6AK7AK8AK9
AK10AK11AK12AK13AK14AK15AK16AK17AK18AK19AK20AK21AK22AK23AK24AK25AK26AK27AK28AK29AK30AK31AK32AK33AK34AK35AK36AK37AK38AK39AK40AK41AK42AK43
AJ1AJ2AJ3AJ4AJ5AJ6AJ7AJ8AJ9
AJ10AJ11AJ33AJ34AJ35AJ36AJ37AJ38AJ39AJ40AJ41AJ42AJ43
AH
1A
H2
AH
3A
H4
AH
5A
H6
AH
7A
H8
AH
9A
H10
AH
11A
H33
AH
34A
H35
AH
36A
H37
AH
38A
H39
AH
40A
H41
AH
42A
H43
AG
1A
G2
AG
3A
G4
AG
5A
G6
AG
7A
G8
AG
9A
G10
AG
11A
G33
AG
34A
G35
AG
36A
G37
AG
38A
G39
AG
40A
G41
AG
42A
G43
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF1
0A
F11
AF3
3A
F34
AF3
5A
F36
AF3
7A
F38
AF3
9A
F40
AF4
1A
F42
AF4
3
AEAEAEAEAEAEAEAEAEAEAE
AEAEAEAEAEAEAEAEAEAEAE
ADADADADADADADADADAD
ACACACACACACACACACACAC
ADADADADADADADADADADADAD
AC
33A
C34
AC
35A
C36
AC
37A
C38
ACACACACAC
AB
3A
B4
AB
5A
B6
AB
7A
B8
AB
9A
B10
AB
11
AB
33A
B34
AB
35A
B36
AB
37A
B38
AB
39A
B40
AB
41A
B42
AB
43
AA
3A
A4
AA
5A
A6
AA
7A
A8
AA
9A
A10
AA
11
AA
33A
A34
AA
35A
A36
AA
37A
A38
AA
39A
A40
AA
41
U100-41366LGA_6U100-41366LGA_6
Y1Y2Y3Y4Y5Y6Y7Y8Y9
Y10Y11Y33Y34Y35Y36Y37Y38Y39Y40Y41
W1W2W3W4W5W6W7W8W9
W10W11W33W34W35W36W37W38W39W40W41W42W43
V1V2V3V4V5V6V7V8V9
V10V11V33V34V35V36V37V38V39V40V41V42V43
U1U2U3U4U5U6U7U8U9
U10U11
U33
U34
U35
U36
U37
U38
U39
U40
U41
U42
U43 T1 T2 T3 T4 T5 T6 T7 T8 T9 T1
0T1
1T3
3T3
4T3
5T3
6T3
7T3
8T3
9T4
0T4
1T4
2T4
3
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43 P
1P
2P
3P
4P
5P
6P
7P
8P
9P
10P
11
P33P34P35P36P37P38P39P40P41P42P43
N1N2N3N4N5N6N7N8N9N10N11
N33N34N35N36N37N38N39N40N41N42N43
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24M25M26M27M28M29M30M31M32M33M34M35M36M37M38M39M40M41M42M43
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
L31
L32
L33
L34
L35
L36
L37
L38
L39
L40
L41
L42
L43
U100-5
1366LGA_6
U100-5
1366LGA_6
J1J2J3J4J5J6J7J8J9
J10J11J12J13J14J15J16J17J18J19J20J21J22J23J24J25J26J27J28J29
J30
J31
J32
J33
J34
J35
J36
J37
J38
J39
J40
J41
J42
J43
K1K2K3K4K5K6K7K8K9
K10K11K12K13K14K15K16K17K18K19K20K21K22K23K24K25K26K27K28K29K30K31K32K33K34K35K36K37K38K39K40K41K42K43
H1H2H3H4H5H6H7H8H9H10H11H12H13H14H15H16H17H18H19H20H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
H38
H39
H40
H41
H42
H43
G1G2G3G4G5G6G7G8G9G10G11G12G13G14G15G16G17G18G19G20G21G22G23G24G25G26G27G28G29G30G31G32G33G34G35G36G37G38G39G40G41G42G43
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
F38F39F40F41F42F43
U100-1
1366LGA_6
U100-1
1366LGA_6
BA3BA4BA5BA6BA7BA8BA9
BA10BA11BA12BA13BA14BA15BA16BA17BA18BA19BA20
BA24BA25BA26BA27BA28BA29BA30
BA35BA36BA37BA38BA39BA40
AY2AY3AY4AY5AY6AY7AY8AY9
AY10AY11AY12AY13AY14AY15AY16AY17AY18
AY
19A
Y20
AY
21
AY22AY23AY24AY25AY26AY27AY28AY29AY30AY31AY32AY33AY34AY35AY36AY37AY38AY39AY40AY41AY42
AW1AW2AW3AW4AW5AW6AW7AW8AW9AW10AW11AW12AW13AW14AW15AW16AW17AW18AW19AW20
AW22AW23AW24AW25AW26AW27AW28AW29AW30AW31AW32AW33AW34AW35AW36
AW
37A
W38
AW
39A
W40
AW
41A
W42
AW21
Technical Brief 486
ISL6334EVAL1Z Board Layout
FIGURE 12. TOP SILKSCREEN
7 July 7, 2010TB486.0
Technical Brief 486
FIGURE 13. TOP COMPONENT SIDE
ISL6334EVAL1Z Board Layout (Continued)
8 July 7, 2010TB486.0
Technical Brief 486
FIGURE 14. INTERNAL PLANE L2
ISL6334EVAL1Z Board Layout (Continued)
9 July 7, 2010TB486.0
Technical Brief 486
FIGURE 15. INTERNAL ETCH L3
ISL6334EVAL1Z Board Layout (Continued)
10 July 7, 2010TB486.0
Technical Brief 486
FIGURE 16. INTERNAL ETCH L4
ISL6334EVAL1Z Board Layout (Continued)
11 July 7, 2010TB486.0
Technical Brief 486
FIGURE 17. INTERNAL PLANE L5
ISL6334EVAL1Z Board Layout (Continued)
12 July 7, 2010TB486.0
Technical Brief 486
FIGURE 18. SOLDER SIDE BOTTOM
ISL6334EVAL1Z Board Layout (Continued)
13 July 7, 2010TB486.0
Technical Brief 486
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, thereader is cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
FIGURE 19. SILKSCREEN BOTTOM
ISL6334EVAL1Z Board Layout (Continued)
14 July 7, 2010TB486.0