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1. General description

The TDA8566 is an integrated class-B output amplier which is available in severalpackages. TDA8566TH is contained in a 20-lead small outline plastic package. TheTDA8566TH1 is a 24-lead small outline plastic package which is pin compatible with theI2C-bus controlled amplier TDA1566TH for one board layout. TDA8566Q is a 17-pinDIL-bent-SIL package.

The device contains 2 ampliers in a Bridge-Tied Load (BTL) conguration. The output

power is 2 25 W in a 4 load or 2 40 W in a 2 load. It has a differential input stageand 2 diagnostic outputs. The device is primarily developed for car radio applications.

2. Features

Differential inputsVery high Common Mode Rejection Ratio (CMRR)High common mode input signal handlingRequires very few external componentsHigh output power4 and 2 load driving capabilityLow offset voltage at outputFixed gainDiagnostic facility (distortion, short-circuit and temperature pre-warning)Good ripple rejectionMode select switch (operating, mute and standby)Load dump protectionShort-circuit proof to ground, to V P and across the loadLow power dissipation in any short-circuit conditionThermally protectedReverse polarity safeProtected against electrostatic dischargeNo switch-on/switch-off plopsLow thermal resistanceTDA8566TH1 is pin compatible with TDA1566TH

TDA85662 40 W/2 stereo BTL car radio power amplier withdifferential inputs and diagnostic outputsRev. 06 15 October 2007 Product data sheet

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TDA8566_6 NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 15 October 2007 2 of 21

NXP Semiconductors TDA85662 40 W/2 stereo BTL car radio power amplier

3. Quick reference data

[1] The circuit is DC adjusted at V P = 6 V to 18 V and AC operating at V P = 8.5 V to 18 V.

[2] Vripple = Vripple(max) = 2 V (p-p); R s = 0 .

[3] Common mode rejection ratio measured at the output (over R L) with both inputs tied together;Vcommon 3.5 V (RMS); f i = 100 Hz to 10 kHz; R s = 0 .

[4] Noise measured in a bandwidth of 20 Hz to 20 kHz.

4. Ordering information

Table 1. Quick reference dataV P = 14.4 V; T amb = 25 C; f i = 1 kHz; measured in test circuit of Figure 9 ; unless otherwise specied.

Symbol Parameter Conditions Min Typ Max Unit

VP supply voltage [1] 6 14.4 18 V

IORM repetitive peak outputcurrent

- - 7.5 A

Iq quiescent current R L = - 115 180 mA

Istb standby current - 0.1 10 A

Zi input impedance differential 100 120 150 k

Po

output power RL

= 4 ; THD = 10 % 21 25 - W

RL = 2 ; THD = 10 % 33 40 - W

SVRR supply voltage ripplerejection

operating [2] 50 60 - dB

cs channel separation P o = 25 W; R s = 1 0 k 45 50 - dB

CMRR common mode rejectionratio

Rs = 0 [3] 60 75 - dB

Gv closed loop voltage gain 25 26 27 dB

Vn(o) noise output voltage operating; R s = 0 [4] - 85 120 V

Table 2. Ordering information

Type number Package

Name Description Version

TDA8566TH HSOP20 plastic, heatsink small outline package; 20 leads; low stand-off height SOT418-3

TDA8566TH1 HSOP24 plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3TDA8566Q DBS17P plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm) SOT243-1

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5. Block diagram

(1) Pin HEATTAB is available in TDA8566TH1 only.

Fig 1. Block diagram

CM

VA

(9 )

2.3 k

2.3k

muteswitch

CM

VA

VA

1

standbyreference

voltage

standbyswitch

mutereferencevoltage

Vref muteswitch

CLIP

(9 )

2.3 k

2.3k

60k

60k

60k

60k

muteswitch

CM

VA

(9 )

2.3 k

2.3k

muteswitch

CM

VA

TDA8566

VP2VP1

PGND2 PGND1

OUT2

OUT2+

OUT1

OUT1+IN1

IN1+

IN2

IN2+

SGND

HEATTAB (1)

n.c.

DIAG

MODE

CLIP

mgu358

(9 )

2.3 k

2.3k

muteswitch

DIAG

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6. Pinning information

6.1 Pinning

Fig 2. Pin conguration TDA8566TH Fig 3. Pin conguration TDA8566TH1

Fig 4. Pin conguration TDA8566Q

TDA8566TH

MODE DIAG

VP2 IN2+

OUT2 IN2

PGND2 n.c.

OUT2+ n.c.

OUT1 n.c.

PGND1 n.c.OUT1+ IN1+

VP1 IN1

CLIP SGND

001aag902

20

19

18

17

16

15

1413

12

11

9

10

78

5

6

3

4

1

2

TDA8566TH1

HEATTAB DIAG

VP2 IN2+

n.c. IN2

OUT2 n.c.

PGND2 n.c.

OUT2+ n.c.

OUT1 MODE

PGND1 n.c.

OUT1+ n.c.

n.c. IN1+

VP1 IN1

CLIP SGND

001aah015

24

23

22

21

20

19

18

17

16

15

14

13

11

12

9

10

7

8

5

6

3

4

1

2

TDA8566Q

IN1+

IN1

SGNDCLIP

VP1OUT1+

PGND1

OUT1

n.c.

OUT2+

PGND2

OUT2

VP2MODE

DIAGIN2+

IN2

001aah059

1

2

34

5

6

7

8

9

10

11

12

13

14

1516

17

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7.3 Short-circuit diagnostic (pin DIAG)When a short-circuit occurs at one or more outputs to ground or to the supply voltage, theoutput stages are switched off until the short-circuit is removed and the device is switchedon again (with a delay of approximately 20 ms after the removal of the short-circuit).During this short-circuit condition, pin DIAG is continuously LOW.

When a short-circuit occurs across the load of one or both channels, the output stages areswitched off for approximately 20 ms. After that time the load condition is checked duringapproximately 50 s to see whether the short-circuit is still present. Due to this duty cycleof 50 s/20 ms the average current consumption during the short-circuit condition is verylow (approximately 40 mA). During this condition, pin DIAG is LOW for 20 ms and HIGHfor 50 s; see Figure 6 . The power dissipation in any shor t-circuit condition is very low.

7.4 Temperature pre-warning (pin DIAG)When the virtual junction temperature (T vj) reaches 145 C, pin DIAG will becomecontinuously LOW.

7.5 Open-collector diagnostic outputsPins DIAG and CLIP are open-collector outputs, therefore more devices can be tiedtogether. Pins DIAG and CLIP can also be tied together. An external pull-up resistor isrequired.

Fig 5. Clip detection waveforms

0

VO(V)

VCLIP(V)

0

t (s)

mgu357

Fig 6. Short-circuit diagnostic timing diagram

mgu360

short-circuit over the load

20 ms

50 s

t (s)

t (s)

VDIAG(V)

currentin

outputstage

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7.6 Differential inputsThe input stage is a high-impedance fully differential balanced input stage that is alsocapable of operating in a single-ended mode with one of the inputs capacitively coupled toan audio ground. It should be noted that if a source resistance is added (input voltagedividers) the CMRR degrades to lower values.

8. Limiting values

9. Thermal characteristics

Table 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VP supply voltage operating - 18 V

non-operating - 30 Vload dump protection;during 50 ms; t r 2.5 ms

- 45 V

IOSM non-repetitive peak outputcurrent

- 10 A

IORM repetitive peak outputcurrent

- 7.5 A

Tstg storage temperature 55 +150 C

Tvj virtual junction temperature - 150 C

Tamb ambient temperature 40 +85 C

Vpsc short-circuit safe voltage - 18 V

Vrp reverse polarity voltage - 6.0 VP tot total power dissipation - 60 W

Table 6. Thermal characteristicsThermal characteristics in accordance with IEC 60747-1.

Symbol Parameter Conditions Typ Unit

R th(j-c) thermal resistance from junction to case see Figure 7 1.3 K/W

R th(j-a) thermal resistance from junction to ambient in free air 40 K/W

Fig 7. Equivalent thermal resistance network

001aaa155

2.2 K/W 2.2 K/W

0.2 K/W

case

output 1virtual junction

output 2

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10. Static characteristics

[1] The circuit is DC adjusted at V P = 6 V to 18 V and AC operating at V P = 8.5 V to 18 V.

[2] At VP = 18 V to 30 V the DC output voltage is 0.5V P .

Table 7. Static characteristicsV P = 14.4 V; T amb = 25 C; measured in test circuit of Figure 9 ; unless otherwise specied.


Supply

VP supply voltage [1] 6 14.4 18 V

Iq quiescent current R L = - 115 180 mA

Operating condition

VMODE mode select switchlevel

8.5 - V P V

IMODE mode select switchcurrent

VMODE = 14.4 V - 15 40 A

VO output voltage [2] - 7.0 - V

VOO output offset voltage - - 100 mV

Mute condition


3.3 - 6.4 V

VO output voltage [2] - 7.0 - V

VOO output offset voltage - - 60 mV

VOO output offset voltagedifference

with respect tooperating condition

- - 60 mV

Standby condition


0 - 2 V

Istb standby current - 0.1 10 A

Diagnostic

VDIAG diagnostic outputvoltage

during any faultcondition

- - 0.6 V

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11. Dynamic characteristics

Table 8. Dynamic characteristicsV P = 14.4 V; T amb = 25 C; R L = 2 ; f i = 1 kHz; measured in test circuit of Figure 9 ; unless otherwise specied.


P o output power THD = 0.5 % 25 30 - W

THD = 10 % 33 40 - W

THD = 30 % 45 55 - W

VP = 13.5 V; THD = 0.5 % - 25 - W

VP = 13.5 V; THD = 10 % - 35 - W

THD = 0.5 %; R L = 4 16 19 - W

THD = 10 %; R L = 4 21 25 - WTHD = 30 %; R L = 4 28 35 - W

VP = 13.5 V;THD = 0.5 %; R L = 4

- 14 - W

VP = 13.5 V;THD = 10 %;RL = 4

- 22 - W

THD total harmonicdistortion

P o = 1 W - 0.1 - %

VCLIP = 0.6 V [1] - 8 - %

P o = 1 W; R L = 4 - 0.05 - %

B power bandwidth THD = 0.5 %; P o = 1 dBwith respect to 25 W

- 20 to20000

- Hz

fro(l) low frequency rolloff

1 dB [2] - 25 - Hz

fro(h) high frequency rolloff

1 dB 20 - - kHz

Gv closed loop voltagegain

25 26 27 dB

SVRR supply voltageripple rejection

operating [3] 50 60 - dB

mute [3] 50 - - dB

standby [3] 80 - - dB

Zi input impedance differential 100 120 150 k

single-ended 50 60 75 k

|Zi| input impedancemismatch

- 2 - %

Vn(o) noise outputvoltage

operating; R s = 0 [4] - 85 120 V

operating; R s = 1 0 k [4] - 100 - V

mute; independent of R s [4] - 60 - V

cs channel separation P o = 25 W; R s = 10 k 45 50 - dB

|Gv| channel unbalance - - 1 dB

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[1] Dynamic distortion detector active; pin CLIP is LOW.

[2] Frequency response externally xed.

[3] Vripple = Vripple(max) = 2 V (p-p); R s = 0 .

[4] Noise measured in a bandwidth of 20 Hz to 20 kHz.

[5] Common mode rejection ratio measured at the output (over RL) with both inputs tied together;

Vcommon 3.5 V (RMS); f i = 100 Hz to 10 kHz; R s = 0 .

[6] Common mode rejection ratio measured at the output (over R L) with both inputs tied together;Vcommon 3.5 V (RMS); f i = 1 kHz; R s = 45 k . The mismatch of the input coupling capacitors is excluded.

12. Application information

12.1 Diagnostic outputSpecial care must be taken in the PCB layout to separate pin CLIP frompins IN1+, IN1 , IN2+ and IN2 to minimize the crosstalk between the CLIP output andthe inputs.

12.2 Mode select switchTo avoid switch-on plops, it is advisable to keep the amplier in the mute mode during 150 ms (charging of the input capacitors at pins IN1+, IN1 , IN2+ and IN2 ). The circuitin Figure 8 slowly ramps-up the voltage at the mode select switch pin when switching onand results in fast muting when switching off.

Vo(mute) output signalvoltage in mute

Vin = Vin(max) = 1 V (RMS) - - 2 mV

CMRR common moderejection ratio

Rs = 0 [5] 60 75 - dB

Rs = 4 5 k [6] 40 - - dB

Table 8. Dynamic characteristics continued V P = 14.4 V; T amb = 25 C; R L = 2 ; f i = 1 kHz; measured in test circuit of Figure 9 ; unless

otherwise specied.Symbol Parameter Conditions Min Typ Max Unit

Fig 8. Mode select switch circuit

100 k

mgd102

47 F

10 k S

100

modeselectswitch

+VP

+

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14. Package outline

Fig 10. Package outline SOT418-3 (HSOP20)

UNIT A4(1)

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE IEC JEDEC JEITA

mm +0.08

0.043.5 0.35

DIMENSIONS (mm are the original dimensions)

Notes1. Limits per individual lead.2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT418-3

0 5 10 mm

scale

HSOP20: plastic, heatsink small outline package; 20 leads; low stand-off height SOT418-3

Amax.

detail X

A2

3.53.2

D2

1.10.9

HE

14.513.9

Lp

1.10.8

Q

1.71.5

2.52.0

v

0.25

w

0.25

y Z

80

0.07

x

0.03

D1

13.012.6

E1

6.25.8

E2

2.92.5

b p c

0.320.23

e

1.27

D(2)

16.015.8

E (2)

11.110.9

0.530.40

A3

A4

A2(A3)

Lp

A

Q

D

y

x

HE

E

c

v M A

X

A

bpw MZ

D1D2

E2

E1

e

20 11

1 10

pin 1 index

02-02-1203-07-23

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Fig 11. Package outline SOT566-3 (HSOP24)

UNIT A4(1)


EUROPEANPROJECTION ISSUE DATE

03-02-1803-07-23

IEC JEDEC JEITA

mm +0.08

0.043.5 0.35


Notes1. Limits per individual lead.2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT566-3

0 5 10 mm

scale

HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3

Amax.

detail X

A2

3.53.2

D2

1.10.9

HE

14.513.9

Lp

1.10.8

Q

1.71.5

2.72.2

v

0.25

w

0.25

y Z

80

0.07

x

0.03

D1

13.012.6

E1

6.25.8

E2

2.92.5

b p c

0.320.23

e

1

D(2)

16.015.8

E (2)

11.110.9

0.530.40

A3

A4

A2(A3)

Lp

A

Q

D

y

x

HE

E

c

v M A

X

A

bpw MZ

D1D2

E2

E1

e

24 13

1 12

pin 1 index

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Fig 12. Package outline SOT243-1 (DBS17P)


EUROPEANPROJECTION ISSUE DATE IEC JEDEC JEITA


Note1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT243-1

0 5 10 mm

scale

D

L

E

A

c

A2

L3

Q

w Mb p

1

d

D

Z e

e

x h

1 17

j

E h

non-concave

99-12-1703-03-12

DBS17P: plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm) SOT243-1

view B: mounting base side

m 2e

v M

B

UNIT A e 1A2 b p c D (1) E (1) Z (1)d eDh L L 3 m

mm 17.015.5

4.64.4

0.750.60

0.480.38

24.023.6

20.019.6

10 2.54

v

0.812.211.8

1.27

e 2

5.08 2.41.6

E h

6 2.001.45

2.11.8

3.43.1 4.3

12.411.0

Qj

0.4

w

0.03

x

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15. Soldering

This text provides a very brief insight into a complex technology. A more in-depth accountof soldering ICs can be found in Application Note AN10365 Surface mount reow soldering description .

15.1 Introduction to solderingSoldering is one of the most common methods through which packages are attached toPrinted Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides boththe mechanical and the electrical connection. There is no single soldering method that isideal for all IC packages. Wave soldering is often preferred when through-hole andSurface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is notsuitable for ne pitch SMDs. Reow soldering is ideal for the small pitches and highdensities that come with increased miniaturization.

15.2 Wave and reow solderingWave soldering is a joining technology in which the joints are made by solder coming froma standing wave of liquid solder. The wave soldering process is suitable for the following:

Through-hole components Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadlesspackages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,due to an increased probability of bridging.

The reow soldering process involves applying solder paste to a board, followed bycomponent placement and exposure to a temperature prole. Leaded packages,packages with solder balls, and leadless packages are all reow solderable.

Key characteristics in both wave and reow soldering are:

Board specications, including the board nish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages

Package placement Inspection and repair Lead-free soldering versus PbSn soldering

15.3 Wave solderingKey characteristics in wave soldering are:

Process issues, such as application of adhesive and ux, clinching of leads, boardtransport, the solder wave parameters, and the time during which components areexposed to the wave

Solder bath specications, including temperature and impurities

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15.4 Reow solderingKey characteristics in reow soldering are:

Lead-free versus SnPb soldering; note that a lead-free reow process usually leads tohigher minimum peak temperatures (see Figure 13 ) than a PbSn process, thusreducing the process window

Solder paste printing issues including smearing, release, and adjusting the processwindow for a mix of large and small components on one board

Reow temperature prole; this prole includes preheat, reow (in which the board isheated to the peak temperature) and cooling down. It is imperative that the peaktemperature is high enough for the solder to make reliable solder joints (a solder pastecharacteristic). In addition, the peak temperature must be low enough that thepackages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classied in accordance withTable 9 and 10

Moisture sensitivity precautions, as indicated on the packing, must be respected at alltimes.

Studies have shown that small packages reach higher temperatures during reowsoldering, see Figure 13 .

Table 9. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reow temperature ( C)

Volume (mm 3)

< 350 350

< 2.5 235 220

2.5 220 220

Table 10. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reow temperature ( C)Volume (mm 3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

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For further information on temperature proles, refer to Application Note AN10365 Surface mount reow soldering description .

MSL: Moisture Sensitivity Level

Fig 13. Temperature proles for large and small components

001aac844

temperature

time

minimum peak temperature= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak temperature

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16. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

TDA8566_6 20071015 Product data sheet - TDA8566Q_5TDA8566TH_2

Modications: The format of this data sheet has been redesigned to comply with the new identityguidelines of NXP Semiconductors.

Legal texts have been adapted to the new company name where appropriate. Section 9 Thermal characteristics : changed value of R th(j-c) to 1.3 K/W Figure 7 : values updated Included TDA8566TH1 and TDA8566Q in the data sheet

TDA8566Q_5 20010221 Product specication - -

TDA8566TH_2 20030708 Product specication - -

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17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term short data sheet is explained in section Denitions.

[3] The productstatus of device(s) described in thisdocument may havechanged since this document was published andmaydiffer in case ofmultiple devices.The latestproduct statusinformation is available on the Internet at URL http://www.nxp.com .

17.2 DenitionsDraft The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result inmodications or additions. NXP Semiconductors does not give anyrepresentations or warranties as to the accuracy or completeness ofinformation included herein andshall have no liabilityfor the consequencesofuse of such information.

Short data sheet A short data sheet is an extract from a full data sheetwith thesame product type number(s) andtitle. A short data sheet is intendedfor quick reference only and should not be relied upon to contain detailed andfull information. For detailed and full information see the relevant full datasheet, which is available on request via the local NXP Semiconductors salesofce. In case of any inconsistency or conict with the short data sheet, thefull data sheet shall prevail.

17.3 Disclaimers

General Information in this document is believed to be accurate andreliable. However, NXP Semiconductors does not give any representations orwarranties, expressed or implied, as to the accuracy or completeness of suchinformation and shall have no liability for the consequences of use of suchinformation.

Right to make changes NXP Semiconductors reserves the right to makechanges to information published in this document, including withoutlimitation specications and product descriptions, at any time and withoutnotice. This document supersedes and replaces all information supplied priorto the publication hereof.

Suitability for use NXP Semiconductors products are not designed,authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected toresult in personal injury, death or severe property or environmental damage.NXP Semiconductors accepts no liability for inclusion and/or use of NXPSemiconductors products in such equipment or applications and thereforesuch inclusion and/or use is at the customers own risk.

Applications Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for thespecied use without further testing or modication.

Limiting values Stress above one or more limiting values (as dened inthe Absolute Maximum Ratings System of IEC 60134) may cause permanentdamage to the device. Limiting values are stress ratings only andoperation ofthe device at these or any other conditions above those given in theCharacteristics sections of this document is not implied. Exposure to limitingvalues for extended periods may affect device reliability.

Terms and conditions of sale NXP Semiconductors products are soldsubject to the general terms and conditions of commercial sale, as publishedat http://www.nxp.com/prole/terms , including those pertaining to warranty,intellectual property rights infringement and limitation of liability, unlessexplicitly otherwise agreed to in writing by NXP Semiconductors. In case ofany inconsistency or conict between information in this document and suchterms and conditions, the latter will prevail.

No offer to sell or license Nothing in this document may be interpretedor construed as an offer to sell products that is open for acceptance or thegrant, conveyance or implication of any license under any copyrights, patentsor other industrial or intellectual property rights.

17.4 TrademarksNotice: All referenced brands, product names, service names and trademarksare the property of their respective owners.

18. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofce addresses, send an email to: [email protected]

Document status [1][2] Product status [3] Denition

Objective [short] data sheet Development This document contains data from the objective specication for product development.

Prel iminary [short] data sheet Qualicat ion This document contains data from the preliminary specicat ion.

Product [short] data sheet Production This document contains the product specication.

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NXP B.V. 2007. All rights reserved.For more information, please visit: http://www.nxp.comFor sales office addresses, please send an email to: [email protected]

Date of release: 15 October 2007Document identifier: TDA8566_6

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section Legal information.

19. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 12 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Quick reference data . . . . . . . . . . . . . . . . . . . . . 24 Ordering information. . . . . . . . . . . . . . . . . . . . . 25 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Pinning information. . . . . . . . . . . . . . . . . . . . . . 46.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 57 Functional description . . . . . . . . . . . . . . . . . . . 67.1 Mode select switch (pin MODE) . . . . . . . . . . . . 67.2 Clip detection (pin CLIP). . . . . . . . . . . . . . . . . . 67.3 Short-circuit diagnostic (pin DIAG) . . . . . . . . . . 7

7.4 Temperature pre-warning (pin DIAG) . . . . . . . . 77.5 Open-collector diagnostic outputs . . . . . . . . . . 77.6 Differential inputs . . . . . . . . . . . . . . . . . . . . . . . 88 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 89 Thermal characteristics. . . . . . . . . . . . . . . . . . . 810 Static characteristics. . . . . . . . . . . . . . . . . . . . . 911 Dynamic characteristics . . . . . . . . . . . . . . . . . 1012 Application information. . . . . . . . . . . . . . . . . . 1112.1 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . 1112.2 Mode select switch . . . . . . . . . . . . . . . . . . . . . 1113 Test information. . . . . . . . . . . . . . . . . . . . . . . . 1214 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

15 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1615.1 Introduction to soldering. . . . . . . . . . . . . . . . . 1615.2 Wave and reow soldering . . . . . . . . . . . . . . . 1615.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 1615.4 Reow soldering . . . . . . . . . . . . . . . . . . . . . . . 1716 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 1917 Legal information. . . . . . . . . . . . . . . . . . . . . . . 2017.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 2017.2 Denitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2017.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2017.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 2018 Contact information. . . . . . . . . . . . . . . . . . . . . 2019 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Date post:	04-Jun-2018
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