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TDTL Architecture with Fast Error Correction Technique
O. Al-Ali, N. Anani, and P. PonnapalliSchool of Engineering
Manchester Metropolitan UniversityManchester, UK
M. A. Al-Qutayri and S. R. Al-ArajiCollege of Engineering
Khalifa University of Science, Technology and ResearchSharjah Campus, UAE
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ICECS 2010
ICECS 2010
Outline
• Introduction• Conventional DTL• Conventional TDTL System• Conventional Adaptive TDTL• Adaptive TDTL Structure Based on Comparison• Simulation Results• Conclusions and Future work
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ICECS 2010
Introduction• Phase Lock Loop Types
Analogue Digital
3
ICECS 2010
Introduction• Digital Phase Lock Loop Types
• Digital PLLs: Classified as uniform and non-uniform• Non-uniform:
• ZCDPLL: Zero crossing Digital PLL• CDTL: Conventional Digital Tanlock Loop
• Applications• Clock recovery, hard drive synchronization, satellite
communications
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ICECS 2010
Conventional Digital Tanlock Loop (CDTL)
5
ICECS 2010
Digital Tanlock Loop (DTL)cont.• Phase Detector Characteristics.
where
6
][
cos
sin)( 1
fTanfh
)2mod( f
ICECS 2010
Digital Tanlock Loop (DTL)cont.• Locking Range.
WK 20 1
7
ICECS 2010
Time Delay Tanlock Loop (TDTL)• Block Diagram
8
ICECS 2010
Time Delay Tanlock Loop (TDTL) cont.
• Locking Range.
Where , is the steady state phase error
)sin(
)(sin)(sin212
22
1
W
WWKWo
o
jss ss
9
ICECS 2010
Conventional Adaptive TDTL• Block Diagram
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ICECS 2010
Conventional Adaptive TDTL cont.
Limitation• The feed forward arm is active all the time and
hence burdens the loop whether there is a change in the incoming signal Frequency or not.
Solution• Change the Loop filter only when there is a
change in the incoming signal Frequency.
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ICECS 2010
Adaptive TDTL Structure Based on Comparison• Block Diagram
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ICECS 2010
Adaptive TDTL Structure Based on Comparison cont.• Frequency estimator block diagram.
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DerivativeGain
(1/(2*pi))Envelope Detector
y(t)
Fo Value
+
-
IN
ICECS 2010
Adaptive TDTL Structure Based on Comparison cont.• Controller block diagram.
14
ICECS 2010
Simulation Results
(a) FSK Input Signal, (b) FSK Demodulation using Conventional Adaptive DTL,
(c) FSK Demodulation using AC-TDTL.15
(b)(a)
(c)
FSK Demodulation using Conventional Adaptive DTL
ICECS 2010
FSK and Demodulation using AC TDTL
ICECS 2010
Simulation Results cont.
(a) FSK Input Signal, (b) Phase plane of the conventional Adaptive TDTL
(c) Phase plane of the proposed system AC-TDTL.18
(b)(a)
(c)
ICECS 2010
Conclusion and Future works • The Adaptive TDTL Structure Based on Comparison compares the
frequency of the incoming with that of the DCO signal and acts accordingly without burdening the loop flow.
• This results in substantial improvement in the acquisition time by more than three times.
• The proposed architecture will require some additional circuitry compared to the conventional TDTL in order to implement the adaptation mechanism. However, the additional circuit overhead is considered acceptable in order to achieve the fast acquisition performance as demonstrated by the results.
• Future work will include more extensive evaluation of the loop under different conditions such as noise and high dynamic environment.
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