Team MUX

Adam Burton Mark ColomboDavid Moore Daniel Toler

Introduction

• Overview• (3) 16 Bit Master-Slave Rising edge registers

using transmission gates • ALU comprised of 5 functional blocks– Adder/Subtractor– And– Or– Shift– Multiplier

Team MUX- ALU Block

`

A - 16

B - 16

Control - 3

Out - 16

Cout - 1

8 -1

MU

X

16

16

16

3

16

16Bit Adder

16Bit OR

16Bit AND

16Bit Multiplier

16Bit Shift

3

116

Output Register Value

Adder/Subtractor Bitslice

• In our Adder/Subtractor we had two bit slices with different inverting stages. This was so we could take advantage of the inversion property to cut down on the number of inverters in the carry path.

To MUXX

Y

ZA

BSubSignal

Cin Cout

1Bit Adder (Mirror)

To next bit slice

Shifter Bitslice

Bundled with other Bitslices

X

Shift Amount

Z1Z2Z3Z4

A

B0B1

1 bit shifter (Passgate Logic)

• We used passgate logic because the reduced output swing was not an issue, and we could save area.

Passc2c1c0=001 A0=0>1 Out0=0>1

A0

CLK

A0

Out0Out0

Functionality Plots

ANDC2c1c0=110 A0=1>0 B0=0 Out0=1>0

A0

CLK

Out0Out0

A0

Functionality Plots

SUBc2c1c0=011 A0=1 B0=1 Out0=0

A0,B0

CLK

A0,B0

Out0Out0

Functionality Plots

Innovation

Sizing Strategy What to size How to size it

Design Trade-OffsArbitrary Function – 16 bit multiplier

Sizing

Not on Critical Path Sized to conserve areaOn Critical Path Sized for Delay

Attempted Logical Effort Calculations Result – Tapered Path for reduced delay Optimized further through simulation

Buffers between registers and ALU

Trade-Offs

Considered Carry Look-ahead Adder Additional area and power Small benefit to delay

Supply Voltage Higher Better Delay, More Power Lower Worse Delay, Less Power Decided on Delay due to being squared in metric,

used 5V

Innovation in Multiplier

To produce a 16-bit output, need 8-bit multiplier

Team MUX Multiplier is 16 bitsDespite limited output width, offers more

flexibility

Multiplier Attributes

The multiplier is a basic array-based multiplier.

Delay through the multiplierPower consumption of the multiplier

Results

Worst case delay analyzed 0x7FFF + 0x0001  Caused all bits to flip Period: 7ns Frequency: 143 MHz

Results

Area measurementCounted up widthsExcluded buffers and multiplier Width: 4.2115*10^-3 m

Results

Energy calculationCycle through all functions with alternating

inputIntegrated instantaneous power over period

of operationEnergy: 2.3426*10^-9 J

Results

Final Metric D^2*A*EMetric: 4.846*10-28 s^2*m*J

Conclusion

Meets or exceeds all specificationsImplements all functionsLow metric valueMultiplier is a valuable, common function

Questions?