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TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

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TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA
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Page 1: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

TECHNICAL QUIZ-1

EC6302 – DIGITAL ELECTRONICSSUBJECT HANDLER: U.POORNIMA

Page 2: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

1. The output of an exclusive-NOR gate is 1. Which input combination is correct?

a. a = 1, b = 0b. a = 0, b = 1c. a = 0, b = 0d. none of the above

Page 3: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

2. Before an SOP implementation, the expression would require a total of how many gates?

a. 1b. 2c. 4d. 5

Page 4: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

3. A 4-variable AND-OR-Invert circuit produces a 0 at its Y output. Which combination of inputs is correct?

a. b.c. d.

none of the above

Page 5: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

4. To implement the expression , it takes one OR gate and how many other gates along with that?

a. Three and gates and three invertersb.Three and gates and four invertersc. Three and gatesd.One and gate

,

Page 6: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

5. How many AND gates are required to implement the Boolean expression,

? a.1b.2c.3d.4

Page 7: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

6. How many NOT gates are required to implement the Boolean expression,

? a.1b.2c.4d.5

Page 8: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

7. The inverter can be produced with how many NAND gates?

a.1b.2c.3d.4

Page 9: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

8. A 4-variable AND-OR circuit produces a 0 at its Y output. Which combination of inputs is correct?

a.A = 0, b = 0, c = 1, d = 1b.A = 1, b = 1, c = 0, d = 0c.A = 1, b = 1, c = 1, d = 1d.A = 1, b = 0, c = 1, d = 0

Page 10: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

9. A 4-variable AND-OR circuit produces a 1 at its Y output. Which combination of inputs is correct?

a.A = 0, b = 0, c = 0, d = 0b.A = 0, b = 1, c = 1, d = 0c.A = 1, b = 1, c = 0, d = 0d.A = 1, b = 0, c = 0, d = 0

Page 11: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

10. Implementation of the Boolean expression results in how many basic gates?

a.Three and gates, one or gateb.Three and gates, one not gate, one or gatec.Three and gates, one not gate d.Three and gates, three or gates three or gates

Page 12: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

11. What is the possible output expression for an AND-OR-Invert circuit having one AND gate with inputs A, B, and C and one AND gate with inputs D and E?

a. b.c. d.

Page 13: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

12. How many 2-input NOR gates does it take to produce a 2-input NAND gate?

a.1 b.2c.3 d.4

Page 14: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

13. How many numbers of gates that a logic circuit contains with an output ?

a.2 and gates, 2 or gates, 2 inverters b.3 and gates, 2 or gates, 1 inverterc.2 and gates, 1 or gate, 2 inverters d.2 and gates, 1 or gate

Page 15: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

14. What may be the values of A, B, C, and D that make the sum term equal to zero?

a.A = 1, b = 0, c = 0, d = 0b.A = 1, b = 0, c = 1, d = 0c.A = 0, b = 1, c = 0, d = 0d.A = 1, b = 0, c = 1, d = 1

Page 16: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

15. One of De Morgan's theorems states that

. How can we state that logically there is no difference between them?

a. a NOR and an AND gate with inverted inputsb. a NAND and an OR gate with inverted inputsc. an AND and a NOR gate with inverted inputsd. a NOR and a NAND gate with inverted inputs

Page 17: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

16. The commutative law of Boolean addition states that A + B = A × B.Is it true?

a.True b.False

Page 18: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

17. What will be the outcome, if we apply DeMorgan's theorem to the expression ?

a. b.c. d.

Page 19: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

18. How the systematic reduction of logic circuits is accomplished?

a.Using boolean algebrab.Symbolic reductionc.TTL logicd.Using a truth table

Page 20: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

19. What will be the gate, if an AND gate with schematic "bubbles" on its inputs?

a.NOTb.ORc.NORd.NAND

Page 21: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

20. For the SOP expression , how many 1s are in the truth table's output column?

a.1 b.2c.3 d.5

Page 22: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

21. A truth table for the SOP expression has how many input

combinations?a.1 b.2c.4 d.8

Page 23: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

22. How many gates would be required to implement the following Boolean expression before simplification? XY + X(X + Z) + Y(X + Z)

a.1 b.2c.4 d.5

Page 24: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

23. Determine the values of A, B, C, and D that make the product term equal to 1

a.A = 0, B = 1, C = 0, D = 1b.A = 0, B = 0, C = 0, D = 1c.A = 1, B = 1, C = 1, D = 1d.A = 0, B = 0, C = 1, D = 0

Page 25: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

24. What is the primary motivation for using Boolean algebra to simplify logic expressions?

a.It may make it easier to understand the overall function of the circuit.

b.It may reduce the number of gates.c.It may reduce the number of inputs required.d.All of the above

Page 26: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

25. AC + ABC = AC. Is it true?a.Trueb.False

Page 27: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

26. Which Boolean algebra property allows us to group operands in an expression in any order without affecting the results of the operation [for example, A + B = B + A]?

a.Associativeb.Commutativec.Booleand.Distributive

Page 28: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

27. The output of an exclusive-NOR gate is 1. Which input combination is correct?

a.a = 1, b = 0b.a = 0, b = 1c.a = 0, b = 0d.none of the above

Page 29: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

28. When grouping cells within a K-map, how the cells must be combined in groups?

a.2sb.1, 2, 4, 8, etc.c.4sd.3s

Page 30: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

29. Why the NAND or NOR gates are referred to as "universal" gates?

a.Can be found in almost all digital circuitsb.Can be used to build all the other types of

gatesc.Are used in all countries of the worldd.Were the first gates to be integrated

Page 31: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

30. A Karnaugh map is a systematic way of reducing which type of expression?

a.Product-of-sumsb.Exclusive norc.Sum-of-productsd.Those with overbars

Page 32: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

31. The Boolean expression is logically equivalent to what single gate?

a.NAND b.NORc.ANDd.OR

Page 33: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

32. For the SOP expression , how many 0s are in the truth table's output column?

a.zero b.1c.4 d.5

Page 34: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

33. Which statement below best describes a Karnaugh map?

a.A Karnaugh map can be used to replace Boolean rules.

b.The Karnaugh map eliminates the need for using NAND and NOR gates.

c.Variable complements can be eliminated by using Karnaugh maps.

d.Karnaugh maps provide a cookbook approach to simplifying Boolean expressions.

Page 35: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

34. Which of the following is an important feature of the sum-of-products (SOP) form of expression?

a.All logic circuits are reduced to nothing more than simple AND and OR gates.

b.The delay times are greatly reduced over other forms.

c.No signal must pass through more than two gates, not including inverters.

d.The maximum number of gates that any signal must pass through is reduced by a factor of two.

Page 36: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

35. Which is the gate performs the same function if an OR gate with schematic "bubbles" on its inputs?

a.NORb.ORc.NOTd.NAND

Page 37: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

36. The expression W(X + YZ) can be converted to SOP form by applying which law?

a.Associative lawb.Commutative lawc.Distributive lawd.None of the above

Page 38: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

37. What the commutative law of addition and multiplication indicates?

a.we can group variables in an AND or in an OR any way we want

b.an expression can be expanded by multiplying term by term just the same as in ordinary algebra

c.the way we OR or AND two variables is unimportant because the result is the same

d.the factoring of Boolean expressions requires the multiplication of product terms that contain like variables

Page 39: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

38. Which of the following combinations cannot be combined into K-map groups?

a.Corners in the same rowb.Corners in the same columnc.Diagonald.Overlapping combinations

Page 40: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

39. Any number with an exponent of zero is equal to:

a.Zero b.Onec.That numberd.Ten

Page 41: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

40. In the decimal numbering system, what is the MSD?

a.The middle digit of a stream of numbersb.The digit to the right of the decimal pointc.The last digit on the rightd.The digit with the most weight

Page 42: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

41. What is the requirement of a full subtractor circuit?

a.Two inputs and two outputsb.Two inputs and three outputsc.Three inputs and one outputd.Three inputs and two outputs

Page 43: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

42. When the output of an AND gate is LOW?a.all the timeb.when any input is LOWc.when any input is HIGHd.when all inputs are HIGH

Page 44: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

43. What is the decimal value of binary 100102?

a.610 b.910

c.1810 d.2010

Page 45: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

44. When the output of a NOT gate is HIGH?a.The input is lowb.The input is highc.The input changes from low to highd.Voltage is removed from the gate

Page 46: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

45. When the output of an OR gate is LOW?a.all inputs are LOWb.any input is LOWc.any input is HIGHd.all inputs are HIGH

Page 47: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

46. A 4-variable AND-OR-Invert circuit produces a 0 at its Y output. Which combination of inputs is correct?

a.b.c.d.none of the above

Page 48: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

47. The inverter can be produced with how many NAND gates?

a. 1b. 2c. 3d. 4

Page 49: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

48. How many 2-input NOR gates does it take to produce a 2-input NAND gate?

a. 1b. 2c. 3d. 4

Page 50: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

49. What is the major difference between half-adders and full-adders?

a. Nothing basically; full-adders are made up of two half-adders.

b. Full adders can handle double-digit numbers.c. Full adders have a carry input capability.d. Half adders can handle only single-digit

numbers.

Page 51: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

50. When performing subtraction by addition in the 2's-complement system:

a. the minuend and the subtrahend are both changed to the 2's-complement.

b. the minuend is changed to 2's-complement and the subtrahend is left in its original form.

c. the minuend is left in its original form and the subtrahend is changed to its 2's-complement.

d. the minuend and subtrahend are both left in their original form.

Page 52: TECHNICAL QUIZ-1 EC6302 – DIGITAL ELECTRONICS SUBJECT HANDLER: U.POORNIMA.

THANK YOU


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