25.11.2014
1
Computer System Structures
cz:Struktury počítačových systémů
Lecturer: Richard Šusta
ČVUT-FEL in Prague, CR – subject A0B35SPS
Version: 1.0
Technologie pro FPGA
What is it inside?
[ http://radio411.com/ ]
25.11.2014
2
The Memory Element
There are four kinds
SRAM brought to us by Xilinx
EEPROM brought to us by Altera
Flash (EEPROM) brought to us by
Actel
Antifuse brought to us by Actel
R
E
F
A
SPS 4
CMOS SRAM Cell Advantages
Static RAM (SRAM)
+ Unlimited fast read / write programming cycles
bit’ bit
word
R
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3
SPS 5
SRAM Drawbacks
Static (SRAM)
- Data stored only as long as supply is applied
- Large (4-6 transistors/cell)
R
SPS 6
DRAM - Dynamic RAM
Write: 1. Drive bit line
2. Select row
Read: 1. Precharge bit line to Vdd/2
2. Select row
3. Cell and bit line share charges Minute voltage changes on the bit line
4. Sense (fancy sense amp) Can detect changes of ~1 million electrons
5. Write: restore the value
Refresh 1. Just do a dummy read to every cell.
row select
bit
Read is really a read followed by a restoring write
DRAMs are smaller, but they require periodical refreshing
and are suitable only as internal memory in FPGA
[Source: Vijay Narayanan: FPGA technolgies]
R
25.11.2014
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Volatile Memory Comparison
Larger cell lower density,
higher cost/bit
No refresh required
No dissipation of data
Read non-destructive
Simple read faster access
Standard IC process natural
for integration with logic
Smaller cell higher density,
lower cost/bit
Needs periodic refresh,
and refresh after read
Complex read longer access
time
Special IC process difficult to
integrate with logic circuits
word line
bit line bit line
word line
bit line
The primary difference between different memory types is the bit cell.
addr
data
SRAM DRAM
[Source: Vijay Narayanan: FPGA technolgies]
R
EEPROM: FLOTOX transistor
Floating gate
Source
Substrate p
Gate
Drain
n 1 n 1
FLOTOX transistor Fowler-Nordheim
I-V characteristic
20 – 30 nm
10 nm
-10 V
10 V
I
V GD
• Applying high voltage over this insulator allows electron to travel
to/from floating gate via Fowler-Nordheim tunneling.
• Erasing only requires reversing applied voltage.
[Source: Vijay Narayanan: FPGA technolgies]
E
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EEPROM Cell
WL
BL
V DD
Access Device
Programming Device
• Removing too much charge from
floating gate results in a depletion
device that cannot be turned off by
the standard word-line signals.
• Extra transistor is required to access
the transistor and FLOTOX
transistor is used only for storage
(open or closed).
• Fabrication of thin oxide is
challenging and costly
• Repeated programming causes shift
in threshold voltages
[Source: Vijay Narayanan: FPGA technolgies]
E
Flash EEPROM
Control gate
erasure
p- substrate
Floating gate
Thin tunneling oxide
n 1 source n 1 drain programming
Extra transistor of EEPROM is eliminated.
F
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Basic Operations in a NOR Flash Memory―Write
Always off
- Apply high voltage at gate to write selected device.
- Raises threshold of device. [Source: Vijay Narayanan: FPGA technolgies]
F
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Basic Operations in a NOR Flash Memory―Erase
- Erase all cells simultaneously via tunneling by applying high
voltage at source.
[Source: Vijay Narayanan: FPGA technolgies]
F
Basic Operations in a NOR Flash Memory―Read
- Read operation is the same as any NOR ROM structure.
[Source: Vijay Narayanan: FPGA technolgies]
F
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Cross-sections of NVM cells
EPROM Flash Courtesy Intel
F
SRAM / Flash F
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Struktura AntiFuse
substrát
Kov 1
oxid
amorfní silikon oxid oxid
Kov 2
Obrázek platí pro nepoužívanější technologie ViaLink či MicroVia, obě se liší jen použitými kovy 1 a 2
A
Metal to metal antifuse moved the antifuse out of silicon
making the part denser and faster
A
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Logic Logic
M1 M1
M2 M2
Logic Logic
M1
M2
M1 M1 M1
M2
M1 M1
M2
M3 M3
M2
SRAM SRAM
Antifuse
Antifuse: SX Routing Efficiency
Faster Signal Propagation than SRAM FPGA
Signals travel through more interconnect in SRAM
Interconnect dominates delays in deep sub-micron
Antifuse architecture uses minimum silicon area
SRAM needs silicon overhead for interconnect
A
Antifuse / Flash
45 nm
Vivien, L.: FPGA Technologies
25.11.2014
11
SEE problems SEU: Single Event Upset
- a change of state or transient induced by an energetic particle such as a cosmic ray or proton in a device. This may occur in digital, analog, and optical components or may have effects in surrounding interface circuitry (a subset known as Single Event Transients [SETs]). These are "soft" errors in that a reset or rewriting of the device causes normal device behavior thereafter.
SHE: Single Hard Error - an SEU which causes a permanent change to the operation of a device. An example is a stuck bit in a memory device.
SEE: Single Event Effect - any measurable effect to a circuit due to an ion strike, includes SEU, SHE and others.
from: http://nepp.nasa.gov/
R E F A
Přehled technologií
Podle McCollum, J: Programmable Elements and Their Impact on FPGA Architecture, Performance, and
Radiation Hardness
SRAM Antifuse Flash EEPROM
Velikost buňky 1 1/10 1/7 1/3
Rychlost (←kapacita, odpor) Horší Výborná Horší? Střední
Hustota integrace Střední Dobrá Výborná Horší
Odolnost vůči záření Špatná Výborná Střední Střední
Energetická náročnost Různá Výborná Horší Dobrá
Kritérium / Typ
Přeprogramování Ano,
neomezeně Ne Ano,
<100000 Ano,
<1000
R E F A
dobrá Cena výborná horší horší
100% Testovatelnost při výrobě 100% Ne, 1-3% vad 100%
Odolnost utajení návrhu úroveň 0,
1 jen při šifrování
úroveň 3,
(pozn. IO mají 2) >4, skoro
nemožné
>4, skoro
nemožné
25.11.2014
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DE0
Price: $119
Academic: $79
http://www.terasic.com.tw/
• Altera Cyclone III 3C16 FPGA
Logic elements (LEs) 15,408
M9K embedded memory blocks 56
Embedded memory (Kbits) 504
18-bit x 18-bit embedded
multipliers 56
Phase-locked loops (PLLs) 4
Maximum user I/O pins 346
Semi-Programmable ASIC
Neprovádím obyčejnou konstrukci,
ale dělám věčnou rekonstrukci! [www.metropoleparis.com/]
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SPS 25
Opakování: Realizace logiky
Programovatelné ASIC
Application Specific Integrated Circuits
• Programmable Logic Device (PLD)
• Complex PLD (CPLD )
• Field Programmable Gate Arrays (FPGAs)
Microprocessor
& RAM
Full Custom
Standard
Logic
TTL
74xx
CMOS
4xxx
ASICs
Gate
Arrays
Standard
Cells
Programmable
PLDs FPGAs CPLDs
Semi-Programmable
Již téměř nepoužívané G S
SPS 26
Gate Array
Vd
d G
nd
Horizontal Routing Channel Vertic
al R
outin
g C
hannel
Sea of Gates: Routing Channels removed,
route at higher metal layers
G
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SPS 27
Gate Array Example
Vd
d G
nd
A A
B B
Vdd Vdd
Schematic
A
A
B
B
Out
Out
G
SPS 28
Gate-array Layout
Transistors pre-placed, fixed in size
Personalized by metal routing
Fastest to manufacture
Lowest mask cost
Lends itself to automated placement and wiring
G
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SPS 29
Gate-array Disadvantages
Non-optimized spacing
Limited transistor sizing options
Density
Performance
Power
Wiring blockages/inefficiencies
Excess circuitry
G
SPS 30
Standard Cell Layout
Routing Channel
Routing Channel Feed-through cell
Note uniform
height
S
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SPS 31
Standard Cell Layout
Design partitioned into cells of standard height
Power and Ground (Power grid) wiring preset
Technology provider supplies libraries of pre-designed cell
elements for usage (utilize varying numbers of cells)
Primitives (NAND, NOR, etc.)
Storage Elements (DFF)
Libraries can be tailored to specific applications (e.g., low
power vs. high performance)
Requires full manufacturing sequence
Typically automated place and wiring
S
SPS 32
Standard Cell Disadvantages
Cell height restrictions limits cell library contents
Full set of masks
Longer manufacturing times
S
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SPS 33
Macro-cell Layout
Library elements provided by technology
supplier (e.g., foundry)
Elements can be of varying heights and widths
Richer variety of library elements (IP friendly)
S
SPS 34
Macro-cell Disadvantages
Similar to Standard-cell in length of
manufacturing times, mask costs
Placement and wiring more complex
Pre-layout of power grid more difficult, may not
be possible
S
25.11.2014
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Finite State Machines
Automata
Automaton, pl. Automata
– odborná angličtina užívá latinské skloňování
SPS 36
Binary Counter State Diagram
S0
000
S5
101 S3
011
S1
001 S7
111
S6
110 S2
010
S4
100
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SPS 37
Example:Debouncer (cz:odrušení vstupu)
S1
S2
X=1
X=1
X=1
S0
X=0 S3
X=0
Z=0
Z=1
Z=0 Z=1
X=1
X=0 X=0
38
Ancient controller:
On an Apple being lifted, Hercules shoots a Dragon
which then hisses. Hero from Alexandria, Pneumatica.
25.11.2014
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39
Control Units (in Czech "řadiče")
the most probable action – go to the next state
- e.g. control unit of furnace
they generate control signals, conditions
accomplishing
1
2
Water
3
Fire
4
Bell Start=1 Full=1
Start=0 Full=0 Boil =0 Human=0
Human=1, confirmation
Boil=1
& Full =0
Boil=1
Full =1
Computer
Processor
Control Unit
Da
tap
ath
Memory
Devices
Input
Output
Processor
Control Unit - cz:Řadič -
Datapath cz:?cesta dat?
Control Signals
State signals
Program
25.11.2014
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Boiler and its analogy
Music box, Leopold Aucac Aine, Paris
42
Control unit
BELL
Counter
-memory
of pos.
Decoder
One
Hot
WATER
FIRE
Multi-
plexor FULL
BOILING
HUMAN
START enable
clock
Start
1 Water
+
-
Full
2 Fire
+
-
Boiling
3 Bell
+
-
Human
4
+
-
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43
Electromechanical Control Unit
Relay
Non-stabilized AC power
Step
motor
Co
nd
ition
al
Start
Full
Boiling
Human
co
nta
cts
Program drum
with jags
Water
Fire
Bell
Ou
tpu
t
co
nta
cts
44
Animation: Electromechanical Control Unit 1/5
Relay
Non-stabilized AC power
Step
motor
Co
nd
ition
al
Start
Full
Boiling
Human
co
nta
cts
Program drum
with jags
Water
Fire
Bell
Ou
tpu
t
co
nta
cts
25.11.2014
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45
Animation: Electromechanical Control Unit 2/5
Relay
Non-stabilized AC power
Step
motor
Co
nd
ition
al
Start
Full
Boiling
Human
co
nta
cts
Program drum
with jags
Water
Fire
Bell
Ou
tpu
t
co
nta
cts
46
Animation: Electromechanical Control Unit 3/5
Relay
Non-stabilized AC power
Step
motor
Co
nd
ition
al
Start
Full
Boiling
Human
co
nta
cts
Program drum
with jags
Water
Fire
Bell
Ou
tpu
t
co
nta
cts
25.11.2014
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47
Animation: Electromechanical Control Unit 4/5
Relay
Non-stabilized AC power
Step
motor
Co
nd
ition
al
Start
Full
Boiling
Human
co
nta
cts
Program drum
with jags
Water
Fire
Bell
Ou
tpu
t
co
nta
cts
48
Animation: Electromechanical Control Unit 5/5
Relay
Non-stabilized AC power
Step
motor
Co
nd
ition
al
Start
Full
Boiling
Human
co
nta
cts
Program drum
with jags
Water
Fire
Bell
Ou
tpu
t
co
nta
cts
25.11.2014
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49
Control Unit You know it...
50
Control Units w/o Input Conditions
Heron of Alexandria, 1st century
Famous automaton from 19th century
25.11.2014
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51
Astronomical clock
Program stored in cogwheel
(cz:ozubené kolo)
= memory of state
A rod for
transmitting
information
from clock
[Zdroj: Šíma, Z.: Astronomical clocks - HI-TECH of the 14th century,
Google search "Orloje - hi-tech 14. století" (1. a 2. část)]
52
Cz:Konečno a nekonečno...
Konečná kola mají
své celočíselné limity....
Schéma funkce 3 hlavních kol orloje
Chyba pohybu Měsíce v závislosti na
počtu zubů kol (tj. stavů), žel přesná
hodnota je necelé číslo, a tak nelze
popsat konečným převodem
25.11.2014
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General Sequential Circuit as Finite State Machine (FSM)
δ Next State
Combinatorial
Logic
ω - Output
Combinatorial
Logic
Memory:
flip-flops
with common
clock
Syn
ch
ron
ou
s
Inp
uts
of
SC
Synchronizing clock signal
Asynchr. inputs
Asynchronous inputs of SC with immediate influence to outputs i
are utilized only for "Power Up" initializations
Asynchronous inputs
D >C
D >C
Example:
2 bit memory
from 2 D-flip-flops
with common clock
CLK
CLR
CLR
ACLRN 53
Syn
ch
ron
ou
s
Ou
tpu
ts o
f S
C
SPS 54
FSMs in VHDL
FSMs are preferable styles of process
codes - they can be easily converted into
logical elements!
• State transitions (δ function) should be
described in a process sensitive to clock
and asynchronous reset signals only!
• Outputs of FSM (ω function) should be
described as concurrent statements
outside the process!
25.11.2014
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Mealy and Moore
Finite State Machines/Automata
Flip
Flops
ω Output
Combinatorial
Logic
δ Next State
Combinatorial
Logic
Mealy Machine
Inputs Outputs
Flip
Flops
ω Output
Combinatorial
Logic
δ Next State
Combinatorial
Logic
Moore Machine
Inputs Outputs
SPS 56
Moore and Mealy Differences
Moore and Mealy machine are mutually convertible in all cases.
Selection guide: There are four major differences between the Moore machine
and Mealy machine-based designs.
1.A Mealy machine normally requires fewer states to perform the same task.
2.A Mealy machine can generate a faster response. Since a Mealy output is a
function of input, it changes whenever the input meets the designated
condition.
3.In a Mealy machine, the width of an output signal is determined by the input
signal. Glitches in the input signal are passed as undesired disturbances to
the output. The output of a Moore machine is synchronized with the clock
edge and its width is about the same as a clock period. It is not susceptible to
glitches from the input signal.
4.Moore machines are more advantageous for analyses because they have
better verifiability and information capability.
25.11.2014
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4bit Counter versus Boiler
S0
S2
S3 S1
Moore
Machine X Z
S0
S1
X=START
X=START
X=HUMAN
X=FULL
S3
X=BOILING S2 X=FULL
X = 0
Z=0
Z=FIRE
Z=BELL
Z=WATER
X=BOILING
Z=0
Z=1
Z=2
Z=3
X=don't care
Automaton/FSM in VDHL
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30
SPS 59
Full code: VHDL State Model of Counter
LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY citac IS PORT ( clock, reset : IN STD_LOGIC := '0';
Z : OUT STD_LOGIC_VECTOR(1 downto 0) );
END citac;
ARCHITECTURE RTL OF citac IS
SIGNAL state : integer range 0 to 3;
BEGIN
PROCESS (clock, reset) -- transient function
BEGIN
IF rising_edge(clock) THEN
IF (reset='1') THEN state <= 0; Z<="00";
ELSE CASE state IS -- state:=state+1;
WHEN 0 => Z <= "00"; state <= 1;
WHEN 1 => Z <= "01"; state <= 2;
WHEN 2 => Z <= "10"; state <= 3;
WHEN 3 => Z <= "11"; state <= 0;
END CASE;
END IF;
END IF;
END PROCESS;
END;
SPS 60
VHDL State Model of Counter
LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY citac2bit IS
PORT
( clock, reset : IN STD_LOGIC := '0';
Z : OUT STD_LOGIC_VECTOR(1 downto 0)
)
END;
EP: entity-ports
L:Libraries
Moore
Machine
X = reset
input of FSM
Z
output of FSM
clock
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SPS 61
VHDL State Model of Counter
ARCHITECTURE RTL OF citac IS
SIGNAL state : std_logic_vector(1 downto 0);
BEGIN
PROCESS (clock, reset) -- FSM
BEGIN
IF rising_edge(clock) THEN
IF (reset='1') THEN state <= "00";
ELSE
CASE state IS -- state:=state+1;
WHEN "00" => state <= "01";
WHEN "01" => state <= "10";
WHEN "10" => state <= "11";
WHEN "11" => state <= "00";
END CASE;
END IF;
END IF;
Z<=state;
END PROCESS;
END;
PS: process
-synchronous part
AD: architecture-declarations
PC: process-clock test
PH: process-header with sensitivity list
state:synchronous reset
state: next
state+output
Used: 2 LE/2 Reg (i.e. 2 logic elements, all of them as registers)
PCS: process-concurrent statements
SPS 62
VHDL State Model of Counter
ARCHITECTURE RTL OF citac IS
SIGNAL state : std_logic_vector(1 downto 0);
BEGIN
PROCESS (clock, reset) -- FSM
BEGIN
IF rising_edge(clock) THEN
IF (reset='1') THEN state <= "00";
ELSE
CASE state IS -- state:=state+1;
WHEN "00" => state <= "01";
WHEN "01" => state <= "10";
WHEN "10" => state <= "11";
WHEN "11" => state <= "00";
END CASE;
Z<=state;
END IF;
END IF;
END PROCESS;
END;
PS: process
-synchronous part
Used:4 LE/4 Reg
Assignments of signals, here signal Z, inside of a
process synchronous part create additional memory
elements and add clock delays !
25.11.2014
32
SPS 63
Disadvantages of Single Process
The counter was designed as a single process with numeric
codes of states directly corresponding to outputs, so any
future changes in generated output signals will require
assigning new codes for states and rewrite program
=> Solution: Use symbolic names for states
the next state function contains two independent operations
- next state and output function increasing of their
complexity will decrease transparency of program
=> Solution: Separate output and next state functions
The code contains many fixed predefined parts for reset and
clocks - any unintentional change in them will cause errors
=> Solution: Separate clock section
SPS 64
State Encoding
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SPS 65
State Encoding Problem
State Encoding Can Have a Big Influence
on Optimality of the FSM Implementation
No methods other than checking all possible
encodings are known to produce optimal
circuit, but it is feasible for small circuits only
SPS 66
Types of State Encodings (1)
Binary (Sequential) – States Encoded as Consecutive Binary Numbers
Small number of used flip-flops
Potentially complex transition functions leading to slow implementations
One-Hot – Only One Bit Is Active
Number of used flip-flops as big as number of states
Simple and fast transition functions
Preferable coding technique in FPGAs
Using Enumerated Types for States in VHDL Leaves Encoding Problem for Synthesis Tool
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SPS 67
Types of State Encodings (2)
State Binary Code One-Hot Code
S0 000 10000000
S1 001 01000000
S2 010 00100000
S3 011 00010000
S4 100 00001000
S5 101 00000100
S6 110 00000010
S7 111 00000001
SPS 68
68
State Encoding (3)
Minimum-bit change: assigns codes to states so that
the total number of bit changes for all state
transitions is minimized.
25.11.2014
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SPS 69
Enconding of states (4)
type state_enum is (s0, s1);
SUBTYPE state_type is STD_LOGIC_VECTOR(1 DOWNTO 0);
CONSTANT s0 : state_type := "01" ;
CONSTANT s1 : state_type := "11" ;
signal state, state_reg : state_enum;
Encoding by subtype
Encoding by enum
constant s0 : integer := 0;
constant s12 : integer := 1;
constant s3 : integer := 2;
signal state, state_reg : integer range 2 downto 0;
SPS 70
Language Features: SUBTYPES
SUBTYPE = TYPE + constraints on values
TYPE is the base-type of SUBTYPE
SUBTYPE inherits all the operators of TYPE
SUBTYPE can be more or less used interchangeably with TYPE
examples subtype small_integer is integer range 0 to 5;
subtype regB is std_logic_vector(5 downto 2);
signal x : small_integer;
signal y : regB;
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SPS 71
VHDL Structure of FSM
SPS 72
Moore FSM as 3 Processes
Present State
Register
δ Next State
function
ω Output
function
X:set of inputs
PresentStateRegister
Next State
Z:set of outputs
clock
reset_asyn
concurrent
statements
reset
synchronous
NextStateFunction
OutputFunction
25.11.2014
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SPS 73
Mealy FSM as 3 Processes
Present State
Register
δ Next State
function
ω Output
function
X:set of inputs
PresentStateRegister
Next State
Z:set of outputs
clock
reset_asyn
concurrent
statements
reset
synchronous
NextStateFunction
OutputFunction
SPS 74
Counter as Moore FSM (1/5)
Present State
Register
Next State
function
Output
function
stReg - present state
stored in a register
Next State - stNext
Z - outputs depend
only on stReg state
clock
concurrent
statements
reset
reset_asyn
X-inputs
25.11.2014
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SPS 75
Counter as Moore FSM (1/6)
LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY citac2bit IS
PORT
( clock, reset : IN STD_LOGIC := '0';
Z : OUT STD_LOGIC_VECTOR(1 downto 0)
)
END;
ARCHITECTURE RTL OF citac2bit IS
TYPE state_enum IS (state0, state1, state2, state3);
SIGNAL stReg, stNext : state_enum;
BEGIN
-- 3 processes
END;
EP: entity-ports
L:Libraries
SPS 76
Counter as Moore FSM (2/6)
ARCHITECTURE RTL OF citac2bit IS
PresentStateRegister : PROCESS (clock , reset_asyn)
BEGIN ... END PROCESS;
NextStateFunction : PROCESS (stReg, reset , inputs)
BEGIN ... END PROCESS;
OutputFunction : PROCESS(stReg)
BEGIN ... END PROCESS;
END RTL;
Note: reset_asyn and
inputs are stroke out
because they are not
used in the counter
25.11.2014
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SPS 77
Counter as Moore FSM (3/6)
PresentStateRegister : PROCESS (clock)
BEGIN -- state register
IF rising_edge(clock) THEN stReg <= stNext;
END IF;
END PROCESS;
PresentStateRegister : PROCESS (clock, reset_asyn)
BEGIN
IF reset_asyn ='0' THEN stReg <= a_initial_state;
ELSIF rising_edge(clock) THEN stReg <= stNext;
END IF;
END PROCESS;
SPS 78
Counter as Moore FSM (4/6)
NextStateFunction : PROCESS (stReg, reset) -- transient function
BEGIN
IF (reset='1') THEN stNext <= state0;
ELSE
CASE stReg IS
WHEN state0 => stNext <= state1;
WHEN state1 => stNext <= state2;
WHEN state2 => stNext <= state3;
WHEN state3 => stNext <= state0;
WHEN OTHERS =>
report "Reach undefined state";
-- if it is active -> the error will be in compile time
END CASE;
END IF;
END PROCESS;
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SPS 79
Counter as Moore FSM (5/6)
OutputFunction : PROCESS (stReg) --output function
BEGIN
CASE stReg IS
WHEN state0 => Z <= "00";
WHEN state1 => Z <= "01";
WHEN state2 => Z <= "10";
WHEN state3 => Z <= "11";
END CASE;
END PROCESS;
SPS 80
Counter as Moore FSM (6/6)
clk
reset
state0
state1
state2
clock
reset
Z[1..0]
Z~0
Z~1
stReg
state1 state2 state3reset
state0
state0 0 0 0 0
state1 0 0 1 1
state2 0 1 0 1
state3 1 0 0 1
Quartus Encoding
reset
reset
reset
not reset not reset not reset
RTL View
25.11.2014
41
SPS 81
Q: Possible Modification
Q: Is it possible add
the output function
into the case
statement of preset
register state
process?
A, Yes, but output Z
will be uninitialized
before reset signal.
Present State
Register
Next State
function
Output
function
Inputs
Next State
Outputs
clock
reset_asyn
concurrent
statements
of process
reset
synchrono
us
ω
But always keep the next state function
in a separate process to prevent 1 clock delays
SPS 82
Modification 1: for smaller code
NextStatePlusOutputFunction : PROCESS (stReg, reset)
BEGIN
IF (reset='1') THEN stNext <= state0;
ELSE
CASE stReg IS
WHEN state0 => stNext <= state1; Z <= "00";
WHEN state1 => stNext <= state2; Z <= "01";
WHEN state2 => stNext <= state3; Z <= "10";
WHEN state3 => stNext <= state0; Z <= "11";
WHEN OTHERS => report "Reach undefined state";
END CASE;
END IF;
END PROCESS;
Notice that Z will be assigned
for the first time after 1st clock
25.11.2014
42
SPS 83
Modification 1: for smaller code
3 processes -> outputs are created by combinational circuit - they depend on
initialized state and contain glitches
2 processes - outputs are set added after reset end
SPS 84
Modification 2 for better transparency
NextStateFunction : PROCESS (stReg, reset) -- transient function
BEGIN
IF (reset='1') THEN stNext <= state0;
ELSE
CASE stReg IS WHEN state0 => stNext <= state1;
WHEN state1 => stNext <= state2;
WHEN state2 => stNext <= state3;
WHEN state3 => stNext <= state0;
WHEN OTHERS => report "Reach undefined state";
END CASE;
CASE stReg IS WHEN state0 => Z <= "00";
WHEN state1 => Z <= "01";
WHEN state2 => Z <= "10";
WHEN state3 => Z <= "11";
END CASE;
END IF;
END PROCESS;; The code is longer but more readable - unlike smaller variant, it
does not hide important information that the next state and
output function are two independent operations.
25.11.2014
43
SPS 85
Boiler in VHDL
SPS 86
EP: Entity-ports
clock, reset : IN STD_LOGIC := '0';
start, full, boiling, human : IN STD_LOGIC := '0';
water, fire, bell : OUT STD_LOGIC;
•OutputFunction OutputFunction : PROCESS (stReg)
BEGIN case stReg is
when state0=> water <= '0'; fire<='0'; bell <= '0';
when state1=> water <= '1'; fire<='0'; bell <= '0';
when state2=> water <= '0'; fire<='1'; bell <= '0';
when state3=> water <= '0'; fire<='0'; bell <= '1';
end case;
END PROCESS;
Boiler FSM Changes versus Counter (1/3)
25.11.2014
44
SPS 87
•NextStateFunction NextStateFunction : PROCESS (stReg, reset, start, full, boiling, human)
BEGIN
IF reset='1' THEN stNext <= state0;
ELSE
CASE stReg IS
WHEN state0 =>
IF start = '1' THEN stNext <= state1;
ELSE stNext <= state0; -- result of IF must be always defined
END IF;
WHEN state1 =>
IF full = '1' THEN stNext <= state2;
ELSE stNext <= state1;
END IF;
Boiler FSM Changes versus Counter (2/3)
SPS 88
WHEN state2 =>
IF boiling = '1' THEN stNext <= state3;
ELSE stNext <= state2;
END IF;
WHEN state3 =>
IF human = '1' THEN stNext <= state0;
ELSE stNext <= state3;
END IF;
WHEN OTHERS =>
report "Reach undefined state";
-- if it is active -> the error will be in compile time
END CASE;
END IF;
END PROCESS;
Boiler FSM Changes versus Counter (3/3)