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Leading at the edgeTECHNOLOGY AND MANUFACTURING DAY
TECHNOLOGY AND MANUFACTURING DAY
Moore’s lawleadershipMARK BOHRIntel Senior Fellow, Technology and Manufacturing GroupDirector, Process Architecture and Integration
TECHNOLOGY AND MANUFACTURING DAY
Intel Technology and Manufacturing Day 2017 occurs during Intel’s “Quiet Period,” before Intel announces its 2017 firstquarter financial and operating results. Therefore, presenters will not be addressing first quarter information duringthis year’s program.
Statements in this presentation that refer to forecasts, future plans and expectations are forward-looking statementsthat involve a number of risks and uncertainties. Words such as “anticipates,” “expects,” “intends,” “goals,” “plans,”“believes,” “seeks,” “estimates,” “continues,” “may,” “will,” “would,” “should,” “could,” and variations of such words andsimilar expressions are intended to identify such forward-looking statements. Statements that refer to or are based onprojections, uncertain events or assumptions also identify forward-looking statements. Such statements are based onmanagement’s expectations as of March 28, 2017, and involve many risks and uncertainties that could cause actualresults to differ materially from those expressed or implied in these forward-looking statements. Important factors thatcould cause actual results to differ materially from the company’s expectations are set forth in Intel’s earnings releasedated January 26, 2017, which is included as an exhibit to Intel’s Form 8-K furnished to the SEC on such date.Additional information regarding these and other factors that could affect Intel’s results is included in Intel’s SEC filings,including the company’s most recent reports on Forms 10-K, 10-Q and 8-K reports may be obtained by visiting ourInvestor Relations website at www.intc.com or the SEC’s website at www.sec.gov.
Disclosures
TECHNOLOGY AND MANUFACTURING DAY
Intel leads the industry in introducing innovations that enable scaling
Hyper scaling on Intel 14 nm and 10 nm provides better-than-normal scaling while continuing to reduce cost per transistor
Intel’s 14 nm technology has ~3 year lead over other “10 nm” technologies with similar logic transistor density
Intel’s 10 nm technology provides industry-leading logic transistor density using a quantitative density metric
Enhanced versions of 14 nm and 10 nm provide improved performance and extend the life of these technologies
Key messages
Moore’s Law is alive and well at Intel
Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
Intel innovation leadership
Intel leads the industry by at least 3 years in introducing major process innovations
Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm
Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20
Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
Intel innovation leadership
Intel leads the industry by at least 3 years in introducing major process innovations
Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm
Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20
>3 yearslater
StrainedSilicon
Strained Silicon
Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
Intel innovation leadership
Intel leads the industry by at least 3 years in introducing major process innovations
Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm
Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20
>3 yearslater
High-kMetal Gate
High-kMetal Gate
>3 yearslater
StrainedSilicon
Strained Silicon
Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
Intel innovation leadership
Intel leads the industry by at least 3 years in introducing major process innovations
Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm
Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20
>3 yearslater
High-kMetal Gate
High-kMetal Gate
SelfAlign Via
>3 yearslater
SelfAlign Via
>3 yearslater
StrainedSilicon
Strained Silicon
Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
Intel innovation leadership
Intel leads the industry by at least 3 years in introducing major process innovations
Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm
Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20
>3 yearslater
High-kMetal Gate
High-kMetal Gate
>3 yearslater
FinFETTransistor
FinFETTransistor
SelfAlign Via
>3 yearslater
SelfAlign Via
>3 yearslater
StrainedSilicon
Strained Silicon
Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
Intel innovation leadership
Intel leads the industry by at least 3 years in introducing major process innovations
Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm
Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20
>3 yearslater
High-kMetal Gate
High-kMetal Gate
>3 yearslater
FinFETTransistor
FinFETTransistor
SelfAlign Via
>3 yearslater
SelfAlign Via
>3 yearslater
StrainedSilicon
Strained Silicon
~3 yearslater
Hyper Scaling
Hyper Scaling
Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
Intel innovation leadership
Intel leads the industry by at least 3 years in introducing major process innovations
Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm
Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20
>3 yearslater
High-kMetal Gate
High-kMetal Gate
>3 yearslater
FinFETTransistor
FinFETTransistor
SelfAlign Via
>3 yearslater
SelfAlign Via
>3 yearslater
StrainedSilicon
Strained Silicon
~3 yearslater
Hyper Scaling
Hyper Scaling
Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm
Contact
Fin
Gate
??
HyperScaling
HyperScaling
Source: Intel. 10 nm is based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
Intel innovation leadership
Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm
Year ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18 ‘19 ‘20
>3 yearslater
High-kMetal Gate
High-kMetal Gate
>3 yearslater
FinFETTransistor
FinFETTransistor
Contact
Fin
Gate
??
HyperScaling
HyperScaling
SelfAlign Via
>3 yearslater
SelfAlign Via
>3 yearslater
StrainedSilicon
Strained Silicon
~3 yearslater
Hyper Scaling
Hyper Scaling
Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm
Intel developed all the major logic process innovations used by our industry over the past 15 years
Source: Intel. 10 nm is based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
Industry recognitions2008 SEMI Award for North America“For integration of strain-enhanced mobility techniquesfor CMOS transistors”
2012 SEMI Award for North America“For the first development, integration and introduction of a successful high-k dielectric and metal electrode gate stack for CMOS IC production”
2015 SEMI Award for North America“For implementation of bulk CMOS FinFET production”
2016 IEEE Corporate Innovation Award“For pioneering the use of high-k metal gate and tri-gate transistor technologies in high-volume manufacturing”
Other names and brands may be claimed as the property of others
TECHNOLOGY AND MANUFACTURING DAY
0.1
1
2007 2008 2009 2010 2011 2012 2013 2014
LogicArea
(relative)
HVM Wafer Start Date
45nm
22nm
32nm
.49x
.45x
Logic area scaling
Traditional logic area scaling was ~0.49x per generation using a “gate pitch x cell height” metric
Logic Cell Width
Logic Cell
Height
Gate Pitch
Logic Area Metric
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
Logic area scaling
… but “gate pitch x cell height” is not a comprehensive transistor density metric
Logic Cell Width
Logic Cell
Height
Gate Pitch
Logic Area Metric
0.1
1
2007 2008 2009 2010 2011 2012 2013 2014
LogicArea
(relative)
HVM Wafer Start Date
45nm
22nm
32nm
.49x
.45x
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
Logic Transistor density metric
Standard NAND+SFF metric is a more accurate estimate of logic transistor density
NAND2 Tr CountNAND2 Cell Area
Scan Flip Flop Tr CountScan Flip Flop Cell Area
0.6 x + 0.4 x = # Transistors / mm2
2-Input NAND Cell Complex Scan Flip-Flop Logic Cell
Cell Height
Cell Width
Cell Width
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
1
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Transistor Density
MTr / mm2
HVM Wafer Start Date
Intel
45nm
22nm
32nm 2.1x
2.3x
Logic Transistor density
Logic transistor density improvement was ~2.2x per generation using NAND+SFF metric
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
1
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Transistor Density
MTr / mm2
HVM Wafer Start Date
Intel
45nm
22nm
14nm
32nm 2.1x
2.3x
2.5x
Logic Transistor density
14 nm hyper scaling provided ~2.5x transistor density improvement
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
1
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Transistor Density
MTr / mm2
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
2.7x
2.5x
2.1x
2.3x
Logic Transistor density
10 nm hyper scaling provides ~2.7x transistor density improvement
Source: Intel. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
1
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Transistor Density
MTr / mm2
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
Logic Transistor density
Transistor density improvements continue at a rate of ~doubling every 2 years
Source: Intel. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
1
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Transistor Density
MTr / mm2
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
100.8
3.3
7.5
15.3
37.5
MTr / mm2
Logic Transistor density
Logic node names should be accompanied with logic transistor density
Source: Intel. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
1
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Transistor Density
MTr / mm2
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
45/40nm
14/16nm
28/32nm28nm
Others(measured)
20nm
Logic Transistor density
Other measured transistor densities using same NAND+SFF metric
Source: Amalgamation of analyst data and Intel analysis. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
1
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Transistor Density
MTr / mm2
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
45/40nm
14/16nm
28/32nm28nm
Others(measured)
20nm
Logic Transistor density
Rate of density improvement was slow on other 20/16/14 nm technologies
Source: Amalgamation of analyst data and Intel analysis. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
1
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Transistor Density
MTr / mm2
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
45/40nm
14/16nm
28/32nm28nm
Others(measured)
20nm
~1.3x
Logic Transistor density
Intel 14 nm has ~1.3x higher transistor density than other 20/16/14 nm
Source: Amalgamation of analyst data and Intel analysis. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
1
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Transistor Density
MTr / mm2
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
45/40nm
14/16nm
28/32nm28nm
Others(measured)
20nm
10nm(est.)
~3 years
Logic Transistor density
Other “10 nm” technologies will have density similar to Intel 14 nm, but ~3 years later
Source: Amalgamation of analyst data and Intel analysis. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
Logic Transistor density
Logic node names should be accompanied with logic transistor density
1
10
100
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Transistor Density
MTr / mm2
HVM Wafer Start Date
Intel
45nm
22nm
14nm
10nm
32nm
45/40nm
14/16nm
28/32nm28nm
Others(measured)
20nm
10nm(est.)
100.8
~50
MTr / mm2
Source: Amalgamation of analyst data and Intel analysis. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
Moore’s law is a law of economics
Twice the numberof transistors in
same space
Same circuitry in half the space
(Feature Neutral)
ORLOWER COST
MOREFUNCTIONALITY
( more transistors )
TECHNOLOGY AND MANUFACTURING DAY
Microprocessor die area scaling
Normal microprocessor die area scaling has been ~0.62x per generation
0.62x
Logic
SRAM
IO
100 mm2
Logic
SRAM
IO
100 mm2
Logic
SRAM
IO
100 mm2
Logic
SRAM
IO
100 mm2
Logic
SRAM
IO
0.62x0.62x
0.62xArea
100 mm2
62 mm2
38.4 mm2
23.8 mm214.8 mm2
45 nm 32 nm 22 nm 14 nm 10 nm
Source: Intel.
TECHNOLOGY AND MANUFACTURING DAY
Microprocessor die area scaling
Hyper scaling delivers 0.46-0.43x die area scaling on 14 nm and 10 nm
100 mm2
45 nm 32 nm 22 nm 14 nm 10 nm
62 mm2
17.7 mm27.6 mm2
0.62x
Logic
SRAM
IO
100 mm2
Logic
SRAM
IO
100 mm2
Logic
SRAM
IO
100 mm2
Logic
SRAM
IO
100 mm2
Logic
SRAM
IO
0.43x
0.46x0.62x
Area
38.4 mm2
Source: Intel.
TECHNOLOGY AND MANUFACTURING DAY
45 n
m
32 n
m
22 n
m
14 n
m
10 n
m
7 nm
$ / mm2
(normalized)
45 n
m
32 n
m
22 n
m
14 n
m
10 n
m
7 nm
$ / Transistor(normalized)
x =
45 n
m
32 n
m
22 n
m
14 n
m
10 n
m
7 nm
mm2 / Transistor(normalized)
Log
Scal
e
Log
Scal
e
Log
Scal
e
Cost per transistor
Normal scaling would have provided poor CPT improvements
Hypothetical
Hypothetical
Hypothetical
Source: Intel.
TECHNOLOGY AND MANUFACTURING DAY
45 n
m
32 n
m
22 n
m
14 n
m
10 n
m
7 nm
$ / mm2
(normalized)
45 n
m
32 n
m
22 n
m
14 n
m
10 n
m
7 nm
$ / Transistor(normalized)
x =
45 n
m
32 n
m
22 n
m
14 n
m
10 n
m
7 nm
mm2 / Transistor(normalized)
Log
Scal
e
Log
Scal
e
Log
Scal
e
Cost per transistor
Normal scaling + 450 mm wafers would have provided better CPT
Hypothetical
Hypothetical
Hypothetical450 mm
Source: Intel.
TECHNOLOGY AND MANUFACTURING DAY
45 n
m
32 n
m
22 n
m
14 n
m
10 n
m
7 nm
$ / mm2
(normalized)
45 n
m
32 n
m
22 n
m
14 n
m
10 n
m
7 nm
$ / Transistor(normalized)
x =
45 n
m
32 n
m
22 n
m
14 n
m
10 n
m
7 nm
mm2 / Transistor(normalized)
Log
Scal
e
Log
Scal
e
Log
Scal
e
Cost per transistor
Hyper scaling on Intel 14 nm and 10 nm provides lower CPT
Source: Intel.
TECHNOLOGY AND MANUFACTURING DAY
2007 2009 2011 2013 2015 2017 2019 2021
Tran
sist
orPe
rform
ance
(log
scal
e)
Process Readiness Date
45nm
22nm
14nm
10nm
32nm
HigherPerformance
2007 2009 2011 2013 2015 2017 2019 2021
Dyn
amic
Cap
acita
nce
(log
scal
e)
Process Readiness Date
45nm
22nm
14nm
10nm
32nm
LowerPower
Transistor performance and power
Scaled transistors continue to provide improved performance and lower power
Source: Intel. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
2007 2009 2011 2013 2015 2017 2019 2021
Tran
sist
orPe
rform
ance
(log
scal
e)
Process Readiness Date
45nm
22nm
14nm
10nm
32nm
HigherPerformance
14++
14+
2007 2009 2011 2013 2015 2017 2019 2021
Dyn
amic
Cap
acita
nce
(log
scal
e)
Process Readiness Date
45nm
22nm
14nm
10nm
32nm
LowerPower
14+ 14++
Technology enhancements
14 nm enhancements improve performance and extend technology life
Source: Intel. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
2007 2009 2011 2013 2015 2017 2019 2021
Tran
sist
orPe
rform
ance
(log
scal
e)
Process Readiness Date
45nm
22nm
14nm
10nm
32nm
10++
10+
HigherPerformance
14++
14+
2007 2009 2011 2013 2015 2017 2019 2021
Dyn
amic
Cap
acita
nce
(log
scal
e)
Process Readiness Date
45nm
22nm
14nm
10nm
32nm
10+ 10++LowerPower
14+ 14++
Technology enhancements
10 nm enhancements improve performance and extend technology life
Source: Intel. 2017-2020 are estimates based upon current expectations and available information.
TECHNOLOGY AND MANUFACTURING DAY
Derivative technologies
Multiple derivative options offered for each technology generation
CPU SoC
High Perf Transistors Yes Yes
Low Leakage Transistors - Yes
Analog/RF Transistors - Yes
HV I/O Transistors - Yes
High-Q Inductors - Yes
Precision Resistors Yes Yes
MIMCAP Yes Yes
Low Cost Dense High Perf
Interconnect Stack OptionsDevice Options
Source: Intel
TECHNOLOGY AND MANUFACTURING DAY
14 nm products
Wide range of 14 nm products in volume production on various derivative technologies
Mobile Mobile
ClientClient
Server FPGAServer
TECHNOLOGY AND MANUFACTURING DAY
Die 1 Die 2
Package Substrate
Die 2Die 1
Package Substrate
Die 1 Die 2
Package SubstrateSilicon Bridge
Heterogeneous Integration OptionsMulti-Chip
Package
Silicon Interposer
Embedded Multi-Die
Interconnect Bridge
Poor density of die-package connectionsPoor density of die-die interconnects
Good density of die-interposer connectionsGood density of die-die interconnectsHigher cost of large interposer + thru-silicon vias
Good density of die-bridge connectionsGood density of die-die interconnectsLow cost of small silicon bridges
EMIB technology provides high density, high bandwidth die-die interconnects
Interposer
TECHNOLOGY AND MANUFACTURING DAY
Embedded Multi-Die Interconnect Bridge
EMIB technology provides high density, high bandwidth die-die interconnects
Silicon Chips
Package Substrate
Silicon Bridge
Custom I/O circuits Custom I/O circuits
TECHNOLOGY AND MANUFACTURING DAY
Embedded Multi-Die Interconnect Bridge
Silicon Bridge
55 um pitch bumps130 um pitch
bumpsSilicon Die
TECHNOLOGY AND MANUFACTURING DAY
Embedded Multi-Die Interconnect Bridge
Silicon Bridge
55 um pitch bumps130 um pitch
bumpsSilicon Die
M1
M2
M3
PAD
TV1
V3
M4
V1
TECHNOLOGY AND MANUFACTURING DAY
Heterogeneous integration
EMIB enables dense and cost effective in-package heterogeneous integration
TECHNOLOGY AND MANUFACTURING DAY
Intel leads the industry in introducing innovations that enable scaling
Hyper scaling on Intel 14 nm and 10 nm provides better-than-normal scaling while continuing to reduce cost per transistor
Intel’s 14 nm technology has ~3 year lead over other “10 nm” technologies with similar logic transistor density
Intel’s 10 nm technology provides industry-leading logic transistor density using a quantitative density metric
Enhanced versions of 14 nm and 10 nm provide improved performance and extend the life of these technologies
Key messages
Moore’s Law is alive and well at IntelSource: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information.
Leading at the edgeTECHNOLOGY AND MANUFACTURING DAY