Technology For Realizing 3D Integration

By-Dipyaman Modak

What is 3D IC?

• It’s a system level integration architecture wherein multiple layers of active components are stacked and interconnected.

A vision of future 3D hyper-integration of infotech, nanotech and biotech.

Why?Heterogeneous Integration

Performance

Form Factor Cost Effective

Manufacturing Technologies

•MonolithicElectronic components and their connections (wiring) are built on a single semiconductor wafer, which is then diced into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or through-silicon vias.

• Wafer on Wafer

• Die on Wafer

• Die on Die

Wafer on WaferElectronic components are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D ICs.

The "through-silicon vias" (TSVs) pass through the silicon substrates between active layers or between an active layer and an external bond pad.

Die on Wafer-• Electronic components are built on two semiconductor wafers.

• One wafer is diced

• The singulated dies are aligned and bonded onto die sites of the second wafer.

• Thinning and TSV creation are performed either before or after bonding.

Die on Die-• Electronic components are built on multiple dies.

• Then, they are aligned and bonded.

• Thinning and TSV creation can be done before or after bonding.

+ Die-on-die, each component die can be tested first, so that one bad die does not ruin an entire stack.

+Each die in the 3D IC can be binned beforehand, so that they can be mixed and matched to optimize power consumption and performance.

3D Stacking Technology

There are basically three major technology platforms for 3D integration, based on the rudimentary infrastructure:

3D-SIP: • Packages with wire-bond die-stacks package-on-package.

• A system consists of different sub systems and in each of them can be integrated on a system in a package fashion .

Fully integrated low power rf radio, realized by 3D stacking of CSP packages, joining using micro bumps

• It consist of only two “Chip scale package” type devices

• The top one is integrated with the help of IMEC’s rf-MCM-D technology [7].

• The bottom CSP is double sided high density flip chip die

3D-WLP: Wafer-Level packaging infrastructure-• The 3D WLP is based on wafer level packaging infrastructure.

• The simplest way to realize 3D wafer level packaging are by face to face bonding using flip chip technique or by micro bump technique.

• The most common way is by TSV technology-

• Etching of a “blind” via hole in the Si-wafer.

• Dielectric isolation of the Si-hole with the help of CVD oxide or nitride passivation.

• Metallization of silicon holes.

• Back grinding of the wafer, exposing the Cu plug, finalizing the 3D via process.IMEC’s 3D-WLP process with Si through-hole electrical connections

3D-SIC:The 3D-SIC approach develops high density vertical interconnects through Si-foundry technologies. This type of 3D stacks can be divided in two classes-

• Firstly, wafer stacks having large circuit blocks “tiles” are interconnected in a 3D fashion. The 3D interconnects corresponds to intermediate BEOL on-chip interconnects. In this case 3D SIC is also considered as a “3D SOC”.

• Secondly, high density wafer stacks aims at connecting small circuits, logic gates and even transistors in a 3D fashion. Interconnects are done by local BEOL hierarchy and this device are true 3D-IC.

Conclusion

In my opinion, adding the third dimension to fabrication world, unwraps new opportunities for the design and fabrication. In near future it is expected that there will be mass production of 3D ICs like in the field of medical and logic applications. Once 3D applications is matured and manufacturing infrastructure such as ECAD tools, fabrication equipment , more ICs will be designed and comes to the market due to its low manufacturing cost, small form factor and low power consumption

References

• [1] Ji Fan and Chuan Seng Tan, Low Temperature Wafer-Level Metal Thermo-Compression Bonding Technology for 3D Integration.

• [2] Proc. of the I't and 2nd conf. on "3D Architectures for Semiconductor Integration and packaging", RTI. International, Burlingame, California, April 13-15, 2004 and Tempe, Arizona, June 13-15, 2005.

• [3] Beyne, E. (2006). 3D system integration technologies. Proceeding of 2006 International Symposium on VLSI Technology, Systems, and Applications, Hsinchu, IEEE, pp.19-27.

• [4] E.Beyne, "3D Interconnection and packaging: impending reality or still a dream?" proceedings of the IEEE International Solid-State Circuits Conference, ISSCC2004, 15-19 February 2004; San Francisco, CA, USA, IEEE, 2004, pp.138-145.

• [5] M. Karnezos. "3-D Packaging: Where All Technologies Come Together". IEEE/SEMI 29th International Electronics Manufacturing Technology Symposium, July 2004, pp. 64-67.

• [6] Tezzaron's Patented Technologies-“FaStack - Wafer stacking and die stacking technology with TSVs for 3D-IC devices”.

• [7] E Beyne, “Multilayer thin film technology as an enabling technology for system in package (SiP) and "above-IC" Processing", idem [7] pp.91-99.

• [8] E.Beyne, "Technologies for very high bandwidth electrical interconnects between next generation VLSI circuits", IEEE-IEDM 2001 Technical Digest, December 2-5, Washington, D.C., S23-p13, 2001.

• [9] J.H.McMahon et al., "Wafer bonding of damascene- patterned metal/adhesive redistribution layers for via first 3D Interconnect", Proc. of the 55t ECTC,, Orlando, Florida, May 31-June 3, 2005, pp. 332-336.

• [10] Jian-Qiang Lu, "3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems