ETLCE - A2 23/09/2009
© 2009 DDC 1
23/09/2009 - 1 TLCE - A2 - © 2009 DDC
Politecnico di TorinoICT School
Telecommunication Electronics
A2 – Transistor amplifiers
» Bias point and circuits, » Small signal models» Gain and bandwidth» Limits of linear analysis
ETLCE - A2 23/09/2009
© 2009 DDC 2
23/09/2009 - 2 TLCE - A2 - © 2009 DDC
Amplifiers
• Op Amp amplifiers– Previous courses
• Transistor amplifiers (lesson A2 and A3)– Reference circuit and design procedures– Linear model
– Nonlinear model» Distortion, harmonics, gain compression
• Lab 1: small signal analysis (linear model)
• Lab 2: large signal behaviour (nonlinear model)
• References:– Transistor circuits 1.1, 1.2
ETLCE - A2 23/09/2009
© 2009 DDC 3
23/09/2009 - 3 TLCE - A2 - © 2009 DDC
Amplifiers in positioning radio receiver
LNA:
Low Noise Amplifier
VGA: Variable Gain Amplifier
IF tunedamplifiers
ETLCE - A2 23/09/2009
© 2009 DDC 4
23/09/2009 - 4 TLCE - A2 - © 2009 DDC
GPS radio IC
LNA:
Low Noise Amplifier
Wide dynamic range, low distorsion
VGA: Variable Gain Amplifier
ETLCE - A2 23/09/2009
© 2009 DDC 5
23/09/2009 - 5 TLCE - A2 - © 2009 DDC
Amplifiers in radio structure
PA (power amplifier)
TX output amplifiers
- High efficiency, low distorsion
IF channel
LNA (low noise amplifier)
RX input amplifiers
- Low noise, wide dynamic
ETLCE - A2 23/09/2009
© 2009 DDC 6
23/09/2009 - 6 TLCE - A2 - © 2009 DDC
OpAmp–based Amplifers: where ?
Audio interface (mike and earphones)
IF channel amplifiers
Amplifiers and filtersfor A/D converters
ETLCE - A2 23/09/2009
© 2009 DDC 7
23/09/2009 - 7 TLCE - A2 - © 2009 DDC
Fully differential OpAmp
• Differential input AND differential output
– Double feedback loop
– Better balance
ETLCE - A2 23/09/2009
© 2009 DDC 8
23/09/2009 - 8 TLCE - A2 - © 2009 DDC
Transistor-based amplifiers: where ?
LNA (low noise amplifier)
RX input amplifiers:
- Low noise
- Wide dynamic range
PA (power amplifier)
TX output amplifier:
- High efficiency
- Low harmonic contents
ETLCE - A2 23/09/2009
© 2009 DDC 9
23/09/2009 - 9 TLCE - A2 - © 2009 DDC
Amplifiers or ….
• What matters in an amplifier– Gain
– Bandwidth – Linearity (no distorsion)– Noise (low)
• There is always some nonlinearity – Reduce, counteract
» Negative feedback, tuned circuits, …
– Used to build» VGA/dynamic compressor» Mixers» oscillators
ETLCE - A2 23/09/2009
© 2009 DDC 10
23/09/2009 - 10 TLCE - A2 - © 2009 DDC
Lesson A2: Amplifiers
• Types of amplifiers
• Transistor amplifiers– Basic circuit
– Linear transistor model– Biasing– Small signal analysis
– Frequency response
• Design of amplifiers– Specifications – Design sequence
– Lab experiment
ETLCE - A2 23/09/2009
© 2009 DDC 11
23/09/2009 - 11 TLCE - A2 - © 2009 DDC
Transistor models
• Small signal– BJT, MOS, MOS-FET
– Same linear model (gm or hybrid)
• Large signal: same method, different models– BJT: exponential large signal model (rather simple)– MOS: lin/log/quad large signal model (complex !)
– analytic model for BJT– euristic models for MOS
– Similar effects and countermeasures
ETLCE - A2 23/09/2009
© 2009 DDC 12
23/09/2009 - 12 TLCE - A2 - © 2009 DDC
Bulding the BJT amplifier
• Basic bias circuit– Ic depends on current gain
• Improved bias– Ic depends on temperature (Vbe)
• Feedback bias– R1 to Vc
• Final bias– Stable Ic– Gain depend on bias
VAL
Vi
R1 Rc
C1
VAL
Vi
R1 Rc
Re
C1
VAL
Vi
R1
R2
Rc
Re2
C1
ETLCE - A2 23/09/2009
© 2009 DDC 13
23/09/2009 - 13 TLCE - A2 - © 2009 DDC
BJT reference circuit
• Common Emitter circuit
RE1
RE2
ETLCE - A2 23/09/2009
© 2009 DDC 14
23/09/2009 - 14 TLCE - A2 - © 2009 DDC
Amplifier features and analysis
• AC amplifier: BJT Common Emitter circuit
• Input and output AC coupling: C1, C4
• Emitter feedback– DC: stabilize the bias point– AC control the gain
• Analysis or design:– Bias point– AC passband gain (linear model)– Cutoff frequency
– Nonlinear model analysis
ETLCE - A2 23/09/2009
© 2009 DDC 15
23/09/2009 - 15 TLCE - A2 - © 2009 DDC
Analysis of BJT circuit: step 2
• CE amplifier with bipolar transistor (BJT)– Find bias point:
(IC, VCE)
– The bias pointmust be in the active region:
VCE > 0,2 VVCE
ETLCE - A2 23/09/2009
© 2009 DDC 16
23/09/2009 - 16 TLCE - A2 - © 2009 DDC
Analysis of BJT circuit: step 3
• CE amplifier with bipolar transistor (BJT)– Find bias point:
(IC, VCE)
– The bias pointmust be in the active region:
VCE > 0,2 V
– Compute small signalparametares:
hie, hfe, gm...
hie, hfe
ETLCE - A2 23/09/2009
© 2009 DDC 17
23/09/2009 - 17 TLCE - A2 - © 2009 DDC
BJT (simplified) models
• Simplified model for bias point analysis (active area)
• Simplified model for small signal analysis, CE configuration.Parametershfe iB or gm vBE
hie = VT * hfe/IC
gm = IC/VT
B C
E
IB β IB
gm vBE
vBE
B C
E
ETLCE - A2 23/09/2009
© 2009 DDC 18
23/09/2009 - 18 TLCE - A2 - © 2009 DDC
Bias point analysis
• DC bias point– Small signal parameters depend on IC and (to a lesser
extent) on VCE solve bias point first
– IC ≈ IE is fixed by Base-Emitter mesh– VCE is related with Collector-Emitter mesh
• Step 1: compute IC– Equation on BE mesh
– First approximation: IB = 0 (hFE →∞)
• Step 2: check VCE value; – Equation on CE mesh– if > 0,2 V active area
ETLCE - A2 23/09/2009
© 2009 DDC 19
23/09/2009 - 19 TLCE - A2 - © 2009 DDC
BE net
• Ic depends fromthese devices
– Ic depends only from Base-Emitter mesh
– Vcc, R1, R2are mapped to a unique mesh, with equivalent Theveninparameters
VBB, RB
ETLCE - A2 23/09/2009
© 2009 DDC 20
23/09/2009 - 20 TLCE - A2 - © 2009 DDC
BE mesh
• BE equivalent circuit
VBB
ETLCE - A2 23/09/2009
© 2009 DDC 21
23/09/2009 - 21 TLCE - A2 - © 2009 DDC
Vce
CE net
• Vce depends fromdevices in the CEmesh
– Vce depends from Ic and devices at the Collectornode
– Vce =Vcc-IcRc-IeRe
ETLCE - A2 23/09/2009
© 2009 DDC 22
23/09/2009 - 22 TLCE - A2 - © 2009 DDC
Design choices
• If hfe is large, – IB = (VBB – VBE)/RB
• Design variables (for a given Ic)– VBB, RB/VB
• Large VBB
– Good stability vs ∆VBE(mainly due to temperature)
– Reduced output dynamic range (VCE)
• Small RB
– Good stability vs ∆β (mainly due to parameters spreading)– High power consumption (RB = R1//R2)
ETLCE - A2 23/09/2009
© 2009 DDC 23
23/09/2009 - 23 TLCE - A2 - © 2009 DDC
R1 120 kΩR2 82 kΩRe1 330 ΩRe2 12 kΩRc 10 kΩ
Vcc 12 Vhfe 100
Vbb = Rb =
Ie =Vce = hie = gm =
VccR1
R2
Rc
Re2
Re1
C1
C3
C2
Q1I1
Ie
Example: bias point, SS parameters
ETLCE - A2 23/09/2009
© 2009 DDC 24
23/09/2009 - 24 TLCE - A2 - © 2009 DDC
R1 120 kΩR2 82 kΩRe1 330 ΩRe2 12 kΩRc 10 kΩ
Vcc 12 Vhfe 100
Vbb = 12 * 82 / 202 = 4,9 V Rb = 48,7 kΩ
Ie = 4,3 / (12,33 + 48,7/100) = 0,335 mAVce = 4,35 V hie = 7,76 kΩ gm = 12,88 mA/V
VccR1
R2
Rc
Re2
Re1
C1
C3
C2
Q1I1
Ie
Example: bias point, SS parameters
ETLCE - A2 23/09/2009
© 2009 DDC 25
23/09/2009 - 25 TLCE - A2 - © 2009 DDC
MOS reference circuit
• CommonSource
RE1
RE2
G
D
S
ETLCE - A2 23/09/2009
© 2009 DDC 26
23/09/2009 - 26 TLCE - A2 - © 2009 DDC
Lesson A2: Amplifiers
• Types of amplifiers
• Transistor amplifiers– Basic circuit
– Linear transistor model– Biasing– Small signal analysis
– Frequency response
• Design of amplifiers– Specifications – Design sequence
– Lab experiment
ETLCE - A2 23/09/2009
© 2009 DDC 27
23/09/2009 - 27 TLCE - A2 - © 2009 DDC
BJT circuit: small signal analysis
• Parts related with in-band gain (C3 open, C1, C2, C4 shorted)
• Reminders – In signal analysis
Vcc = 0
– R1, R2 are connected as parallel resistances to Vi
ETLCE - A2 23/09/2009
© 2009 DDC 28
23/09/2009 - 28 TLCE - A2 - © 2009 DDC
• Compute the gain using the linear model
vO = iC ZC; iC = iB hfe; vi = iB hie + iB(1+hfe) ZE
Vo
ZC
ViR1//R2
IB hfeIB
hie
ZE
Gain analysis equivalent circuit
ETLCE - A2 23/09/2009
© 2009 DDC 29
23/09/2009 - 29 TLCE - A2 - © 2009 DDC
Results with linear model
• Gain with linear model
• If hfe >> 1 – hie becomes negligible with respect to ZE (hfe+1)
(hfe+1)
ETLCE - A2 23/09/2009
© 2009 DDC 30
23/09/2009 - 30 TLCE - A2 - © 2009 DDC
hie = 8,96khfe = 100gm = 12,9 mA/V
Rc 12 kΩRe1 330 ΩRL 10 kΩ
Total load on the Collector: Rc//RL
Av = - (12k//10k)*100 / (8,96k + 330*100) = -13
Vo
RL
ViR1//R2
Ib
Rc
Re1
hfe Ib
hie
Example: gain with linear model 1
ETLCE - A2 23/09/2009
© 2009 DDC 31
23/09/2009 - 31 TLCE - A2 - © 2009 DDC
hie = 8,96khfe = 100gm = 12,9 mA/V
Rc 12 kΩRe1 330 ΩRL 10 kΩ
Total load on the Collector: Rc//RL
Av =
Vo
RL
ViR1//R2
Vbe
Rc
Re1
gm Vbe
hie
Example: gain with linear model 2
ETLCE - A2 23/09/2009
© 2009 DDC 32
23/09/2009 - 32 TLCE - A2 - © 2009 DDC
hie = 8,96khfe = 100gm = 12,9 mA/V
Rc 12 kΩRe1 330 ΩRL 10 kΩ
Ri = ?
Ro = ?
Vo
RL
ViR1//R2
Ib
Rc
Re1
hfe Ib
hie
Example: Ri and Ro
ETLCE - A2 23/09/2009
© 2009 DDC 33
23/09/2009 - 33 TLCE - A2 - © 2009 DDC
Frequency response
• Wideband AC amplifier– Emitter/source feedback
» stabilize DC bias point and in-band AC gain |AV| ≅ ZC/ZE
• Lower band limit:– interstage series coupling capacitance
– ZE frequency behaviour – transformer coupling (if any)
• Higher band limit– parallel capacitors towards ground
» designed capacitors» wiring parasitic» active device parasitic
ETLCE - A2 23/09/2009
© 2009 DDC 34
23/09/2009 - 34 TLCE - A2 - © 2009 DDC
Wideband AC amplifier
f(Hz)
|Vu/Vi| (dB)
Low cutofffrequency(C1, C2, Ce)
High cutofffrequency(C3, Cp1, Cp2)
Band pass
1 10 100
ETLCE - A2 23/09/2009
© 2009 DDC 35
23/09/2009 - 35 TLCE - A2 - © 2009 DDC
High Frequency: L and C parasitics
• Output Capacitance (load)– insert isolation stage (Common Collector/Drain)
• PCB parasitic L and C– Use SMD devices– Careful PCB design
• Active device parasitic (CBC) – multiplied by Miller effect– use HF devices with low CBC (GaAs, SiGe, ..)
– proper circuit configuration (Common Base, cascode)
ETLCE - A2 23/09/2009
© 2009 DDC 36
23/09/2009 - 36 TLCE - A2 - © 2009 DDC
Cp1: Base-Collector parasitic (Cbc)C3: designed to set high cutoff frequency
Vcc
Vi
R1
R2
Rc
Re2
Re1
C1
C3
C2
Q1
Vo
RL
C4
Ie
Cp1 Cp2
Parasitic capacitances
ETLCE - A2 23/09/2009
© 2009 DDC 37
23/09/2009 - 37 TLCE - A2 - © 2009 DDC
Miller effect
• Parasitic Base-Collector capacitance (CBC) is connected between to nodes with inverting gain –A
– Corrent Icond flowing in CBC:
– Icond = jωCBC (VB–VC) = jωCBC (VB+AVB) = jωCBC (A+1) VB
(multiplied by Miller effect)
– Admittance multiplied by (gain +1)
• Actual equivalent capacitance at Base node:– Cactual = CBC * (A+1)
• This capacitance limits the high frequency response
• Need for Miller free circuit configurations
ETLCE - A2 23/09/2009
© 2009 DDC 38
23/09/2009 - 38 TLCE - A2 - © 2009 DDC
Other circuit configurations: CC
• Common Collector / Common Drain– high Zi
– low Zo– No Miller effect (Av ≈ 1)– Current gain
• Good for– Load separation
– Increasing Zi– Lowering Zo
Vcc
ViRe Vo
Q1
Va
ETLCE - A2 23/09/2009
© 2009 DDC 39
23/09/2009 - 39 TLCE - A2 - © 2009 DDC
Other circuit configurations: CB
• Common Base / Common Gate– low Zi, high Zu
– CBC connected to GND:No Miller effect
– Low Zi
– Low Zo– Voltage gain
• combined with CEin the cascode stage
Vcc
Vi
Rc
Vo
Q2
ETLCE - A2 23/09/2009
© 2009 DDC 40
23/09/2009 - 40 TLCE - A2 - © 2009 DDC
Cascode amplifier
Only basic circuit, no bias network
Vi VaQ1: CE stage, Low Zc low V gainGood current gain- Low ∆Vce- Low Miller effect
Va VuQ2: CB stageGood voltage gain- No Miller effect
Vcc
Vi
Common Base
Rc
Q2
VuRL
Q1
CommonEmitter
Va
ETLCE - A2 23/09/2009
© 2009 DDC 41
23/09/2009 - 41 TLCE - A2 - © 2009 DDC
Cascode amplifier
• Common Base stage (CB)– CBC parasitic towards ground
– no Miller effect (C multiplier)– provides voltage gain
• Common Emitter output to low-Z load– small voltage dynamic
– provides current gain– minimum effect of CBC parasitic capacitance
• Overall result– higher gain at high frequency
ETLCE - A2 23/09/2009
© 2009 DDC 42
23/09/2009 - 42 TLCE - A2 - © 2009 DDC
Lesson A2: Amplifiers
• Types of amplifiers
• Transistor amplifiers– Basic circuit
– Linear transistor model– Biasing– Small signal analysis
– Frequency response
• Design of amplifiers– Specifications – Design sequence
– Lab experiment
ETLCE - A2 23/09/2009
© 2009 DDC 43
23/09/2009 - 43 TLCE - A2 - © 2009 DDC
Lab 1 and lab 2
• Design an amplifier from the provided specs– A real design:
» Multiple solutions» Some specs are implicit» Devices have poorly defined parameters
• Simulate, build, measure– Homework: design, simulation– In the lab: build, measure, debug
• Compare specs/simulation/measurements– Linear model lab 1– Nonlinear model lab 2
ETLCE - A2 23/09/2009
© 2009 DDC 44
23/09/2009 - 44 TLCE - A2 - © 2009 DDC
Amplifier design specs (2009)
• Single-Transistor Amplifier with:– Voltage gain |Vu/Vi| = 18 (nominal)
– Bandwidth -3 dB from 100 Hz to 40 kHz (minimum)– Output dynamic at least 4 Vpp on 10 kΩ load (or higher)– Supply voltage 15 V (nominal)
– 2N2222A Transistor
• All feature within +/-10%, at ambient temperature – Gain and output dynamic at band center
• References:– Text: design procedure: Cap 1, 1.P1
– Lab procedures: Cap 1, 1.L1– web guides: lab 1
ETLCE - A2 23/09/2009
© 2009 DDC 45
23/09/2009 - 45 TLCE - A2 - © 2009 DDC
Design sequence
• Select the circuit: CE with Ze, bias network Vb/Re
• Choose a no-load dynamic, or Ve, or Rc– Stabilty/power/dynamic tradeoff
• Compute Rc, or no-load dynamic , or Ve
• Compute Ic
• Design bias network to get Ic:– R1, R2, Re1+Re2
• Computer Re1 from gain specs
• Get C1, C2, C3, C4 from frequency behaviour specs.
ETLCE - A2 23/09/2009
© 2009 DDC 46
23/09/2009 - 46 TLCE - A2 - © 2009 DDC
Checks and measurements
• Passive devices (R and C) available in normalized values
– Know what they are (E12, E24, …)
– Only E12 values available in the lab– From computed to normalized values
• The transfer function is modified
• Component tolerances expand the Bode plot (a line) to a somewhat wide band
– Specs must lie within the strip
• Compare measurements with allowed variations of Bode plot
ETLCE - A2 23/09/2009
© 2009 DDC 47
23/09/2009 - 47 TLCE - A2 - © 2009 DDC
Theory and practice
f(Hz)
|Vu/Vi| (dB)
1 10 100 1k
Design specification
Design band, takinginto account deviceparameters tolerances
Measured values(with errors)
ETLCE - A2 23/09/2009
© 2009 DDC 48
23/09/2009 - 48 TLCE - A2 - © 2009 DDC
Lesson A2: final questions
• Which different types of amplifiers can be found in a radio system?
• Write an approximate expression for the voltage gain of a CE amplifier.
• Which elements limit the bandwidth of amplifiers?
• Which are the best configurations for high bandwidth amplifiers?
• List the specifications for an amplifier (what you must know to selct an amplifier from a catalogue)
• Define the design procedure for a single transistor amplifier
• Describe the lab procedures to measure the frequency response on an amplifier.
ETLCE - A2 23/09/2009
© 2009 DDC 49
23/09/2009 - 49 TLCE - A2 - © 2009 DDC
Next lesson (A3)
• How to evaluate the effects of nonlinearity • How to reduce the nonlinearity effects
– Feedback
– Tuned circuits
• How to exploit nonlinearity– Exploit harmonics– Exploit gain changes
• Lab 2: – Large signal behaviour (nonlinear)
• Text reference:– Narrowband and tuned amplifiers: 1.2.3
