RESOURCE PERSONS Eminent Faculty members and researchers from the premier Institutions such as IITs/NITs/IIITs and industry are invited to deliver the expert lectures on Modelling and simulation of Advanced Semiconductor Devices and VLSI circuits

It is a TEQUIP-III sponsored short term course. Number of seats are limited and participants will be

entertain on first come first serve basis.” Note: No FEE will be charged for attending the course.

ACCOMODATION AND FOOD

Fooding and lodging will be provided by the Institute for participants.

Patron

Prof. M.P.S Chauhan, Director, GBPIET Pauri-Garhwal

Convener Prof. Y. Singh Head ECED

TEQIP –III Coordinator Dr. M. K. Panda Coordinators Dr. Balraj Singh Dr. R.B.Yadav

Co-Coordinators Mr Vinay Mohan Kotwal

Mr. Agya Ram Verma Mr. Tripuresh Joshi

Mr. Sandeep Kumar Mr Rohit Negi

Mr Ajay Kumar

TEQIP-III Sponsored ONE WEEK Short Term Course

on Modeling and Simulation of Advanced

Semiconductor Devices & VLSI Circuits

25-29 June, 2018 Venue:

Department of Electronics and Communication Engineering G. B. Pant Institute of Engineering &Technology, Pauri-Garhwal –246194, Uttarakhand, India Website:-www.gbpec.ac.in

Ph: 09457166920

IMPORTANT DATES Receipt of registration Form 20/06/2018

(By Email)

Intimation to the selected participants: 21/06/2018 (By Email)

ELIGIBILITY & FEE People from industry, faculty from academic institutions & Universities and Ph.D. / PG students of, Electrical, Electronics, etc. are eligible to participate in this short term course.

R E G I S T R A T I O N F O R M OneWeekShorttermcourse

On Modeling and Simulation of Advanced

Semiconductor Devices & VLSI Circuits 25-29 June , 2018 Registration Form

(may use Xerox or typed copy) Full Name: ______________________ Designation: _____________________ Age and Sex: ___ ____ Highest Qualification:_______________ Name of the Institute/College/University: ________________________________ Experience (in years):_______________ Address for communication:__________ _________________________________ Tel:- _______ Mobile:___________ Email: ___________________________ Accommodation required: Yes/No _____ Place: ________________ Date:________________ Applicant Sign Sign and Seal of Head of the Dept./Institute /Univ

Address for communication: Dr. Balraj Singh Dept. of Electronics & Communication Engineering G.B.Pant Institute of Engineering & Technology Ghurdauri Dist. Pauri- Garhwal- 246194 (U.K.) Email: balraj.bits@gmail.com Mob 9457166920/ 07895664758

OBJECTIVE OF COURSE Today there is almost no area of technical endeavor that is not im-pacted in some way by the advance devices. To teach the basics of how modern CMOS devices are designed for better power-performance compared to previous generation when simple geo-metric shrinking no longer works. This will be useful for both de-signers and technologists who want to work on advanced nodes as there is a lot of design-technology interaction needed for a success-ful tape This course would bring the people from academia and industry to a common platform to disseminate the specific body of knowledge about the origins and future areas and applications of this technolo-gy. COURSE CONTENTS Topics of interest include, but are not limited to, the followings:

History of Si technology. Review of CMOS scaling. Problems with traditional geometric scaling. Mobility enhancement techniques.

Gate oxide scaling trend. Urgency to switch gate dielectric mate-rial. High k material selection.

Multi-gate transistors. Ways of realization. Fabrication issues and integration challenges

Ultra shallow junctions. Dopant activation methods. Reduction of parasitic RC

Compact modeling process Analog and Digital benchmarking of models. Layout dependent effects. Test structures used for char-acterization

Variations and how it can affect scaling

ABOUT THE DEPARTMENT

The Department of Electronics & Communication Engineering is proud to be first department of the institute established in 1991 to offer Bachelor’s degree in Electronics & Communica-tion Engineering with initial intake of 20 students. Presently, B. Tech. degree program has an intake of 60 students. The Depart-ment started Master’s degree program in Digital Signal Pro-cessing in 2005 with intake of 10 students. The PhD program has been offered since 2013. The department, since its incep-tion, has kept itself well abreast with the ever changing de-mands of the industry and the technological developments.The laboratories are modernized to reflect the rapid changes in tech-nology. With excellent labs and classrooms facilities, challeng-ing and interesting course-work, integrating hands-on practical and research experience are motivating faculty and students for new innovations. Such technological strengths and pollution free peaceful environment of the Shivalik range of Himaliya, has provided unmatched opportunities for research, education, and service to society.

OBJECTIVE OF COURSE Today there is almost no area of technical endeavor that is not im-pacted in some way by the advance devices. To teach the basics of how modern CMOS devices are designed for better power-performance compared to previous generation when simple geo-metric shrinking no longer works. This will be useful for both de-signers and technologists who want to work on advanced nodes as there is a lot of design-technology interaction needed for a success-ful tape This course would bring the people from academia and industry to a common platform to disseminate the specific body of knowledge about the origins and future areas and applications of this technolo-gy. COURSE CONTENTS Topics of interest include, but are not limited to, the followings:

History of Si technology. Review of CMOS scaling. Mobility enhancement techniques. Gate oxide scaling trend. Urgency to switch gate dielectric materi-al. High k material selection. Multi-gate transistors. Ways of realization. Fabrication issues and integration challenges Ultra shallow junctions. Dopant activation methods. Reduc-tion of parasitic RC Compact modeling process Analog and Digital benchmark-ing of models. Layout dependent effects. Test structures used for characterization Variations and how it can affect scaling

OBJECTIVE OF COURSE Today there is almost no area of technical endeavor that is not impacted in some way by the advance devices. To teach the ba-sics of how modern CMOS devices are designed for better pow-er-performance compared to previous generation when simple geometric shrinking no longer works. This will be useful for both designers and technologists who want to work on advanced nodes as there is a lot of design-technology interaction needed for a suc-cessful tape This course would bring the people from academia and industry to a common platform to disseminate the specific body of knowledge about the origins and future areas and applications of this technology. COURSE CONTENTS Topics of interest include, but are not limited to, the followings:

History of Si technology. Review of CMOS scaling. Mobility enhancement techniques. Gate oxide scaling trend. Urgency to switch gate dielectric mate-rial. High k material selection. Multi-gate transistors. Ways of realization. Fabrication is-sues and integration challenges Ultra shallow junctions. Dopant activation methods. Reduc-tion of parasitic RC Compact modeling process Analog and Digital benchmark-ing of models. Layout dependent effects. Test structures used for characterization Variations and how it can affect scaling

OBJECTIVE OF COURSE Today there is almost no area of technical endeavour that is not im-pacted in some way by the advance semiconductor devices. To teach the basics of how modern semiconductor devices are designed for better power-performance compared to previous generation when simple geometric shrinking no longer works. This will be useful for both designers and technologists who want to work on advanced technology nodes as there is a lot of design-technology interaction needed for a successful tape This course would bring the people from academia and industry to a common platform to disseminate the specific body of knowledge about the origins and future areas and applications of this technolo-gy. COURSE CONTENTS Topics of interest include, but are not limited to, the followings:

History of Si technology and review of semiconductor devices.

Physics and operation of MOSFETs

Scaling and Moore's Law

International technology roadmap for semiconductors

Multi-gate transistors.

Advanced MOS Devices (Tunnel FETs, Junctionless FETs )

TCAD simulation : Theory and demonstration.

Modelling of advance semiconductor devices.

Analog/Digital Circuit Design : Theory and simulation

G. B. PANT INSTITUTE OF ENGINEERING & TECHNOLOGY ,GHURDAURI DIST. PAURI- GARHWAL (U.K.) Govind Ballabh Pant Institute of Engineering & Tech-nology, Pauri (Garhwal) is an Engineering Institute established by the State Government in 1989 for im-parting Engineering Education and promoting techno-logical environment of Garhwal region, the state and country. It started its first academic session from 1991-92. The institute aims at shaping engineers, whose number can be at par with their counter parts anywhere in the country. Our students have gone on to make a mark for themselves in top notch companies in India & abroad, while other have persuaded academics in re-puted Institutes and Universities in India, America & other countries. This institute is an Autonomous Insti-tute of the Government of Uttarakhand affiliated to the Uttarakhand Technical University, Dehradun. LOCATION AND HOW TO REACH G.B.P.I.E.T, PAURI The insitute is located in hilly terrain of Garhwal Him-alayas at an altitude of about 1650 meters providing excellent panorama of natural beauty. Pauri is well connected through roads with nearest railway stations such as Dehradun. The campus is a sprawling over 169 acres of land with surrounded green forest. The insti-tute is situated near village Ghurdauri, about 13 Km from Pauri city on Pauri-Devprayag road in district of Pauri- Garhwal. GBPIET Pauri is about 110 km from Rishikesh/Kotdwar and is well connected by roads