Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Test and Test Equipment December 2010Makuhari Meese, Japan

Roger Barth

Test and Test Equipment – 2010 December Conference – Makuhari, Japan2

2010 Test TeamAkitoshi NishimuraAmit MajumdarAnne GattikerAtul GoelBill PriceBurnie WestCalvin CheungChris Portelli-HaleDave ArmstrongDennis ContiErik VolkerinkFrancois-Fabien FerhaniFrank PoehlHirofumi TsuboshitaHiroki IkedaHisao Horibe

Sanjiv TanejaSatoru TakedaSejang OhShawn FetterolfShoji IwasakiStefan EichenbergerSteve ComenSteve TildenSteven SlupskyTakairo NagataTakuya KobayashiTetsuo TadaUlrich SchoettmerWendy ChenYasuo SatoYervant ZorianYi Cai

Jerry McbrideJody Van HornKazumi HatayamaKen LanierKen TaokaKen-ichi AnzouKhushru ChhorMasaaki NambaMasahiro KanaseMichio MaekawaMike BienekMike Peng LiMike RodgersPaul RoddyPeter MaxwellPhil NighPrasad MantriRene SegersRob AitkenRoger Barth

Test and Test Equipment – 2010 December Conference – Makuhari, Japan

2009 Changes• DFT

– Test data compression and test time potential solutions identified– Major rewrite completed of the Design Chapter DFT section

• Test Cost– Test cost survey completed that quantifies industry view– Test parallelism dependency by device type modified based on I/O count

• Adaptive Test– New chapter section shows necessity for adaptive test to lower cost

• Prober– Complete redo of prober table to address parallelism and power

• Probecard– LCD display driver probe added as driver

• Handler– Added 10-50 Watt handler category

• Test Sockets– Socket BW limitations on current sockets– New future contacting solutions are required

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

2010 DriversUnchanged

Revised

New

Drop

• Device trends– Increasing device interface bandwidth and data rates– Increasing device integration (SoC, SiP, MCP, 3D packaging)– Integration of emerging and non-digital CMOS technologies– Device characteristics beyond the deterministic stimulus/response

model– Fault Tolerant architectures and protocols– 3 Dimensional silicon - multi-die and Multi-layer– Multiple Power modes and Multiple time domains– Complex package electrical and mechanical characteristics

• Test process complexity– Adaptive test and Feedback data– Concurrent test within a DUT– Maintaining unit level test traceability– Device customization / configuration during the test process– “Distributed test” to maintain cost scaling

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Drivers

• Economic Scaling of Test– Physical limits of packaged test parallelism

– Test data volume

– Managing interface hardware and (test) socket costs

– Multiple Insertions and System test

– Effective limit for speed difference of HVM ATE versus DUT

– Trade-off between the cost of test and the cost of quality

Unchanged

Revised

New

Drop

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

2010 Difficult Challenges

• Test for yield learning – Critically essential for fab process and device learning below optical device

dimensions

• Detecting Systemic Defects – Testing for local non-uniformities, not just hard defects– Detecting symptoms and effects of line width variations, finite dopant

distributions, systemic process defects

• Screening for reliability– Effectiveness and Implementation of burn-in, IDDQ, and Vstress testing– Detection of erratic, non deterministic, and intermittent device behavior

Unchanged

Revised

New

Drop

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

2010 Difficult Challenges

• Potential yield losses– Tester inaccuracies (timing, voltage, current, temperature control, etc)

– Over testing (e.g., delay faults on non-functional paths)

– Mechanical damage during the testing process

– Defects in test-only circuitry or spec failures in a test mode e.g., BIST, power, noise

– Some IDDQ-only failures

– Faulty repairs of normally repairable circuits

– Decisions made on overly aggressive statistical post-processing

Unchanged

Revised

New

Drop

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Test Cost Components

8

No 2010 Changes

2011 update planned

Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Test Cost Survey

• 2009 Survey to determine key factors & metrics

Test Cost Metrics

Cost per unitPercent of total Product CostCost per secondCost per megabit (memory)

Major Test Cost Drivers

ATE capital Interface hardwareTest program developmentTest Time and Coverage

Current Methodsof controlling cost

Test ParallelismReduced Pin interfacesStructural Test & ScanDFT and BISTConcurrent test

Metrics Not used

Cost per transistorCapital expenditures

Future Methods of controlling cost

Wafer-level at-speed testingAdvanced embedded instrumentsAdaptive Test New contacting technologiesBuild-in Fault Tolerance

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No 2010 Changes

2011 update planned

Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Adaptive Test

Modify testing based on analysis of previous results

Real-time

Near-time

Off-line

BenefitsHigher Quality

Fast Test Time Reduction

Lower cost

Fast yield learning

Requires data infrastructureDatabase

Analysis tools Confidence

Implementation is evolvingMultiple learning steps

Delaying won’t ease task

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Test Parallelism Update

• Soc, Low Performance Logic, commodity DRAM and Commodity Flash unchanged

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

SoC Updates

• Fault models pulled in Bridging faults to 2011• Full ATE standardized interface delayed from 2013 to 2015• DFT based defect analysis has slightly extended life

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Logic Update

• Changes driven by ORTC and Design TWG updates

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Memory Update

• NAND Density update driven by ORTC change• I/O width & Channels dropped

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

RF Update

• Increase in short term Carrier Frequency for 2010• Limited need for 12 GHz requirements…• 20GHz appears to be small volume as compared to other devices…

may be lack of developed instrumentation• Target is now 60+ GHz (personal networks and SR radar)

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Probing Technology Update

• 2011 memory roadmap will separate DRAM and Flash in table

• Low contact force probing process requirement added to roadmap

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

3D Devices

Multiple die systemSub-systems designed to operate and be

assembled togetherProcess optimized for contents of each die

Logic, DRAM, NVM, Analog

Connection by potentially 1000’s of TSVs (Thru Silicon Via’s)

Design, Interconnect, Assembly and Test, PIDS and FEP problem

DFT RequirementsTestability of each dieVias cannot be probed due to ESD issuesN+ die test methodology a possibility as die

added, not recommendedFinal 3D Packaged test

void

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

TSV Test Strategy

• Strong Recommendations– Can’t (and don’t) touch the TSVs.

• Alternative test pads with ESD protection are ok (analog, power, digital)• Use Boundary scan test for access

– Design independently testable die• Cannot require resources from other die for test• Need not operate in mission mode

– Design low resistance TSVs – TSV geometry and parametrics are not be the critical technology limiter

• Needs– Thermal considerations needed for scan after stack – Optimal functional / performance / system test– Possible benefit to self Speed Test (SST) thru TSV loop (post stack)

• Trends– System test / validation much more important in the future with TSVs. The

die stack is a system.

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New for 2010

Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Test Time Reduction Potential Solutions

• Required test time reduction is driven by SoC• Assumes increasing design complexity and transistor count will

not increase test time

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

DFT Compression Potential Solutions

• Development is necessary to get very high levels of data compression

• Demonstrated techniques are just approaching 1000x

• 100k data compression necessary out in time…no clear path yet!

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

High Speed Interfaces

Bit bandwidth increasing…

Physical limit?

Test limit?

Test Sockets are not able to support

controlled impedance contacts at >15 GT/s

Limit?

Jitter Test Critical for HS

Interfaces

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Summary of 2010 table (trend) Changes

• Major update of Device Trends and Challenges

• Minor adjustments to tables– Test parallelism

– SoC

– Logic (ORTC driven)

– Memory (ORTC driven)

– RF

– Probing Technology

• Refinement of TSV testing strategy

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

2011 Plans

• Further definition of 3D Silicon test and DFT requirements

• Investigate potential methods for data volume reduction

• Probing and Contacting of high speed Digital and Analog

• Probing of very thin wafers

• Die level tracking proposal

• Cost model update

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Backup

Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Test Topics (Chapter Sections)

• Key Drivers, Difficult Challenges, Opportunities

• Test for Yield Learning

• Cost of Test

• Adaptive Test

• DFT

• SoC and SiP

• Logic

• Memory – DRAM, NOR, NAND, Embedded

• Analog, RF and Mixed Signal

• Reliability Technology Burn-in

• Mechanical: Handlers and Probers

• Interface: Probecards and Test Sockets

• Specialty Devices – MEMS, Image Sensors, Accelerometers

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

SoC – Consumer Logic

> 1000 cores by 2020MPU / logicMemoryAnalog / RFHS serial

Per core DFT SoC test challenges

Management of per core DFTStandardization of core “wrappers”

IEEE 1500 core testIEEE P1687 JTAG chip-test

High Data Compression (>100)

FLASH

RAM

HS Serial

MPU

MPU

MPU

MPU

Analog

I/O and Logic

DSP

RF

Am

ou

nt

Of

DF

T

SoC Complexity

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

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System in Package (SiP)

Target is low power devices

ChallengesHigh yield with low test cost

Standardized test strategy for mini-systems

Potential test solutionsDesign for die, debug and system test

Per die BIST

KGD with minimal post test“KGD” defined as Functional

and Structural good?

Simple

Complex

Test and Test Equipment – 2010 December Conference – Makuhari, Japan

●　●　●　●　　　　　　　　　　●　●　●　●

●　●　　　　　　　　　　　　　　　　　　　　●　●

Substrate thickness: 0.16

Ball diameter: 0.4 mmBall pitch: 0.8 mm

1.0

Mold resin thickness on top of die: 0.10 mm

Die attach thickness

　 0.015

TSV

0.025mm

Embedded

Typical SiP in 2010Typical SiP in 2010From Assembly and packaging TWG

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Fault Tolerant Devices “Bad but Good”

Many future devices will be Fault Tolerant“Adapt or Repair”

Homogeneous multi-core device…not all cores need be goodIdentify with “Smart kernel” or continuous

test……Ignore the bad core…Fix (run slower or tailor operations)

MemoryAllow or correct bad bits / blocksBackground memory checkerWear leveling

Image sensors without the “perfect” imageWhat is perfect?

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Prober Characteristics

Many changes / additions from 2008 tables

Probe card dimensions

Test head weight

Temperature accuracy

450mm wafer support

Chuck leakage

Planarity

Etc.

Solutions exist until 2014

2009

2008DRIVERS

Full wafer test

Device Power

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Specialty Devices

LCD driversForm factor of 30mm x 1.5mm

Long bond pads on 20um centers

Image sensorsMicro lens check with pupil test

3 axis MEMS AccelerometerConsumer drop/rotate applications

Probing　pad　10x120　um

Image　sensor　structure　cross　section

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Test and Test Equipment – 2010 December Conference – Makuhari, Japan

Thanks!