Test Data Generation for LRU Cache-Memory

Testing

Evgeny KornikhinMoscow State UniversityInstitute for System Programming of RAS

testing by test programs

add r1,r2,r3sub r4, r1, r2lw r5, r1, 0lui r2, r1, r4

assembly program( test program )

microprocessor

Y/N

test program generation

model of microprocessorcoverage oftest situations anddependencies (r-w, r-r)

test templates

test programs

add r1,r2,r3 @ overflowlw r4, r3, c @ hit

mov r2, 0xFFadd r1,r2,r3lw r4, r3, 0

(logical form)

(executable form)

test program generation

model of microprocessorcoverage oftest situations anddependencies (r-w, r-r)

test templates

test programs

add r1,r2,r3 @ overflowlw r4, r3, c @ hit

mov r2, 0xFFadd r1,r2,r3lw r4, r3, 0

(logical form)

(executable form)

R4000

add load

args test situations

rd rs rt overflow regular

...

cache

test program generation

model of microprocessorcoverage oftest situations anddependencies (r-w, r-r)

test templates

test programs

add r1,r2,r3 @ overflowlw r4, r3, c @ hit

mov r2, 0xFFadd r1,r2,r3lw r4, r3, 0

(logical form)

(executable form)

R4000

add load

args test situations

rd rs rt overflow regular

...

cache

add specific initialization of microprocessor (registers and cache)

cache-hit

LOAD val, addr(val := memory[addr])

tag0' value

0'set №0

set №s

cache model

tag0'' value

0''

t' v' t'' v''

cache-hit

LOAD val, addr(val := memory[addr])

st

addr

tag0' value

0'

tag set

set №0

set №s

t = t' ort = t''

cache model

tag0'' value

0''

t' v' t'' v''

t = t''

cache-miss

LOAD val, addr(val := memory[addr])

st

addr

tag0' value

0'

tag set

set №0

set №s

t != t' andt != t''

cache model

tag0'' value

0''

t' v' t'' v''

nextlevel

evicted

problem again

LOAD x, y @ hitSTORE u, z @ missLOAD z, y @ hit

initial state of cacheand registers = ?

key idea

y {a,b,c}u {a,b,c} x = z

add ...load …sub …div …

LOAD x, y @ hit

? ?

? ?

? ?

cache model

test template

constraint

variable

variable

fully associative cache

N

x

x

y

y...

z

z

{x,y,z,...} - current state

cache-hit hit(t)

N

x

x

y

y...

z

z

t

t x,y,z...

cache-miss miss(t)

N

x

x

y

y...

z

z

t

t x,y,z...

new cache=x,y,z...t\?

cache-miss miss(t)→u

N

x

x

y

y...

z

z

t

t x,y,z...

new cache=x,y,z...t\u

ux,y,z...

lru(u)

hit x1

hit x2miss x3->x4hit x5miss t->u

u = x2{x3, x5} = L\{u}

counter(u)=min

L

lru(u)

hit x1

hit x2miss x3->x4hit x5miss t->u

u = x1{x2, x3, x5} = L\{u}

there are another cases

L

example

LOAD x, y @ hit

STORE u, z @ miss

LOAD z, y @ hit

N = 3

y

z→z0 z0

yz\z0

z0=\z0y

initialstate:

example

yz

z0

yz\z0

z0=\z0y

y

z

yz

common cache

z

xR(x)

R(y)

R(z)

x

y

z

y

common cache

hit(t)

miss(t)→u

t L

u Lt Lnew cache=L{t}\{u}R(t) = R(u)lru(u)

lru(u)

hit x1

hit x2

miss x3→x4

hit x5miss t→u

u = x2{x3, x5}∩R(u) = (L\{u})∩R(u)

example

x1,x2 {a1,a2,b1,b2,c1,c2}x3 {a1,a2,b1,b2,c1,c2}R(x3) = R(y3)x4 {a1,...,c2,x3}\{y3}x5 {a1,...,c2,x3}\{y3}

{y3} = ({a1,...,c2}\{x1,x2, y3})∩R(y3)

{y5} = ({a1...c2,x3}\{y3,y5, x3,x4})∩R(y5)y5 = x2

y3 = c2

solver

SAT modulo theories (bit-vectors)

Yices

x {a,b,c}y {a,b,c}x = z

(assert (or (= x a)(= x b)(= x c)))

(assert (and (/= y a)(/= y b)(/= y c)))

(check)

SMT

contacts

http://tesla-project.googlecode.com

http://hardware.ispras.ru

kornevgen@gmail.com